GRM42-6Y5V105Z16

Vendor:MURATAPackage Cooled:SMDD/C:09+

Development software for the CY7C371 is available from Cy press'sandsoftware packages. All of these products are based on the IEEE standard VHDL language. Cy press also actively supports third party design tools such as ABELt, CUPLt, MINC, and LOG/iCt. Please contact your lo cal Cypress representative for further information.

GRM42-6Y5V105Z16

Vendor:MURATAPackage Cooled:SMDD/C:09+

Development software for the CY7C371 is available from Cy press'sandsoftware packages. All of these products are based on the IEEE standard VHDL language. Cy press also actively supports third party design tools such as ABELt, CUPLt, MINC, and LOG/iCt. Please contact your lo cal Cypress representative for further information.

GRM42-6Y5V105Z16C505

D/C:4000

Isolated Frequency Input. Amplifies, Protects, Filters, and Isolates Analog Input. Generates an output of 0 to +5V proportional to input frequency. Model 5B45 accepts full-scale inputs from 500 Hz to 20 kHz. Model 5B46 accepts full-scale input from20 Khz to 275 kHz. Module circuitry can withstand 240v rms at the input screw- terminals. All 5B45 & 5B46 series modules are mix-and-match and Hot Swap...

GRM42-6Y5V105Z16D550

Vendor:MURATAPackage Cooled:06+D/C:101790

GRM42-6Y5V105Z16D550(1206-105Z)

GRM42-6Y5V105Z16U530

Serial data output; 5-V CMOS logic level tri-state output for output (status) register data; sends 16-bit status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless device is selected by CS = low, therefore, several ICs can operate on only one data output line only.

GRM42-6Y5V105Z25

Vendor:MURATAPackage Cooled:SMDD/C:09+

• Plastic package has Underwriters Laboratory Flammability Classification 94V-0 • Dual rectifier construction, positive center tap • Metal silicon junction, majority carrier conduction • Low power loss, high efficiency • Guardring for overvoltage protection • For use in low voltage, high frequency inverters, free wheeling, and polarity protection applications

GRM426Y5V106Z10

Vendor:MURATAPackage Cooled:06+

The CY7C1380D/CY7C1382D SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip En...

GRM42-6Y5V106Z10

Vendor:MURATAPackage Cooled:SMDD/C:09+

GRM42-6Y5V106Z10

Vendor:MURATAPackage Cooled:SMDD/C:09+

GRM426Y5V106Z10D530

GRM42-6Y5V106Z10D530

Vendor:MURATAD/C: 05+

FEATURES Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 12-Bit Resolution Excellent Spurious Free Dynamic Range Performance SFDR to Nyquist @ 5 MHz Output: 70 dBc Differential Current Outputs: 2 mA to 20 mA Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V Power-Down Mode: 25 mW @ 5 V On-Chip 1.20 V Reference Single +5 V or +3 V Supply Operation Package: 28-Lead SOIC and TSSOP Edge...

GRM42-6Y5V106Z10PT

GRM42-6Y5V106Z16C530

GRM42-6Y5V106Z25

Vendor:MURATAPackage Cooled:SMDD/C:09+

Hynix HYMD232726B(L)8J-J series is designed for high speed of up to 166MHz and offers fully synchronous opera- tions referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelin...

GRM42-6Y5V106Z6.3

Vendor:MURATAPackage Cooled:SMDD/C:09+

GRM42-6Y5V106Z6.3

Vendor:MURATAPackage Cooled:SMDD/C:09+

GRM42-6Y5V155Z16

GRM42-6Y5V155Z16U530

Vendor:MURATAPackage Cooled:06+D/C:101000

• State-of-the-art architecture Non-volatile data storage Low voltage operation: 3.0V (Vcc = 2.7V to 6.0V) Full TTL compatible inputs and outputs Auto increment for efficient data dump • Low voltage read operation Down to 2.7V • Hardware and software write protection Defaults to write-disabled state at power-up Software instructions for write-enable/disable • Ad...

GRM42-6Y5V156Z6.3H530

Vendor:MURATAPackage Cooled:06+D/C:102000

GRM42-6Y5V1E225Z

D/C:8000

Output Capacitors (Optional) For applications with load transients (sudden changes in load current), regulator response will benefit from an external output capacitance. The recommended output capacitance of 100 µF will allow the module to meet its transient response specification (see product data sheet). For most applications, a high quality computer-grade aluminum electrolytic capacitor is ad...

GRM42-6Y5V223Z50

TAOperating free-air temperatureC4085C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

GRM42-6Y5V224M50D530

Vendor:SIEMESPackage Cooled:01+D/C:N/A

GRM42-6Y5V225Z10

Vendor:MURATAPackage Cooled:SMDD/C:09+

Auto Memory Store Function This function automatically locates and stores up to six stations, starting from the current point on the selected band. Press and hold the ATP button for more than 2 seconds to begin the ATP operation. After automatically storing the station, preset scan will begin, starting with preset number 1. Preset scanning will continue until it is canceled. • If ATP is started in th...

GRM42-6Y5V225Z10D530

Vendor:MURATAPackage Cooled:06+D/C:101500

GRM42-6Y5V225Z16

Vendor:MURATAPackage Cooled:SMDD/C:09+

3V & 5V operation micro-miniature size .120"x.120" no external biasing circuit required high directivity, 20 dB typ. wide bandwidth, 0.5 to 5.9 GHz low noise figure, 2.9 dB typ. (MNA-6) output power, up to +19 dBm typ. excellent repeatability low cost

GRM42-6Y5V225Z16

Vendor:MURATAPackage Cooled:SMDD/C:09+

3V & 5V operation micro-miniature size .120"x.120" no external biasing circuit required high directivity, 20 dB typ. wide bandwidth, 0.5 to 5.9 GHz low noise figure, 2.9 dB typ. (MNA-6) output power, up to +19 dBm typ. excellent repeatability low cost

GRM42-6Y5V225Z25

The CPU provides fast instruction (up to 10 MHz clock speed) execution and memory efficient input/output bit manipulation. The CPU connects to other internal functions over an 8-bit data bus and 24-bit address bus and dedicated control lines.

GRM42-6Y5V225Z25D500

Vendor:MURATAPackage Cooled:06+D/C:103000

GRM42-6Y5V225Z50D500

Vendor:MURATAPackage Cooled:06+D/C:109000

GRM42-6Y5V226Z10

Vendor:MURATAPackage Cooled:SMDD/C:09+

3.1 Manchester Decoder and PLL The Manchester decoder uses a PLL to extract the clock and NRZ data from the received Manchester signals. The PLL is locked to the internally generated 5MHz clocks during idle time and switched to the incoming data at the start of the packet detection. The decoder also detects the IDL condition of the incoming data by switching off CRS whenever the data stays unchanged longer t...

GRM42-6Y5V226Z6.3

Vendor:MURATAPackage Cooled:SMDD/C:09+

The Electrical Sub-Assembly (ESA) consists of a double-sided printed circuit board on which a BiCMOS Integrated Circuit (IC) and various surface-mount passive circuit elements are attached. The IC contains an LED driver and a receiver that provides a single output channel, RXD.

GRM426Y5V334Z25521

Vendor:murataPackage Cooled:murataD/C:dc00

GRM42-6Y5V334Z50

GRM42-6Y5V335Z10

GRM42-6Y5V335Z10D530

Vendor:MURATAPackage Cooled:06+D/C:100158

GRM42-6Y5V335Z16

Vendor:MURATAPackage Cooled:1206-335Z

The basic unit of logic on the ispLSI 2096VL device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. C7 (see Figure 1). There are a total of 24 GLBs in the ispLSI 2096VL device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB co...

GRM42-6Y5V335Z16D530

Vendor:MURATAPackage Cooled:06+D/C:100894

Stanford Microdevices GRM42-6Y5V335Z16D530 is a high performance cascadeable 50-ohm amplifier designed for operation at voltages as low as 3.4V. This RFIC uses the latest Silicon Germanium Heterostructure Bipolar Transistor (SiGe HBT) process featuring 1 micron emitters with FT up to 50 GHz.

GRM42-6Y5V335Z16D539

Vendor:MURATAPackage Cooled:06+D/C:100218

GRM42-6Y5V335Z16PT

Vendor:MURATAD/C:02+

The ISL6527 provides simple, single feedback loop, voltage- mode control with fast transient response. The output voltage can be regulated to as low as the provided external reference. A fixed frequency oscillator reduces design complexity, while balancing typical application cost and efficiency.

GRM42-6Y5V335Z16PT

Vendor:MURATAD/C:02+

The ISL6527 provides simple, single feedback loop, voltage- mode control with fast transient response. The output voltage can be regulated to as low as the provided external reference. A fixed frequency oscillator reduces design complexity, while balancing typical application cost and efficiency.

GRM42-6Y5V335Z50D500

Vendor:MURATAPackage Cooled:06+D/C:100804

GRM42-6Y5V-474Z-16

GRM42-6Y5V474Z50

Vendor:MURATAPackage Cooled:SMDD/C:09+

The MCP6275s VCM for op amp B (pins VOUTA/VINB+ and VINBC) is VSS + 100 mV. The current at the MCP6275s VINBC pin is specified by IB only. This specification does not apply to the MCP6275s VOUTA/VINB+ pin. The MCP6275s VINBC pin (op amp B) has a common mode range (VCMR) of VSS + 100 mV to VDD C 100 mV. The MCP6275s VOUTA/VINB+ pin (op amp B) has a voltage range specified by VOH and VOL.

GRM42-6Y5V474Z50

Vendor:MURATAPackage Cooled:SMDD/C:09+

The MCP6275s VCM for op amp B (pins VOUTA/VINB+ and VINBC) is VSS + 100 mV. The current at the MCP6275s VINBC pin is specified by IB only. This specification does not apply to the MCP6275s VOUTA/VINB+ pin. The MCP6275s VINBC pin (op amp B) has a common mode range (VCMR) of VSS + 100 mV to VDD C 100 mV. The MCP6275s VOUTA/VINB+ pin (op amp B) has a voltage range specified by VOH and VOL.

GRM426Y5V475Z10

Vendor:murataPackage Cooled:murataD/C:dc97

The SN74CBT16210C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT16210C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state.

GRM42-6Y5V475Z10

Vendor:MURATAPackage Cooled:SMDD/C:09+

In the absence of confirmation by device specification sheets,SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs,data books,etc.Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. Internet address for Electronic Components Group http://sharp-world.com/ecg/

GRM42-6Y5V475Z16

Vendor:MURATAPackage Cooled:SMDD/C:09+

• When the processor power supply voltage drops below the reset threshold, the reset output is driven active, in less than 40µs (TD1). Reset is maintained active for a time period (TD2), after the Vcc rises above the threshold voltage.

GRM42-6Y5V475Z16

Vendor:MURATAPackage Cooled:SMDD/C:09+

• When the processor power supply voltage drops below the reset threshold, the reset output is driven active, in less than 40µs (TD1). Reset is maintained active for a time period (TD2), after the Vcc rises above the threshold voltage.

GRM42-6Y5V475Z25

Vendor:MURATAPackage Cooled:SMDD/C:09+

GRM42-6Y5V475Z25

Vendor:MURATAPackage Cooled:SMDD/C:09+

GRM42-6Y5V475Z25C250

Vendor:MURATAPackage Cooled:1206

GRM42-6Y5V475Z50

Vendor:MURATAPackage Cooled:SMDD/C:09+

GRM42-6Z5U103M050BL

GRM42-6Z5U224M50

Vendor:MURATAPackage Cooled:SMDD/C:09+

GRM42-6Z5U473M050BL

GRM42-6Z5U473M50PT

Hot SwapTM Controller for Positive and Negative Supplies Supply Tracking Mode 2.7V to 16.5V Operation Analog Current Limit with Foldback Allows Safe Board Insertion and Removal from a Live Backplane Open-Collector Power Good Comparators Automatic Retry or Latchoff After a Current Fault Dual Undervoltage Lockout Comparator Inputs Current Fault Indication

GRM42-6Z5U683M50

GRM42A5C3F050DW01L

Vendor:MURATAPackage Cooled:SMDD/C:09+

GND (Pin 10): Signal Ground. The oscillator, slew control circuitry and the internal regulator are referred to signal ground. Internally, signal ground is tied to substrate and the exposed backside of the device. Connect the GND pin to the ground plane and keep the connection free of large currents.

GRM42A5C3F100JW01L

Vendor:MURATAPackage Cooled:SMDD/C:09+

GRM42A5C3F100JW01L is a high performance current mode PWM controller specifically designed for off−line and DC−to−DC converter applications. The device requires very few external components and offers designer additional protection for better system reliability. The device features a trimmed oscillator for precise Duty Cycle control, accurate bandgap voltage reference, high gain error ...

GRM42A5C3F120JW01L

Vendor:MURATAPackage Cooled:SMDD/C:09+

Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate condi- tions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test condi- tions, refer to the Electrical Characteristics section. The guaranteed specifi- cations apply only for the cond...

GRM42A5C3F120JW01L

Vendor:MURATAPackage Cooled:SMDD/C:09+

Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate condi- tions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test condi- tions, refer to the Electrical Characteristics section. The guaranteed specifi- cations apply only for the cond...

GRM42A5C3F150JW01L

Vendor:MURATAPackage Cooled:SMDD/C:09+

The MAPI-400+100 is an extension of the Motorola MAPI-400 interface that is used on the Motorola M•Core products. An additional 100 pin connector was added to support the additional general purpose Input/Output pins from the Port Replacement Unit of the EVB555.

GRM42A5C3F150JW01L

Vendor:MURATAPackage Cooled:SMDD/C:09+

The MAPI-400+100 is an extension of the Motorola MAPI-400 interface that is used on the Motorola M•Core products. An additional 100 pin connector was added to support the additional general purpose Input/Output pins from the Port Replacement Unit of the EVB555.

GRM42A5C3F180J

GRM42A5C3F180JW01L

Vendor:MURATAPackage Cooled:SMDD/C:09+

This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.04 / Oct.01Hynix Semiconductor

GRM42A5C3F220JW01L

Vendor:MURATAPackage Cooled:SMDD/C:09+

The HIP6601B drives the lower gate in a synchronous rectifier to 12V, while the upper gate can be independently driven over a range from 5V to 12V. The HIP6603B drives both upper and lower gates over a range of 5V to 12V. This drive-voltage flexibility provides the advantage of optimizing applications involving trade-offs between switching losses and conduction losses. The HIP6604B can be configured as...

GRM42A5C3F270J

GRM42A5C3F270JW01L

Vendor:MURATAPackage Cooled:SMDD/C:09+

The disk drive adapter functions of W83877TF include a floppy disk controller compatible with the industry standard 82077/765, data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, interrupt and DMA logic. The wide range of functions integrated into the W83877TF greatly reduces the number of components required for interfacing with...

GRM42A5C3F270JW01L

Vendor:MURATAPackage Cooled:SMDD/C:09+

The disk drive adapter functions of W83877TF include a floppy disk controller compatible with the industry standard 82077/765, data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, interrupt and DMA logic. The wide range of functions integrated into the W83877TF greatly reduces the number of components required for interfacing with...

GRM42A5C3F330JW01L

Vendor:MURATAPackage Cooled:SMDD/C:09+

Protect Register Disable (PRDS) The PRDS instruction is a ONE TIME ONLY instruction which renders the Protect Register unalterable in the future Therefore the specified registers become PERMANENTLY protected against data changes As in the PRWRITE in- struction the PRE and PE pins must be held high while loading the instruction and after loading the PRDS instruc- tion the PRE and PE pins become dont care...

GRM42A5C3F330JW01L

Vendor:MURATAPackage Cooled:SMDD/C:09+

Protect Register Disable (PRDS) The PRDS instruction is a ONE TIME ONLY instruction which renders the Protect Register unalterable in the future Therefore the specified registers become PERMANENTLY protected against data changes As in the PRWRITE in- struction the PRE and PE pins must be held high while loading the instruction and after loading the PRDS instruc- tion the PRE and PE pins become dont care...

GRM42A5C3F390J

GRM42A5C3F390JW01L

Vendor:MURATAPackage Cooled:SMDD/C:09+

Note A: Characteristic data has been developed from actual products tested at 25C. This data is considered typical data for the Converter. Note B: SOA curves represent the conditions at which internal components are at or below the manufacturers maximum operating temperatures. Derating limits apply to modules soldered directly to a 4 in. 4 in. double-sided PCB with 1 oz. copper.

GRM42A5C3F390JW01L

Vendor:MURATAPackage Cooled:SMDD/C:09+

Note A: Characteristic data has been developed from actual products tested at 25C. This data is considered typical data for the Converter. Note B: SOA curves represent the conditions at which internal components are at or below the manufacturers maximum operating temperatures. Derating limits apply to modules soldered directly to a 4 in. 4 in. double-sided PCB with 1 oz. copper.

GRM42A5C3F470JW01L

Vendor:MURATAPackage Cooled:SMDD/C:09+

The SG6846 is especially designed for SMPS with surge-current output. It is incorporated with a two-level OCP function. Besides the cycle-by-cycle current limiting, if the switching current is higher than 2/3 of the peak-current threshold for a delay time, over-current protection will be activated such that the SG6846 will be totally shutdown. Other protection functions include: AC input brownout pr...

GRM42A7U3F101JW31L

Vendor:MURATAPackage Cooled:SMDD/C:09+

The ispClock5500s PLL and divider systems supports the synthesis of clock frequencies differing from that of the reference input through the provision of programmable input and feedback dividers. A set of five post-PLL V-divid- ers provides additional flexibility by supporting the generation of five separate output frequencies. Loop feedback may be taken from the output of any of the ...

GRM42A7U3F101JW31L

Vendor:MURATAPackage Cooled:SMDD/C:09+

The ispClock5500s PLL and divider systems supports the synthesis of clock frequencies differing from that of the reference input through the provision of programmable input and feedback dividers. A set of five post-PLL V-divid- ers provides additional flexibility by supporting the generation of five separate output frequencies. Loop feedback may be taken from the output of any of the ...

GRM42A7U3F270JW31L

Vendor:MURATAPackage Cooled:SMDD/C:09+

Propagation delay, clock to modulus control MC Programming Inputs Clock high time, tCH Clock low time, tCL Enable set-up time, tES Enable hold time, tEH Data set-up time, tDS Data hold time, tDH Clock rise and fall times High level threshold Low level threshold Hysteresis Phase Detector Digital phase detector propagation delay Gain programming resistor, RB Hold capacitor, CH Programmi...

GRM42A7U3F270JW31L

Vendor:MURATAPackage Cooled:SMDD/C:09+

Propagation delay, clock to modulus control MC Programming Inputs Clock high time, tCH Clock low time, tCL Enable set-up time, tES Enable hold time, tEH Data set-up time, tDS Data hold time, tDH Clock rise and fall times High level threshold Low level threshold Hysteresis Phase Detector Digital phase detector propagation delay Gain programming resistor, RB Hold capacitor, CH Programmi...

GRM42A7U3F330JW31L

Vendor:MURATAPackage Cooled:SMDD/C:09+

The LM4040 utilizes fuse and zener-zap reverse breakdown voltage trim during wafer sort to ensure that the prime parts have an accuracy of better than 0.1% (A grade) at 25˚C. Bandgap reference temperature drift curvature correction and low dynamic impedance ensure stable reverse break- down voltage accuracy over a wide range of operating tem- peratures and currents. Also available is the LM4041...

GRM42A7U3F390JW31L

Vendor:MURATAPackage Cooled:SMDD/C:09+

When used as a movement Auto Shut-Off module, several timing options are available. All timings are derived from the on chip oscillator and have thus the same tolerance. If the module is left immobile for a time longer than TASO the auto shut-off function becomes active. There is also an additional time period TADI. This time is valid only in the vertical state and determines the time between shut-off and t...

GRM42A7U3F470JW31L

Vendor:MURATAPackage Cooled:SMDD/C:09+

Bt8110B offers internal ROM 24 or 32 full-duplex channel capacity (48 or 64 channels with two processors) 2-, 3-, 4- and 5-bit quantization dynamically selectable on a channel-by-channel, frame-by-frame basis Transparent channel operation Two control modes available: microprocessor and hardware. Direct framer interface for both T1 and E1 signal formats Supports the optimal RESET function described in ...

GRM42A7U3F470JW31L

Vendor:MURATAPackage Cooled:SMDD/C:09+

Bt8110B offers internal ROM 24 or 32 full-duplex channel capacity (48 or 64 channels with two processors) 2-, 3-, 4- and 5-bit quantization dynamically selectable on a channel-by-channel, frame-by-frame basis Transparent channel operation Two control modes available: microprocessor and hardware. Direct framer interface for both T1 and E1 signal formats Supports the optimal RESET function described in ...

GRM42A7U3F560JW31L

Vendor:MURATAPackage Cooled:SMDD/C:09+

The data stored in the data input register is cleared on any SELECT transition (low to high or high to low). It is also cleared when the program power voltage (VPP) is reduced from 18 V to VDD. Clearing the data input register does not affect the data latched in the RAM.

GRM42A7U3F680JW31L

Vendor:MURATAPackage Cooled:SMDD/C:09+

The software clock is a poor timekeeper. Any change in the interrupt-request rates causes the clock to gain or lose time. If the PC is left on for long periods of time, the software clock can be off by large amounts. A minute or more per day that the PC was left on is not an uncommon error rate. It is also possible for an ill-behaved software program to use the timer-counter for another purpose and change t...

GRM42A7U3F820J

GRM42A7U3F820JW31L

Vendor:MURATAPackage Cooled:SMDD/C:09+

TMIN = -40C and TMAX = +85C. Typical values are at TA = 25C, clock frequency = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V differential, transformer coupled inputs, -1dBFS, ISET = 56.2kΩ, internal voltage reference, and LDVS buffer current at 3.5mA per channel, unless otherwise noted.

GRM42C0G220J50P

GRM42COG101J50P

GRM42D1X3F100JY02L

Vendor:MURATAPackage Cooled:SMDD/C:09+

The operation of the MQ photoelectric sensor area reflective type is explained in Fig. 5. After the output from the 2 PSD elements is added, the I/V value is converted and the logarithm deter- mined. By subtraction, the distance sig- nal in (I1/I2) is obtained. This can be optionally set, and with the distance adjustment control, comparison with the produced value can be made to detect whether t...

GRM42D1X3F100JY02L

Vendor:MURATAPackage Cooled:SMDD/C:09+

The operation of the MQ photoelectric sensor area reflective type is explained in Fig. 5. After the output from the 2 PSD elements is added, the I/V value is converted and the logarithm deter- mined. By subtraction, the distance sig- nal in (I1/I2) is obtained. This can be optionally set, and with the distance adjustment control, comparison with the produced value can be made to detect whether t...

GRM42D1X3F120JY02L

Vendor:MURATAPackage Cooled:SMDD/C:09+

The GRM42D1X3F120JY02L has dedicated pins to indicate signal strength, carrier detect, and LOCK. Optional external resistors allow the carrier detect threshold level to be customized to the user's requirement. In addition, the GRM42D1X3F120JY02L provides an 'Output Eye Monitor Test' (OEM_TEST) for diagnostic testing of signal integrity after equalization, prior to reslicing. The serial clock outputs can also ...

GRM42D1X3F150J

GRM42D1X3F150JY02L

Vendor:MURATAPackage Cooled:SMDD/C:09+

Packaged in the SOD523 package this addition to the Zetex Low Leakage Schottky diode range offers an ideal low VF/IR performance combined with a low package height of 0.9mm making the device suitable for various converter, charger, and LED driver circuits.

GRM42D1X3F180JY02L

Vendor:MURATAPackage Cooled:SMDD/C:09+

Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a compl...

GRM42D1X3F220JY02L

Vendor:MURATAPackage Cooled:SMDD/C:09+

The GRM42D1X3F220JY02L is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive l...

GRM42D1X3F270J

GRM42D1X3F270JY02L

Vendor:MURATAPackage Cooled:SMDD/C:09+

The SN65LVCP40 combines a pair of 1:2 buffers with a pair of 2:1 multiplexers (mux). Selectable switch-side loopback supports system testing. System interconnects and serial backplane applications of up to 4 Gbps are supported. Each of the two independent channels consists of a transmitter with a fan-out of two, and a receiver with a 2:1 input multiplexer.

GRM42D1X3F330JY02L

Vendor:MURATAPackage Cooled:SMDD/C:09+

Thus, the first step in designing the antenna circuit is to measure the bandwidth. Figure 17 shows an example for the test circuit. The RF signal is coupled into the bar antenna by inductive means, e.g., a wire loop. It can be measured by a simple oscilloscope using the 10:1 probe. The input capacitance of the probe, typically about 10 pF, should be taken into consideration. By varying the fre- quency...