GA75LS120K

Vendor:IR

On a semi-log plot (as shown in the HP catalog) the current graph will be a straight line with inverse slope 2.3 x 0.026 = 0.060 volts per cycle (until the effect of RS is seen in a curve that droops at high current). All Schottky diode curves have the same slope, but not necessarily the same value of current for a given voltage. This is determined by the saturation current, IS, and is related to th...

GA75LS60U

Vendor:IRPackage Cooled:75A/600V/IGBT/2U

The LM2936 ultra-low quiescent current regulator features low dropout voltage and low current in the standby mode. With less than 15 µA quiescent current at a 100 µA load, the LM2936 is ideally suited for automotive and other battery operated systems. The LM2936 retains all of the features that are common to low dropout regulators including a low dropout PNP pass device, short circuit prote...

GA75LS60U

Vendor:IRPackage Cooled:75A/600V/IGBT/2U

The LM2936 ultra-low quiescent current regulator features low dropout voltage and low current in the standby mode. With less than 15 µA quiescent current at a 100 µA load, the LM2936 is ideally suited for automotive and other battery operated systems. The LM2936 retains all of the features that are common to low dropout regulators including a low dropout PNP pass device, short circuit prote...

GA75TS120U

Care must also be taken to minimize the capacitance to ground seen by the amplifiers inverting input. The larger this capacitance, the worse the gain peaking, resulting in pulse overshoot and possible instability. To this end, it is recommended that the ground plane be removed under traces connected to pin 2, and connections to pin 2 should be kept as short as possible.

GA76C8128ALLFW70

Vendor:LGSPackage Cooled:1000

GA800DD60U

Vendor:IR

The 74HC/HCT4094 are 8-stage serial shift registers having a storage latch associated with each stage for strobing data from the serial input (D) to the parallel buffered 3-state outputs (QP0 to QP7). The parallel outputs may be connected directly to common bus lines. Data is shifted on the positive-going clock (CP) transitions.

GA8257-101

Vendor:GLOBESPAPackage Cooled:N/AD/C:09+

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

GA8257-101-001D

Vendor:GLOBESPAPackage Cooled:QFPD/C:08+09+

compatible with 5.0V systems. When VCCIO pins are connected to a 3.3V source, the input voltage levels are compatible with both 5.0V and 3.3V systems, while the output voltage levels are compatible with 3.3V systems. There will be an additional timing delay on all output buffers when operating in 3.3V I/O mode. The added flexibility of 3.3V I/O capability is available in commercial and industrial temperature ...

GA8532P

Package Cooled:92D/C:1943

Type 1 Configuration Access C If the Bus Number field of CONFADDR is not 0, a Type 1 Configuration is performed on PCI bus. The CONFADDR[23:2] is mapped directly to AD[23:2]. AD[1:0] are driven to 01 to indicate a Type 1 Configuration cycle. All other AD lines are driven to 0.

GA8532P

Package Cooled:92D/C:1943

Type 1 Configuration Access C If the Bus Number field of CONFADDR is not 0, a Type 1 Configuration is performed on PCI bus. The CONFADDR[23:2] is mapped directly to AD[23:2]. AD[1:0] are driven to 01 to indicate a Type 1 Configuration cycle. All other AD lines are driven to 0.

GA88023AT-133

Vendor:GSIPackage Cooled:QFPD/C:08+09+

The UCC5672 Multi-Mode Low Voltage Differential and Single Ended Ter- minator is both a single ended terminator and a low voltage differential ter- minator for the transition to the next generation SCSI Parallel Interface (SPI-3). The low voltage differential is a requirement for the higher speeds at a reasonable cost and is the only way to have adequate skew budgets.

GA901-2MC

GA9102-2MC

Vendor:TQSPackage Cooled:PLCC

RESET/POWER-DOWN: With RP » low, the device is reset, any current operation is aborted and device is put into the deep power down mode. When the power is turned on, RP » pin is turned to low in order to return the device to default con- figuration. When the 3/5 » pin is switched, or when the power transition is occurred, or at the power on/off, RP » is required to stay low in ord...

GA9152-01-A

Vendor:CONEXANTPackage Cooled:QFPD/C:08+09+

The VSC7924 is designed to operate with a maximum junction temperature of 125C. The rise from the case to junction is determined by the power dissipation of the device. The power dissipation is determined by the VSS current plus the operating IMOD and IBIAS currents.

GA9252-203-001D

Vendor:GLOBESPAPackage Cooled:06+D/C:800

3. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 4. Line regulation is defined as the change in output voltage for a change in input voltage. Load regulation is defined as the change in output voltage for a change in output load current at a constant temperature. The limits for line and load regulation are contained within the ...

GA-9830

Vendor:GammaPackage Cooled:SOP14D/C:2007+

GAA30337AAA-10T1S

GAAB938408

Vendor:NSPackage Cooled:SOP-20D/C:00-01+/SX

GAAB938408MML/SMLV01

Maximum Recurrent Peak Reverse Voltage Maximum RMS Voltage Maximum DC Blocking Voltage Maximum Average Forward Rectified Current Maximum Overload Surge 8.3ms Single Half Sine-Wave Typical Junction Capacitance (Note 1) Typical Thermal Resistance Operating Temperature Range Storage Temperature Range Maximum Forward Voltage @ IF =3.0A (Note 2) Maximum Reverse Current at TA =25 Maximum Reverse Cu...

GAAB938578

Vendor:NSPackage Cooled:SOP-20D/C:00+

GAAB939511

Vendor:NSPackage Cooled:SOP-20D/C:0106/SX

Half-duplex, isolated RS-485 transceiver PROFIBUS®-compliant ANSI EIA/TIA 485-A and ISO 8482: 1987(E) compliant 20 Mbps data rate 5 V or 3 V operation (VDD1) High common-mode transient immunity: >25 kV/s Isolated DE status output Receiver open-circuit, fail-safe design Thermal shutdown protection 50 nodes on bus Safety and regulatory approvals

GAAB944689V.06

Vendor:NSPackage Cooled:SOP-28D/C:00+

GAAB944778

Vendor:NSPackage Cooled:SOP-20D/C:01+

GAAL20V8B-25LP

Vendor:LATTICEPackage Cooled:06+D/C:DIP-24

GAB1L03F1228

Vendor:KYOCERAD/C:97

GAC16V8D

Vendor:LATTICED/C:07+

GAC16V8D

Vendor:LATTICED/C:07+

GAC16V8D-15QJ

Vendor:LATPackage Cooled:PLCCD/C:0223+

The device powers on in the read mode. Command sequences are used to place the device in other operation modes such as program and erase. The device has the capability to protect the data in any sector. Once the data protection for a given sector is enabled, the data in that sector cannot be changed using input levels between ground and VCC. The device is segmented into two memory planes. Reads from...

GAC16V8D-15QJ

Vendor:LATPackage Cooled:PLCCD/C:0223+

The device powers on in the read mode. Command sequences are used to place the device in other operation modes such as program and erase. The device has the capability to protect the data in any sector. Once the data protection for a given sector is enabled, the data in that sector cannot be changed using input levels between ground and VCC. The device is segmented into two memory planes. Reads from...

GAC22V10D-25QJ

GADZ00X 110773

Package Cooled:RQFP-64D/C:98

GAEC72952000

Vendor:STMPackage Cooled:SOP-28D/C:00+

GAGO7-1VR150M/AT

Vendor:富士通

GAHK82A2V0AA11

Vendor:SPECTEKPackage Cooled:QFND/C:06+

GAIC4M-T2

Reading from the device is accomplished by taking Chip En- able (CE) and Output Enable (OE) LOW while forcing the write enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O 8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O 9 to I/O16. See the truth table at the back of this data sheet f...

GAJ16V8D-15LP

Vendor:GALPackage Cooled:DIPD/C:2005

GAJ432

Vendor:JATPackage Cooled:SOT-252D/C:05+

Hynix HYMD132725B(L)8-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

GAL1110E-40SC

Vendor:3086

GAL1110E-40SC

Vendor:3086

GAL1-21

Vendor:R.HPackage Cooled:SOT-89D/C:05+

The DG534A is a digitally selectable 4-channel or dual 2-channel multiplexer. The DG538A is an 8-channel or dual 4-channel multiplexer. On-chip TTL-compatible address decoding logic and latches with data readback are included to simplify the interface to a microprocessor data bus. The low on-resistance and low capacitance of the these devices make them ideal for wideband data multiplexing and video and...

GAL1-4X

GAL1-6

GAL162VBC-15LJ

Package Cooled:06+D/C:800

GAL162VBD-5LJ

Package Cooled:06+D/C:800

GAL1-66

GAL168D-15LP

Vendor:LATTICEPackage Cooled:DIPD/C:05+

GAL16C8B-15LP

Vendor:LATTICEPackage Cooled:DIP-20D/C:06+

SMT Assembly Reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., IR or vapor phase reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. Components with a low mass, such as the...

GAL16C8D-15LJ

Vendor:LATTICED/C:NO

The entire power stage of the PA03 may be disabled using one of the circuits shown in Figure 1. There are many applications for this function. One is a load protection based on power delivered to the load or thermal rise. Another one is conservation of power when using batteries. The control voltage requirements accom- modate a wide variety logic drivers. 1. CMOS operating at +5V can drive the control...

GAL16L8D-10LJ

Vendor:LATTICEPackage Cooled:PLCC20

The P/R input is latched by the falling edge of the CE pin. A HIGH level selects a Playback cycle while a LOW level selects a Record cycle. For a Record cycle, the address inputs provide the starting address and recording continues until PD or CE is pulled HIGH or an overflow is detected (i.e. the chip is full). When a Record cycle is termi- nated by pulling PD or CE HIGH, an End-Of-Mes- sage (EOM) marker i...

GAL16LV80-15LJ

GAL16LV8C

Package Cooled:1000

The device employs Analog Devices iCoupler technology to combine a 3-channel isolator, a three-state differential line driver, and a differential input receiver into a single package. The logic side of the device is powered with either a 5 V or a 3 V supply, and the bus side uses an isolated 5 V supply.

GAL16LV8C-10LJ

*This part may also be used in Pollution Degree 3 environments where the rated mains voltage is 300 V rms (per DIN VDE 0110). **Refer to the front of the optocoupler section of the current catalog for a more detailed description of VDE 0884 and other product safety requirements.

GAL16LV8C10LJN

The PIC12CE67X devices have 128 bytes of RAM, 16 bytes of EEPROM data memory, 5 I/O pins and 1 input pin. In addition a timer/counter is available. Also a 4- channel high-speed 8-bit A/D is provided. The 8-bit res- olution is ideally suited for applications requiring low- cost analog interface, e.g. thermostat control, pressure sensing, etc.

GAL16LV8C-15LJ

Vendor:LATTICEPackage Cooled:PLCC

The first character of the part number suffix determines the device operating temperature range. Suffix EC is for the automotive and industrial temperature range of -40C to +85C. Suffix LC is for the automotive and military temperature range of -40C to +150C. Three package styles provide a magnetically optimized package for most applications. Suffix CLT is a miniature SOT89/TO-243AA transistor package ...

GAL16LV8C7LJ

Vendor:N/APackage Cooled:N/AD/C:08+09+

If the A5, A1, A0 address line inputs are LOW then the IDT72V8985 Internal Control Register is addressed (see Table 2). If A5 input line is high, then the remaining address input lines are used to select the 32 possible channels per input or output stream. As explained in the Control Register description, the address input lines and the Stream Address bits (STA) of the Control register give the user the c...

GAL16LV8C-LJ

The F193 is a 4-bit binary synchronous up down (revers- ible) counter It contains four edge-triggered flip-flops with internal gating and steering logic to provide master reset individual preset count up and count down operations A LOW-to-HIGH transition on the CP input to each flip-flop causes the output to change state Synchronous switching as opposed to ripple counting is achieved by driving the st...

GAL16LV8D

Vendor:LATTICEPackage Cooled:554D/C:N/A

Description: The NTE5452 through NTE5458 are sensitive gate 4 Amp SCRs in a TO202 type package designed to be driven directly with IC and MOS devices. These reverseCblocking triode thyristors may be switched from offCstate to conduction by a current pulse applied to the gate terminal. They are de- signed for control applications in lighting, heating, cooling, and static switching relays.

GAL16LV8D

Vendor:LATTICEPackage Cooled:554D/C:N/A

Description: The NTE5452 through NTE5458 are sensitive gate 4 Amp SCRs in a TO202 type package designed to be driven directly with IC and MOS devices. These reverseCblocking triode thyristors may be switched from offCstate to conduction by a current pulse applied to the gate terminal. They are de- signed for control applications in lighting, heating, cooling, and static switching relays.

GAL16LV8D3LJ

Package Cooled:N/AD/C:00+

• Sub-micron CMOS Process C High-speed logic and Interconnect C Low power consumption • Systems-Oriented Features C IEEE 1149.1-compatible boundary-scan logic support C Programmable output slew rate (2 modes) C Programmable input pull-up or pull-down resistors C 12-mA sink current per output C 24-mA sink current per output pair

GAL16LV8D-5JL

Vendor:LATTICEPackage Cooled:PLCC-20D/C:5

The e1217X is an integrated circuit in CMOS silicon gate technology for analog watches. It consists of a 32-kHz oscillator, frequency dividers down to 1/64 Hz, output pulse formers and push-pull motor drivers. Integrated capacitors are provided (select- able mask option) for tuning of the crystal. Low current consumption and high oscillator stability are enabled by an on-chip voltage regulator.

GAL16LV8D5LJ

Vendor:LATTICEPackage Cooled:746D/C:02+

These miniature surface mount MOSFETs low RDS(on) assure minimal power loss and conserve energy, making these devices ideal for use in space sensitive power management circuitry. Typical applications are dcCdc converters and power management in portable and batteryCpowered products such as computers, printers, PCMCIA cards, cellular and cordless telephones. • Low RDS(on) Provides Higher Efficiency ...

GAL16LV8D-5LJ

Vendor:LATTICEPackage Cooled:PLCC20D/C:05+

The 420LE/B series is a two stage transient voltage protector providing primary and secondary protection against lightning, inductive switching and electrostatic discharge (ESD) transient threats. The first stage diverts the transient current through the ground terminal return path and the second stage clamps the voltage to a safe level without interruption of service.

GAL16LV8D-7LJ

Vendor:LATTICEPackage Cooled:PLCC-20D/C:06+

DESCRIPTION The HCC40160B, 40161B, 40162B, 40163B (ex- tended temperature range) and HCF40160B, 40161B, 40162B, 40163B (intermediate tempera- ture range) are monolithic integrated circuits, avail- able in 16-lead dual in line plastic or ceramic package and plastic micropackage. HCC/HCF40160B, 40161B, 40162B and 40163B are 4-bit synchronous programmable counters. The CLEAR function of the HCC/HCF40162...

GAL16LV8ZD

Vendor:LATTICEPackage Cooled:SMDD/C:08+

Note 2: CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at no output loading and operating at 50% duty cycle. (See Figure 2 .) CPD is related to ICCD dynamic operating current by the expression: ICCD = (CPD) (VCC) (fIN) + (ICC static)

GAL16LV8ZD-15QJ

Vendor:LATTICEPackage Cooled:PLCC20D/C:06+

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

GAL16LV8ZD-15QJ

Vendor:LATTICEPackage Cooled:PLCC20D/C:06+

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

GAL16LV8ZD-25QJ

Memories C 8 to 32K dual voltage High Density Flash (HD- Flash) or ROM with read-out protection capa- bility. In-Application Programming and In- Circuit Programming for HDFlash devices C 384 to 1K bytes RAM C HDFlash endurance: 100 cycles, data reten- tion: 20 years at 55C Clock, Reset And Supply Management C Clock sources: crystal/ceramic resonator os- cillators, internal RC oscillator, and b...

GAL16V8(PLCCATF16V8B-15JC)01

Vendor:ATLD/C:1

GAL16V8/25LP

GAL16V80

D/C:02+

IE, VEC, trr, Qrr, diE/dt represent characteristics of the anti-parallel, emitter to collector free-wheel diode. Pulse width and repetition rate should be such that the device junction temp. (Tj) does not exceed Tjmax rating. Junction temperature (Tj) should not increase beyond 150C. Pulse width and repetition rate should be such as to cause negligible temperature rise. B = (InR1-InR2)/(1/T1-1/T2)R1 : Re...

GAL16V80

D/C:02+

IE, VEC, trr, Qrr, diE/dt represent characteristics of the anti-parallel, emitter to collector free-wheel diode. Pulse width and repetition rate should be such that the device junction temp. (Tj) does not exceed Tjmax rating. Junction temperature (Tj) should not increase beyond 150C. Pulse width and repetition rate should be such as to cause negligible temperature rise. B = (InR1-InR2)/(1/T1-1/T2)R1 : Re...

GAL16V805-10LNC

Vendor:GALPackage Cooled:N/AD/C:9+

Added Package Pins to GPIO Table in Section 8. Removed reference to pin group 9 in Table 10-5. Replacing TBD Typical Min with values in Table 10-17. Editing grammar, spelling, consistency of language throughout family. Updated values in Regulator Parameters, Table 10-9, External Clock Operation Timing Requirements Table 10-13, SPI Timing, Table 10-18, ADC Parameters, Table 10-24, and IO Loading Coefficients...

GAL16V80-7LP

Vendor:LatticePackage Cooled:00+D/C:DIP-20

GAL16V810LJ

GAL16V8-10LNC

Vendor:NSPackage Cooled:DIP-20D/C:9206

Fully static operation and Tri-state outputs TTL compatible inputs and outputs Low power consumption Battery backup(L/LL-part) - 2.0V(min) data retention • Standard pin configuration - 32pin 525mil SOP - 32pin 400mil TSOP-II (Standard and Reversed)

GAL16V8-10LNC

Vendor:NSPackage Cooled:DIP-20D/C:9206

Fully static operation and Tri-state outputs TTL compatible inputs and outputs Low power consumption Battery backup(L/LL-part) - 2.0V(min) data retention • Standard pin configuration - 32pin 525mil SOP - 32pin 400mil TSOP-II (Standard and Reversed)

GAL16V8-10LVC

Vendor:PLCCPackage Cooled:NSCD/C:04+

• Drives N-channel High-Side and Low-Side MOSFETs in a synchronous buck configuration • Internal Adaptive Shoot-Through Protection • High Switching Frequency (> 500kHz) C 30ns Output Rise/Fall Times w/3000pF load C 20ns Propagation Delay • 12V High-Side and 12V Low-Side Drive • OD input for Output Disable C allows for synchronization with PWM controller R...

GAL16V8-15

Vendor:800D/C:N/A

The input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data is written into the FIFO on every rising edge of WCLK when WEN is asserted. The output port is controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data is read from the FIFO on every rising edge of RCLK when REN is asserted. An Output Enable (OE) input is provided for three-state control of the o...

GAL16V8-15J

GAL16V8-15LJ

D/C:08+/09+

The bq2060 uses a fully differential, dynamically bal- anced voltage-to-frequency converter (VFC) for charge measurement and a sigma delta analog-to-digital con- verter (ADC) for battery voltage, current, and tempera- ture measurement.

GAL16V8-15LJS

GAL16V8-15LNC

Vendor:NSPackage Cooled:DIPD/C:06+

The MAX1978/MAX1979 are the smallest, safest, most accurate complete single-chip temperature controllers for Peltier thermoelectric cooler (TEC) modules. On-chip power FETs and thermal control-loop circuitry minimize external components while maintaining high efficiency. Selectable 500kHz/1MHz switching frequency and a unique ripple-can- cellation scheme optimize component size and efficiency while reducing ...

GAL16V8-15LP

Vendor:LATTICEPackage Cooled:DIP/20

Short-circuit current is internally limited. The device responds to a sustained overcurrent condition by turning off after a tON delay. The device then stays off for a period, tOFF, that is 40 times the tON delay. The device then begins pulsing on and off at the tON/tOFF duty cycle of 2.5%. This drastically reduces the power dissipation during short circuit such that heat sinking, if at all required, must...

GAL16V8-15LPS

Vendor:LATTICEPackage Cooled:DIP20D/C:2007+

The MAX5069A evaluation kit (EV kit) is a fully assembled and tested circuit board that contains a high-efficiency, 120W isolated push-pull DC-DC converter. The circuit is configured for a +12V output voltage and provides up to 10A of output current. The circuit can be powered from either a +36V to +72V or -36V to -72V DC source, as used in the telecom/datacom markets, industrial environments, or in automoti...

GAL16V8-20LNC

Vendor:NSPackage Cooled:DIP/20

1. 4-channel(4 Form A) of RF Photo- MOS Relays 2. SO package 16-pin type in super miniature design The device comes in a super-miniature SO package measuring (W)10.37 (L)4.4 (H)2.1mm (W) .408(L).173 (H).083inch approx. 50% of the foot- print size of 8-pin(2-channel) type.

GAL16V8-20LNC

Vendor:NSPackage Cooled:DIP/20

1. 4-channel(4 Form A) of RF Photo- MOS Relays 2. SO package 16-pin type in super miniature design The device comes in a super-miniature SO package measuring (W)10.37 (L)4.4 (H)2.1mm (W) .408(L).173 (H).083inch approx. 50% of the foot- print size of 8-pin(2-channel) type.

GAL16V8215QJ

Note 1: Specifications to -40C are guaranteed by design and not production tested. All typical values are guaranteed by design characterization and are not production tested. Note 2: Tested with TA = +25C, DVDD = 3.3V, and all peripherals inactive except for port pins. Note 3: These numbers are guaranteed by design and are not tested. Note 4: Can be calculated as (fHFXIN / 6). Note 5: Can be calculated as 6...

GAL16V82-15QS

Interrupt Select (active high, input with internal pull-down). When 16/68# pin is at logic 1 for Intel bus interface, this pin can be used in conjunction with MCR bit-3 to enable or disable the INT A- D pins or override MCR bit-3 and enable the interrupt outputs. Interrupt outputs are enabled continuously by making this pin a logic 1. Making this pin a logic 0 allows MCR bit-3 to enable and disable the ...

GAL16V8-25

Vendor:800D/C:N/A

Notes: 1. See XPLA3 family data sheet (DS012) for recommended operating conditions 2. See Figure 2 for output drive characteristics of the XPLA3 family. 3. This parameter guaranteed by design and characterization, not by testing. 4. See Table 1, Figure 1 for typical values. 5. This parameter measured with a 16-bit, loadable up/down counter loaded into every function block, with all outputs disabled and ...

GAL16V8-25HC1

Vendor:PLCC-20Package Cooled:STD/C:04+

A common ground is required between the input and the output voltages. The input voltage must remain typically 2.0V above the output voltage even during the low point on the Input ripple voltage. XX = these two digits of the type number indicate voltage. * = Cin is required if regulator is located an appreciable distance from power supply filter. ** = Co is not needed for stability; however, it d...

GAL16V8-25LJ

Vendor:LATTICEPackage Cooled:PLCCD/C:1988

Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. Port 2 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. The operation of port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for ...

GAL16V8-25LJ

Vendor:LATTICEPackage Cooled:PLCCD/C:1988

Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. Port 2 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. The operation of port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for ...

GAL16V8-25LNC

Vendor:NSPackage Cooled:DIP/20

NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-perform...

GAL16V825LP

Package Cooled:2000

8. ENC This block converts between NTSC and PAL. A digital technique in which 4fSC is created from FSC is adopted, and the clock system is unified into a single system. To create the composite video signal, clock rate conversion is also applied to the Y signal and the signals are mixed digitally. The sync signal can also be mixed digitally.

GAL16V8-25LVC

Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is determined by device characterization but is not production tested.

GAL16V8-25QJ

Vendor:3086

Note 5: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On Resistance of the switch and the load capacitance, when driven by an ideal voltage source (zero output impedance).

GAL16V8-25QP

Vendor:LATTICEPackage Cooled:DIP/20

- Input pin for current sensing. Using the sum of drain-source voltages of the MOSFET M1 and the MOSFET M2 (voltage between CS and GND), it senses discharge current during normal mode and detects whether charge current is present during power-down mode. It also used to detect whether load is connected during overcharge mode.

GAL16V8-25QVC

Vendor:NSD/C:05+

"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any...

GAL16V8-30LCM

Vendor:GALPackage Cooled:50D/C:N/A

GAL16V8-35LP

Vendor:LATTICEPackage Cooled:DIP

Input Voltage Range: 3.0V to 5.5V Regulated 5V Output 250mA Output Current with a 3.6V input 400mA Pulsed Output Current (up to 500ms duration) 60µA (typ.) Quiescent Current PFM Regulation Inductor-less solution: requires only 3 small capacitors < 1µA Typical Shutdown Current 10-pin LLP Package (No Pullback): 3mm x 3mm x 0.75mm