H11A5.300W

Vendor:fairchildPackage Cooled:DIP-6D/C:09+

Built-in power save circuit Built-in current limit circuit Built-in thermal shutdown circuit (TSD) Built-in hall bias Built-in FG signal output circuit Built-in rotational direction detecting circuit Built-in protection circuit for reverse rotation Built-in short brake circuit Built-in variable-regulator Built-in 4-CH balanced transformerless (BTL) driver Built-in BTL mute circuit (CH1/2, CH3 an...

H11A5.3S

Vendor:fairchildPackage Cooled:SOP-6D/C:09+

• Message bit rates up to 1 Mbps • Conforms to CAN 2.0B ACTIVE Specification • Fully backward compatible with PIC18XXX8 CAN modules • Three modes of operation: - Legacy, Enhanced Legacy, FIFO • Three dedicated transmit buffers with prioritization • Two dedicated receive buffers • Six programmable receive/transmit buffers • Three full 29-bit acceptan...

H11A5.3SD

Vendor:fairchildPackage Cooled:SOP-6D/C:09+

Power-Good Threshold (Input): Analog reference used to specify the PWRGD threshold. When the voltage at this pin exceeds its threshold, VTH, PWRGD is asserted high. An external resistive divider network is used to determine the output voltage level at which VTH is exceeded. See the Functional Description for further detail. When the PWRGD signal is not utilized, this input should be tied to VOUT.

H11A53S

Vendor:FAIRCHI

Notes: 1.Input & output negative-voltage ratings may be exceeded if the input and output curent rating are observed. 2.Output positive-voltage rating may be exceeded up to 4.6V maximum if theoutput current rating is observed. 3.The package thermal impedance is calculated in accordance with JESD 51.

H11A5FM

Vendor:fairchildPackage Cooled:SOP-6D/C:09+

puts are controlled by an Output Enable (OEn) input. When OEn is LOW, the outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high imped- ance mode but this does not interfere with entering new data into the inputs.

H11A5FM

Vendor:fairchildPackage Cooled:SOP-6D/C:09+

puts are controlled by an Output Enable (OEn) input. When OEn is LOW, the outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high imped- ance mode but this does not interfere with entering new data into the inputs.

H11A5FR2M

Vendor:fairchildPackage Cooled:SOP-6D/C:09+

The H11A5FR2M aligns the recovered data clock frequency to the reference clock on each channel by means of a clock tolerance compensation circuit and internal FIFO that inserts or drops 20-bit IDLE codes as needed in the interpacket gap (IPG). In synchronous mode, the received data for all channels is aligned to a single receive data clock that is a buffered version of the reference clock.

H11A5FR2VM

Vendor:fairchildPackage Cooled:SOP-6D/C:09+

Note 1: Do not exceed switch-to-input voltage limitation. Note 2: For switch currents between 1A and 5A, maximum switch on voltage can be calculated via linear interpolation. Note 3: By setting the feedback pin (FB) to 2.5V, the VC pin is forced to its low clamp level and the switch duty cycle is forced to zero, approximating the zero load condition. Note 4: For proper regulation, total voltage from VIN to...

H11A5FR2VM

Vendor:fairchildPackage Cooled:SOP-6D/C:09+

Note 1: Do not exceed switch-to-input voltage limitation. Note 2: For switch currents between 1A and 5A, maximum switch on voltage can be calculated via linear interpolation. Note 3: By setting the feedback pin (FB) to 2.5V, the VC pin is forced to its low clamp level and the switch duty cycle is forced to zero, approximating the zero load condition. Note 4: For proper regulation, total voltage from VIN to...

H11A5FVM

Vendor:fairchildPackage Cooled:SOP-6D/C:09+

Digital Ground. All digital signals are referred to this pin. +5V Analog Power Supply. These pins should be connected to ground via a 0.1 µF capacitor. All power supply pins should be connected together. +5V Digital Power Supply. +5V Analog Power Supply. This pin should be connected to ground via a 0.1 µF capacitor. All power supply pins should be connected together. Capacitor Noise Filter...

H11A5M

Vendor:FAIRCHILDPackage Cooled:07+PBD/C:10000

When pin CPH exceeds 5.1V, the IR21592 enables the over-current protection and the next cycle where the CS pin exceeds the internal threshold of 1.6V the half-bridge is disabled. The VCO voltage decreases to a minimum value and the IR21592 starts to decreases the frequency to a minimum frequency which is set by the external resistor on pin FMIN (RFMIN) and the current sensing resistor RCS. In this way it ...

H11A5-M

Vendor:FATRCHILDPackage Cooled:N/AD/C:0505+

FAN Tachometer inputs are digital inputs with an acceptable range of 0V to 5V, and are responsible for measuring the FAN s tachometer pulse periods. FAN_TAC1 and FAN_TAC2 are included with programmable divisors, and can be used to measure different fan speed ranges. FAN_TAC3 is included in the fixed divisor, and can only be used in the default range.

H11A5SR2M

Vendor:FAIRCHILDPackage Cooled:07+PBD/C:10000

The microchip is essentially the high efficiency micro-controller, made under the high fidelity CMOS C technology. The microchip contains the programs ROM with the capacity of 4,096 bytes, the embedded data RAM with the capacity of 128 bytes, 32 input/output lines, two 16-bit timers / counters, guard timer, interrupts system with five vectors and two priority levels, the serial port for expansion of inpu...

H11A5T

Vendor:INFINEON Package Cooled:08+D/C:3228

Reverse Current Forward Current Maximum Output Voltage (LM4041-ADJ) Power Dissipation (TA = 25˚C) (Note 2) M3 Package Z Package M7 Package Storage Temperature Lead Temperature M3 Packages Vapor phase (60 seconds) Infrared (15 seconds) Z Package

H11A5T

Vendor:INFINEON Package Cooled:08+D/C:3228

Reverse Current Forward Current Maximum Output Voltage (LM4041-ADJ) Power Dissipation (TA = 25˚C) (Note 2) M3 Package Z Package M7 Package Storage Temperature Lead Temperature M3 Packages Vapor phase (60 seconds) Infrared (15 seconds) Z Package

H11A5TM

Vendor:FAIRCHILDPackage Cooled:07+PBD/C:10000

Reading from the device is accomplished by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table...

H11A617A

Vendor:FAIRCHILDPackage Cooled:07+PBD/C:10000

Enhanced Word Spotting capability (10 SI or 4 SD words) in parallel Noise robust Speaker Independent, Dependent & Continuous Listening recognition Speaker Verification (SVWS) C Noise robust voice biometric security High quality, 3.7-7.8 kbps speech synthesis & sound effects with Sensory SX synthesis technology 8 voice MIDI-compatible music synthesis coincident with speech; drum track feature enable...

H11A617A

Vendor:FAIRCHILDPackage Cooled:07+PBD/C:10000

Enhanced Word Spotting capability (10 SI or 4 SD words) in parallel Noise robust Speaker Independent, Dependent & Continuous Listening recognition Speaker Verification (SVWS) C Noise robust voice biometric security High quality, 3.7-7.8 kbps speech synthesis & sound effects with Sensory SX synthesis technology 8 voice MIDI-compatible music synthesis coincident with speech; drum track feature enable...

H11A617A.300W

• Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation • Programmable code protection • In-Circuit Serial ProgrammingTM (ICSPTM) via two pins

H11A617A.W

The current source provides a closely regulated zener current, which determines the slope of the references voltage vs. temperature function. By trimming the zener current a lower drift over temperature can be achieved. But since the voltage vs. temperature function is nonlinear this compensation technique is not well suited for wide temperature ranges.

H11A617B

Vendor:FAIRCHILDPackage Cooled:07+PBD/C:10000

This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation. In this case, depending on the bus size, the most significant byte or word written to Port A is read from Port B first. A LOW on BE will select Little-Endian operation. In this case, the least significant byte or word written to Port A is read from Port B first. After Master Reset, this pin selects the timing mod...

H11A617B.300

Note 15: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.

H11A617BS

Vendor:FAIRCHILD?Package Cooled:SOP4D/C:05+

Once the FIFO is full (indicated by FSTAT1 and FSTAT2 both = "1"), it can be read by dropping the FIFO READ line (pin 10) to a logic "0" and then applying a series of 15 rising edges to the read line. Since the first data word is already present at the FIFO output, the first read command (the first rising edge applied to FIFO READ) will bring data from the second conversion to the o...

H11A814B

Vendor:QTCPackage Cooled:48484D/C:00+

If the wiper position of the DS1809 is incremented to an end-position, it will stay at that position until the device receives an opposite direction input pulse command over the UC or DC inputs. For example, if the wiper position is incremented to the RH terminal using the UC input control, it will stay at that position until UC is first deactivated, and then the DC input is activated to move the wiper positi...

H11A817

Vendor:FAIRCHILDPackage Cooled:07+PBD/C:10000

Designing for Very Fast Load Transients The transient response of the DC/DC converter has been characterized using a load transient with a di/dt of 1 A/µs. The typical voltage deviation for this load transient is given in the data sheet specification table using the optional value of output capacitance. As the di/dt of a transient is increased, the response of a converters regu- lation circuit ul...

H11A817(Q)

The Hynix HYM7V65801B Q-Series are 8Mx64bits Synchronous DRAM Modules. The modules are composed of eight 4Mx16bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package and 2Kbit EEPROM in 8pin TSSOP package on a 144pin glass-epoxy printed circuit board. Three 0.1uF decoupling capacitors per each SDRAM are mounted on the PCB.

H11A817.300

Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested.

H11A8173SD

Vendor:FAIRCHILDPackage Cooled:07+PBD/C:10000

The special design also exhibits an improved insensitivity to inherent integrated circuit component mismatches as is evidenced by a 500-µV maximum offset voltage and 1.7-µV/C typical drift. Minimum common-mode rejection ratio and supply-voltage rejection ratio are 85 dB and 90 dB, respectively.

H11A817A

The SDRAM employs state-of-the-art technology for high performance, reliability, and low power. All inputs and outputs are synchronized with the CLK input to simplify system design and enhance use with high-speed microprocessors and caches.

H11A817A.300

as possible, between the VOUT1 pin and ground plane. Also connect the Schottky diode as close as possible to the VOUT1 pin to minimize trace resistance and EMI radiation. Sw (Bump D2): Drain connection of the internal power NMOS FET switch. (Figure 2: N1) Minimize the metal trace length and maximize the metal trace width connected to this pin to reduce EMI radiation and trace resistance.

H11A817A300

Vendor:FAIRCHILDPackage Cooled:07+PBD/C:10000

Jitter transfer refers to the portion of jitter allowed to transfer from input to output of the CDR, and jitter generation is that produced by the CDR itself. The ITU-T specs for these two parameters must be met for regenerators in a long-haul system, because at each stage the recovered clock enables transmission to the next regenerator, allowing jitter contributions to accumulate from regenerator to regene...

H11A817A300W

Vendor:FAIRCHILDPackage Cooled:07+PBD/C:10000

Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com- mands are masked when /CS is registered high. /CS provides for external bank selection on systems with multiple banks. /CS is considered part of the command code.

H11A817A3SD

Vendor:FAIRCHILDPackage Cooled:07+PBD/C:10000

A/D converters are calibrated by positioning their digital outputs exactly on the transition point between two adjacent digital output codes. This is accomplished by connecting LED's to the digital outputs and performing adjustments until certain LED's "flicker" equally between on and off. Other approaches employ digital comparators or microcontrollers to detect when the outputs change from o...

H11A817B .C

Vendor:FSCPackage Cooled:DIP-4

H11A817B FSC

H11A817B.300

Package Cooled:FairchildD/C:07+

TEMPERATURE COMPENSATION Figure 2 shows the typical output characteristics of the MPX12 series over temperature. The XCducer piezoresistive pressure sensor element is a semiconductor device which gives an electrical output signal proportional to the pressure applied to the device. This de- vice uses a unique transverse voltage diffused semiconduc- tor strain gauge which is sensitive to stresses prod...

H11A817B.3SD

Vendor:QTCPackage Cooled:SOP4D/C:98

(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A14). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A14).

H11A817B.C

Vendor:N/APackage Cooled:N/AD/C:08+09+

The SLIC performs 2 wire to 4 wire conversion by taking the 4 wire signal from an analog switch or voice CODEC, and converting it to a 2 wire differential signal at Tip and Ring. The 2 wire signal applied to tip and ring by the phone is converted to a

H11A817B.C

Vendor:N/APackage Cooled:N/AD/C:08+09+

The SLIC performs 2 wire to 4 wire conversion by taking the 4 wire signal from an analog switch or voice CODEC, and converting it to a 2 wire differential signal at Tip and Ring. The 2 wire signal applied to tip and ring by the phone is converted to a

H11A817B.C FSC

H11A817B300

Vendor:FARIPackage Cooled:DIP-4D/C:0225+

The 7640 group, an enhanced family of CMOS 8-bit microcontrollers, offers high-speed operation, large internal-memory options, and a wide variety of stan- dard peripherals. The series is code compatible with the 38000, 7200, 7400, and the 7500 series, and pro- vides many performance enhancements to the instruction set.

H11A817B300

Vendor:FARIPackage Cooled:DIP-4D/C:0225+

The 7640 group, an enhanced family of CMOS 8-bit microcontrollers, offers high-speed operation, large internal-memory options, and a wide variety of stan- dard peripherals. The series is code compatible with the 38000, 7200, 7400, and the 7500 series, and pro- vides many performance enhancements to the instruction set.

H11A817B300_NF098

Vendor:FAIRCHILDD/C:O9+

H11A817B3S

Vendor:ＦＡＩＲＣＨＩＬＤ

The H11A817B3S is a high precision, high throughput analog front end. True 16-bit p-p resolution is achievable with a total conversion time of 500 µs (2 kHz channel switching), making it ideally suitable for high resolution multiplexing applications.

H11A817C

Vendor:QTCPackage Cooled:SOPD/C:07+

The Am29DS323D family consists of 32 megabit, 1.8 volt-onl y flas h mem or y devices, o r g a n i ze d a s 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ0CDQ15; byte mode data appears on DQ0CDQ7. The device is designed to be programmed in-system with the stan- dard 1.8 volt VCC supply, and can also be programmed in standard EPROM programmers.

H11A817C FSC

H11A817C300_NF098

Vendor:FAIRCHILDD/C:O9+

H11A817C300_NF098

Vendor:FAIRCHILDD/C:O9+

H11A817C300W

Vendor:Fairchild

To validate the data transmitted from the bq2022, the host generates a CRC value from the data as they are received. This generated value is compared to the CRC value transmitted by the bq2022. If the two CRC values match, the transmission is error-free. The equivalent polynomial function of this CRC is X8 + X5 + X4 + 1. Details are found in the CRC Generation Section of this data sheet.

H11A817C3SD_NF098

H11A817C3SD-NFO FAI SOP 0631+

H11A817CS

Vendor:fscPackage Cooled:fscD/C:dc04

Call Progress Monitor and Group Listening - Adjust the Loudspeaking amplifier (gain, fre- quency response curve) without handsetconnec- tion in order to avoid influence of the handset microphone. - Adjust the Antiacoustic feedback efficiency.

H11A817CSD

Vendor:availPackage Cooled:FSCD/C:06+

• High current sink/source 25 mA/25 mA • Three external interrupts • Enhanced Capture/Compare/PWM (ECCP) module: - One, two or four PWM outputs - Selectable polarity - Programmable dead time - Auto-Shutdown and Auto-Restart - Capture is 16-bit, max resolution 6.25 ns (TCY/16) - Compare is 16-bit, max resolution 100 ns (TCY) • Compatible 10-bit, up to 13-channel Analog-to...

H11A817D

Vendor:FATRCHILDPackage Cooled:N/AD/C:0505+

Anode of the Biasing Diode that matches the thermal and process char- acteristics of the power transistor. Requires a high-RF-impedance, low- DC-impedance (e.g., inductor) connection to the transistor base (Pin 4). Current through the biasing diode (into Pin 3) is proportional to 1/15 the collector current in the transistor.

H11A817S

8-Pin SOIC switching controller with HICCUP current limiting reduces diode power dissipation to less than 1% of normal operation Soft-Start capacitor allows for smooth output voltage ramp up On-Board MOSFET Driver Fastest transient response of any controller method. (0 to 100% Duty Cycle in 100ns) 1% Internal Voltage Reference Internal Under-Voltage Lockout protects MOSFET during start-up

H11A817SD

• A variety of contact arrangements 2 Form A 2 Form B, 3 Form A 1 Form B, 4 Form A • Latching types available • High sensitivity in small size 100 mW pick-up and 200 mW nominal operating power • High shock and vibration resistance Shock: 50 G Vibration: 10 to 55 Hz at double amplitude of 3 mm .118 inch

H11A817X

Vendor:FAIRCHILDPackage Cooled:DIP-4P光藕D/C:6+

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

H11A817X.5632

H11A817X-5645D

Vendor:FAIRCHILDPackage Cooled:SOPD/C:0148+

H11A92

Vendor:FAIPackage Cooled:DIPD/C:08+

The test set described in this paper allows complete quanti- tative characterization of all dc operational amplifier param- eters quickly and with a minimum of additional equipment The method used is accurate and is equally suitable for lab- oratory or production test for quantitative readout or for limit testing As embodied here the test set is conditioned for testing the LM709 and LM101 amplifiers ho...

H11AA1.300

Vendor:fairchildPackage Cooled:DIP-6D/C:09+

This N-Channel power MOSFET is manufactured using the innovative UltraFET® process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in appl...

H11AA1.300

Vendor:fairchildPackage Cooled:DIP-6D/C:09+

This N-Channel power MOSFET is manufactured using the innovative UltraFET® process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in appl...

H11AA1.3SD

Vendor:fairchildPackage Cooled:SOP-6D/C:09+

UART channel A Receive Data or infrared receive data. Normal receive data input must idle HIGH. The infrared receiver pulses typically idles LOW but can be inverted by software control prior going in to the decoder, see MCR[6] and FCTR[2]. If this pin is not used, tie it to VCC or pull it high via a 100k ohm resistor.

H11AA1.SD

Vendor:fairchildPackage Cooled:SOP-6D/C:09+

Hynix HYMD564726(L)8-K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous opera- tions referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipel...

H11AA1-1152

Vendor:西门子Package Cooled:SMD-6D/C:9811

Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the ...

H11AA13SD

Vendor:FAIRCHI

The Altera enhanced configuration device is a single-device, high-speed, advanced configuration solution for very high-density FPGAs. The core of an enhanced configuration device is divided into two major blocks, a configuration controller and a flash memory. The flash memory is used to store configuration data for systems made up of one or more Altera FPGAs. Unused portions of the flash memory can be us...

H11AA1QTC

Package Cooled:5031D/C:92+

H11AA1SD

Vendor:FAIRCHI

The triple driver IC includes three non-inverted and current-limited output stages with an open collector. Common thermal shutdown protects the outputs against critical junction temperatures. Each output can sink a current of 20 mA, parallel output opera- tion is possible. The digital inputs have Schmitt-trigger function with pull-up resistors to 5 V.

H11AA1SD

Vendor:FAIRCHI

The triple driver IC includes three non-inverted and current-limited output stages with an open collector. Common thermal shutdown protects the outputs against critical junction temperatures. Each output can sink a current of 20 mA, parallel output opera- tion is possible. The digital inputs have Schmitt-trigger function with pull-up resistors to 5 V.

H11AA1SM

Vendor:FAIRCHILDPackage Cooled:07+PBD/C:10000

PACMAN™ POP™ Power247™ PowerSaver™ PowerTrench® QFET® QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ SILENT SWITCHER® SMART START™

H11AA1SM

Vendor:FAIRCHILDPackage Cooled:07+PBD/C:10000

PACMAN™ POP™ Power247™ PowerSaver™ PowerTrench® QFET® QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ SILENT SWITCHER® SMART START™

H11AA1T

Vendor:INFINEON Package Cooled:08+D/C:3228

Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and clock inhibit (CLK INH) is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH accomplishes clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. The para...

H11AA1W

Vendor:FAIRCHI

Package thermal resistance for the SOT-363 package is approxi- mately 100C/W, and the chip thermal resistance for these three families of diodes is approxi- mately 40C/W. The designer will have to add in the thermal resistance from diode case to ambient a poor choice of circuit board material or heat sink design can make this number very high.

H11AA2

The MX841 is specifically designed to be operated from a single cell battery source. The step-up voltage necessary for the constant current source to drive up to 5 white LEDs in series, or multiple strings of white LEDs, is achieved with minimal external components. (See Application Schematics on pages 1&4).

H11AA2.300

Vendor:fairchildPackage Cooled:DIP-6D/C:09+

When the outputs of two or more TMS27C512s or TMS27PC512s are connected in parallel on the same bus, the output of any particular device in the circuit can be read with no interference from the competing outputs of the other devices. To read the output of a single device, a low-level signal is applied to the E and G / VPP pins. All other devices in the circuit should have their outputs disabled by applyin...

H11AA2-M

Vendor:FATRCHILDPackage Cooled:N/AD/C:0505+

Stages In One Device Leading-Edge PFC, Trailing-Edge PWM Modulation for Reduced Ripple Built-In Sequencing of PFC and PWM Turn-On 2-A Source and 3-A Sink Gate Drive for Both PFC and PWM Stages Typical 16-ns Rise Time and 7-ns Fall Time into 1-nF Loads

H11AA2-M

Vendor:FATRCHILDPackage Cooled:N/AD/C:0505+

Stages In One Device Leading-Edge PFC, Trailing-Edge PWM Modulation for Reduced Ripple Built-In Sequencing of PFC and PWM Turn-On 2-A Source and 3-A Sink Gate Drive for Both PFC and PWM Stages Typical 16-ns Rise Time and 7-ns Fall Time into 1-nF Loads

H11AA2S

Vendor:FAIRCHI

Parameter DIFFERENTIAL INPUT PERFORMANCE DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth −3 dB Large Signal Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.01% Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE SFDR

H11AA3.300

Vendor:fairchildPackage Cooled:DIP-6D/C:09+

Serial Data present at the input is transferred to the shift register on the logic 0 to logic 1 transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUT- PUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform.

H11AA33S

Vendor:FAIRCHI

The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.

H11AA3M

Vendor:FAIRCHILDPackage Cooled:07+PBD/C:10000

1.3 INSTRUCTION SET In todays 8-bit microcontroller application arena cost/ performance, flexibility and time to market are several of the key issues that system designers face in attempting to build well-engineered products that compete in the marketplace. Many of these issues can be addressed through the manner in which a microcontrollers instruction set handles process- ing tasks. And thats why COP...

H11AA3S

Vendor:FAIRCHI

Hynix HYMD512G726(L)4M-K/H/L series is Low Profile registered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 128Mx72 high-speed memory arrays. Hynix HYMD512G726(L)4M-K/H/L series consists of eighteen 128Mx4 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD512G726(L)4M-K/H/L series provide a high performance 8-byte interfac...

H11AA3S

Vendor:FAIRCHI

Hynix HYMD512G726(L)4M-K/H/L series is Low Profile registered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 128Mx72 high-speed memory arrays. Hynix HYMD512G726(L)4M-K/H/L series consists of eighteen 128Mx4 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD512G726(L)4M-K/H/L series provide a high performance 8-byte interfac...

H11AA3SD

Vendor:FSCPackage Cooled:SOP-6PD/C:03+

Device operations are selected by entering standard JEDEC 8-bit command codes with conventional microprocessor timing into an on-chip CSM through I/O pins DQ0 C DQ7. When the device is powered up, internal reset circuitry initializes the chip to a read-array mode of operation. Changing the mode of operation requires a command code to be entered into the CSM. Table 1 lists the CSM codes for all modes of op...

H11AA3SR2M

Vendor:FAIRCHILDPackage Cooled:07+PBD/C:10000

• CMOS Process Technology • 1M x 16 bit Organization • TTL compatible and Tri-state outputs • Deep Power Down : Memory cell data hold invalid • Standard pin configuration : 48-FBGA • Data mask function by /LB, /UB

H11AA4

Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25C Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 C 2000-V Human-Body Model (A114-A) C 200-V Machine Model (A115-A) C 1000-V Charged-Device Model (C101)

H11AA4.300

Vendor:FAIPackage Cooled:dip-6D/C:07+

The UT51C164 is high speed 5V EDO DRAMs organized as 256K bit X 16 I/O and fabricated with the CMOS process. The UT51C164 offers a combination of unique features including : EDO Page Mode operation for higher bandwidth with Page Mode cycle time as short as 14ns. All inputs are TTL compatible. Input and output capacitance is significantly lowered to increase performance and minimize loading. These features m...

H11AA4.3S

Vendor:QTCPackage Cooled:SOIC-6/5.2mmD/C:9836+

Cellular Base Transceiver Station Transmit Channel C CDMA: W-CDMA, CDMA2000, IS-95 C TDMA: GSM, IS-136, EDGE/UWC-136 Baseband I and Q Transmit Input Interface: Quadrature Modulation for Interfacing With Baseband Complex Mixing ASICs Single-Sideband Up-Conversion Diversity Transmit Cable Modem Termination System

H11AA4.3S

Vendor:QTCPackage Cooled:SOIC-6/5.2mmD/C:9836+

Cellular Base Transceiver Station Transmit Channel C CDMA: W-CDMA, CDMA2000, IS-95 C TDMA: GSM, IS-136, EDGE/UWC-136 Baseband I and Q Transmit Input Interface: Quadrature Modulation for Interfacing With Baseband Complex Mixing ASICs Single-Sideband Up-Conversion Diversity Transmit Cable Modem Termination System

H11AA4.3SD

Vendor:fairchildPackage Cooled:SOP-6D/C:09+

PARAMETER VID Section DAC output voltage (note 1) DAC Output Line Regulation DAC Output Temp Variation VID Input LO VID Input HI VID input internal pull-up resistor to V5 Power Good Section Under voltage lower trip point Under voltage upper trip point UV Hysterises Over voltage upper trip point Over voltage lower trip point OV Hysterises Power Good Output LO Power Good Output HI Soft Start Sectio...

H11AA4.S

Vendor:fairchildPackage Cooled:SOP-6D/C:09+

NOTES: 3. It is recommended that the logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) should be at the same voltage and separate from each other. 4. The bypass capacitor should be located as close as possible to each power supply. 5. The FREFINPUT (pin 3) and PFD OUT (pin 4) terminals are input/output terminals preset for logic function respectively. In normal operation, the FR...

H11AA4300

Vendor:FAIRCHI

Drain-to-Source Breakdown Voltage 200 Gate Threshold Voltage …2.04.0 Gate-to-Source Leakage Forward100 Gate-to-Source Leakage Reverse-100 Zero Gate Voltage Drain Current25 Static Drain-to-Source … 0.100 On-State Resistance One Diode Forward Voltage …1.4

H11AA4300

Vendor:FAIRCHI

Drain-to-Source Breakdown Voltage 200 Gate Threshold Voltage …2.04.0 Gate-to-Source Leakage Forward100 Gate-to-Source Leakage Reverse-100 Zero Gate Voltage Drain Current25 Static Drain-to-Source … 0.100 On-State Resistance One Diode Forward Voltage …1.4

H11AA43S

Vendor:FAIRCHI

The ispLEVER® design tool from Lattice allows large complex designs to be efficiently implemented using the Latti- ceECP/EC family of FPGA devices. Synthesis library support for LatticeECP/EC is available for popular logic syn- thesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the Lattice...

H11AA43SD

Vendor:FAIRCHI

Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

H11AA4M

Vendor:FAIRCHILDPackage Cooled:07+PBD/C:10000

I ARM720T Processor ARM7TDMI CPU 8 KB of four-way set-associative cache MMU with 64-entry TLB Thumb code support enabled I Ultra low power 90 mW at 74 MHz typical 30 mW at 18 MHz typical 10 mW in the Idle State <1 mW in the Standby State I 48 KB of on-chip SRAM I MaverickKey™ IDs

H11AA4M

Vendor:FAIRCHILDPackage Cooled:07+PBD/C:10000

I ARM720T Processor ARM7TDMI CPU 8 KB of four-way set-associative cache MMU with 64-entry TLB Thumb code support enabled I Ultra low power 90 mW at 74 MHz typical 30 mW at 18 MHz typical 10 mW in the Idle State <1 mW in the Standby State I 48 KB of on-chip SRAM I MaverickKey™ IDs

H11AA4S

Vendor:FSC/QTCPackage Cooled:08+D/C:3000

Standard '245-Type Pinout Output Voltage Translation Tracks VCC Supports Mixed-Mode Signal Operation on All Data I/O Ports C 5-V Input Down to 3.3-V Output Level Shift With 3.3-V VCC C 5-V/3.3-V Input Down to 2.5-V Output Level Shift With 2.5-V VCC 5-V-Tolerant I/Os With Device Powered Up or Powered Down Bidirectional Data Flow With Near-Zero Propagation Delay Low ON-State Resistance (ron) Characteris...

H11AA4S

Vendor:FSC/QTCPackage Cooled:08+D/C:3000

Standard '245-Type Pinout Output Voltage Translation Tracks VCC Supports Mixed-Mode Signal Operation on All Data I/O Ports C 5-V Input Down to 3.3-V Output Level Shift With 3.3-V VCC C 5-V/3.3-V Input Down to 2.5-V Output Level Shift With 2.5-V VCC 5-V-Tolerant I/Os With Device Powered Up or Powered Down Bidirectional Data Flow With Near-Zero Propagation Delay Low ON-State Resistance (ron) Characteris...

H11AA4SD

Vendor:FAIRCHI

HT1623 is a peripheral device specially designed for I/O type MCU used to expand the display capability. The max. display segment of the device are 384 patterns (48´8). It also supports serial interface, buzzer sound, watchdog timer or time base timer functions. The HT1623 is a memory mapping and multi-function LCD controller. The software configuration feature of the