HCPL0931

Vendor:agiPackage Cooled:agiD/C:dc0546

• Stabilized power supply Provides power to the microprocessor. • Power on and clock off functions The power on function outputs a low level signal to the microprocessor for a fixed period when power is first applied. The clock off function outputs a RES signal to the microprocessor a fixed period after a runaway occurs.

HCPL-0931

Notes 1. Device is considered as a two terminal device: Pins 1,2 3 and 4 are shorted together and Pins 5,6,7 and 8 are shorted together. 2. Common mode transient immunity at output high is the maximum tolerable (positive) dVcm/dt on the leading edge of the com- mon mode impulse signal, Vcm, to assure that the output will remain high. Common mode transient immunity at output low is the maximum tolerable ...

HCPL0931-300E

Vendor:AVAGOD/C:07无铅

Lead Temperature (Soldering 10 sec )300 C Note Absolute maximum ratings indicate limits beyond which damage to the device may occur DC and AC electri- cal specifications are not ensured when operating the de- vice at absolute maximum ratings

HCPL-0945

Vendor:AGILENTPackage Cooled:04+D/C:5000

REGISTER HEX 09 PUNCTURE RATE ENABLE (R/W) Reset Value : Hex 10 (mode A) 0E0 (1) Puncture 1/2 enabled, (0) disabled 1E1 (1) Puncture 2/3 enabled, (0) disabled 2E2 (1) Puncture 3/4 enabled, (0) disabled 3E3 (1) Puncture 5/6 enabled, (0) disabled 4E4 (1) Puncture7/8 (mode A), 6/7 (mode B) (0) disabled 5 unused6 7

HCPL-0945

Vendor:AGILENTPackage Cooled:04+D/C:5000

REGISTER HEX 09 PUNCTURE RATE ENABLE (R/W) Reset Value : Hex 10 (mode A) 0E0 (1) Puncture 1/2 enabled, (0) disabled 1E1 (1) Puncture 2/3 enabled, (0) disabled 2E2 (1) Puncture 3/4 enabled, (0) disabled 3E3 (1) Puncture 5/6 enabled, (0) disabled 4E4 (1) Puncture7/8 (mode A), 6/7 (mode B) (0) disabled 5 unused6 7

HCPL-0945500

Vendor:AgilentPackage Cooled:07/08+D/C:1700

Two important wavelength ranges (windows 2 and 3) are in use for transmitting information over a fiber cable in telecommunication networks. Within an optical window, the signals benefit from a lower impact on quality (less dispersion) and less attenuation per unit of fiber length. The range between 1000nm and 1300nm, called the second optical window, is known for low dispersion-as low as 0dB. The range from...

HCPL-0945500

Vendor:AgilentPackage Cooled:07/08+D/C:1700

Two important wavelength ranges (windows 2 and 3) are in use for transmitting information over a fiber cable in telecommunication networks. Within an optical window, the signals benefit from a lower impact on quality (less dispersion) and less attenuation per unit of fiber length. The range between 1000nm and 1300nm, called the second optical window, is known for low dispersion-as low as 0dB. The range from...

HCPL-1001500

Vendor:AgilentPackage Cooled:N/AD/C:00+

The ÉlanSC300 microcontroller from AMD is part of the growing Élan family of mobile computing products, which leverage existing AMD core modules. The ÉlanSC300 microcontroller demonstrates the feasibil- ity of constructing highly integrated components built from standard cores and getting these products to mar- ket quickly.

HCPL-1005

Vendor:AVAGOPackage Cooled:DIP-8D/C:06+

loop timing applications to assure PLL tracking, especially during GR-253 jitter tolerance testing. The recommended maximum phase detector frequency for loop timing mode is 19.44MHz. The LOL pin should not be used during loop timing mode. When LOL is to be used for system health monitoring, the phase detector frequency should be 5MHz or greater. Low phase detector frequencies make LOL overly sensitive, and...

HCPL-1006W

Vendor:AVAGOPackage Cooled:DIP-8D/C:06+

Notes: 1. For codes not listed in the figure above, please refer to the respective datasheet or contact your nearest Agilent representative for details. 2. Bin options refer to shippable bins for a part number. Color and Intensity Bins are typically restricted to 1 bin per tube (exceptions may apply). Please refer to respective datasheet for specific bin limit information.

HCPL-1006W

Vendor:AVAGOPackage Cooled:DIP-8D/C:06+

Notes: 1. For codes not listed in the figure above, please refer to the respective datasheet or contact your nearest Agilent representative for details. 2. Bin options refer to shippable bins for a part number. Color and Intensity Bins are typically restricted to 1 bin per tube (exceptions may apply). Please refer to respective datasheet for specific bin limit information.

HCPL111

Vendor:AGILENTD/C:DIP

HCPL-1312

Vendor:AVAGOPackage Cooled:DIP-8D/C:07+

(21 Appropriatemeasures, such as fail-safe design and redundantdesign considering the safety design of the overall system and equipment,should be taken to ensure reliability and safety when this product is used for equipmentwhich demands high reliability and safety in function and precision, such as ;

HCPL-1366

Vendor:AgilentPackage Cooled:DIP/SOP

HCPL-1458

Vendor:AGILENTPackage Cooled:05+D/C:2035

FEATURES l Multi quantum wells (MQW) DFB Laser Diode module l Emission wavelength is in 1.55µm band l Polarization maintaining optical fiber pig-tail l Built-in optical isolator l Built-in thermal electric cooler l Butterfly package l With 2 photodiodes for wavelength monitor and optical output power monitor

HCPL1466

The plastic package carries Underwriters Laboratory Flammability Classification 94V-0 Fast switching for high efficiency Low reverse leakage High forward surge current capability High temperature soldering guaranteed: 250 C/10 seconds,0.375(9.5mm) lead length, 5 lbs. (2.3kg) tension

HCPL1466

The plastic package carries Underwriters Laboratory Flammability Classification 94V-0 Fast switching for high efficiency Low reverse leakage High forward surge current capability High temperature soldering guaranteed: 250 C/10 seconds,0.375(9.5mm) lead length, 5 lbs. (2.3kg) tension

HCPL-1466

Vendor:availPackage Cooled:AGILENTD/C:00+

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input ...

HCPL-1487

Vendor:AGILENTD/C:04+

The GS 702 transmitter controller has been designed in order to meet the requirements of replacement remote control makers. Its structure is based on Application Specific Programmable Micro-controller with a super parallel architecture implemented by means of CMOS EPROM technology.

HCPL-1510

Vendor:AVAGOPackage Cooled:SOP-4D/C:07+

(1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed.

HCPL158

Vendor:AGILENTD/C:DIP

HCPL-158

Vendor:AGILENTD/C:DIP

•Single +5V power supply •No clocks, no ref resh •Data-Hold on +2.0V power supply •Directly TTL compatible : all inputs and outputs •Three-state outputs : OR-tie capability •/OE prev ents data contention in the I/O bus •Common Data I/O •Battery backup capability •Low stand-by current .......... 0.05µA(ty p.)

HCPL-1620

HCPL-177K-100

RESET The RESET input pin when pulled low initializes the micro- controller Upon initialization the ports L and G are placed in the TRl-STATE mode The PC PSW and CNTRL regis- ters are cleared The data and configuration registers for ports L and G are cleared The external RC network shown in Figure 3 should be used to ensure that the RESET pin is held low until the power supply to the chip stabilizes

HCPL-177K-600

The ICL7106 and ICL7107 are high performance, low power, 3½ digit A/D converters. Included are seven segment decoders, display drivers, a reference, and a clock. The ICL7106 is designed to interface with a liquid crystal display (LCD) and includes a multiplexed backplane drive; the ICL7107 will directly drive an instrument size light emitting diode (LED) display. The ICL7106 and ICL7107 bring together...

HCPL181

HCPL-181-000E

Vendor:AVAGOD/C:07无铅

The IWORX (InterWORking element neXt genera- tion) IC controller is a multi service engine for line card applications in wireless access networks and media gateways. It transports ATM traffic over PDH and SDH based networks. Supporting speeds of up to 155 Mbit/s, IWORX enables the adaptation of voice, video and data traffic via AAL2. Shared location of 2G and 3G mobile networks for easy network migr...

HCPL181-000E

Vendor:AVAGOD/C:07无铅

NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VT...

HCPL181-000E

Vendor:AVAGOD/C:07无铅

NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VT...

HCPL-181-00AE

Package Cooled:08D/C:18000

During power-up and power-down, or in the event of overcurrent (OI) or overtemperture (OT), the latch inhibits the PWM gate, deactivating the gate drive circuits and shutting off the inverter. The relay control circuit delivers an on/off signal via an opto-isolator to the relay driver which controls the relay (K1). The relay contact is open during power-up, inserting the resistor R in series with the...

HCPL-181-00AE

Package Cooled:08D/C:18000

During power-up and power-down, or in the event of overcurrent (OI) or overtemperture (OT), the latch inhibits the PWM gate, deactivating the gate drive circuits and shutting off the inverter. The relay control circuit delivers an on/off signal via an opto-isolator to the relay driver which controls the relay (K1). The relay contact is open during power-up, inserting the resistor R in series with the...

HCPL-181-060E

Vendor:AVAGOD/C:08+

The DC/DC converter is a programmable topology synchronized Buck converter for todays continuous changing portable electronic market. The DC/DC converter provides flexibility of utilizing various battery configurations and chemistries such as NiCd, NiMH, or Li+ with an input voltage range of 2.7V to 6V. An additional flexibility is provided with topology programmability to power multiple loads such a...

HCPL-181-06BE

Vendor:AGID/C:07+

These devices have Type-1 and Type-2 receivers that detect the bus state with as little as 50 mV of differential input voltage over a common-mode voltage range of C1 V to 3.4 V. The Type-1 receivers exhibit 25 mV of differential input voltage hysteresis to prevent output oscillations with slowly changing signals or loss of input. Type-2 receivers include an offset threshold to provide a known output st...

HCPL-181-06CE

Vendor:AVAGOPackage Cooled:07+D/C:3000

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-Q7; UDM corresponds to the data on DQ8-Q15.

HCPL-181V

Vendor:AGILENTD/C:0337+

If the system designer needs more than 16 outputs with the features just described, using two or more zero-delay buffers such as PI6C2509Q, and PI6C2510Q, is likely to be impractical. The device- to-device skew introduced can significantly reduce the perfor- mance. Pericom recommends the use of a zero-delay buffer and an eighteen output non-zero-delay buffer. As shown in Figure 1, this combination produces a ...

HCPL-1930

Vendor:HPPackage Cooled:CDIP16D/C:8603

The HYS64/72D32000GU and HYS64/72D64020GU are industry standard 184-pin 8-byte Dual in- line Memory Modules (DIMMs) organized as 32M 64 and 64M 64 for non-parity and 32M x 72 and 64M x 72 for ECC main memory applications. The memory array is designed with 256Mbit Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect b...

HCPL-1931

Vendor:AGILENTD/C:03+

New P-Channel HEXFET Ò power MOSFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications.

HCPL1931200

HCPL-1931500

HCPL-1989

Vendor:AGILENTD/C:DIP

HCPL-1CS223

Vendor:AVAGOPackage Cooled:DIP-8D/C:06+

The CD54AC534/3A and CD54ACT534/3A are octal D-type, three-state, positive-edge triggered flip-flops that utilize the Harris Advanced CMOS Logic technology. The eight flip- flops enter data into their registers on the LOW-to-HIGH transition of the clock (CP). The Output Enable (OE) controls the three-state outputs and is independent of the register operation. When the Output Ena...

HCPL-2005

Vendor:AGILENTPackage Cooled:98+D/C:2035

The NE5534 and NE5534A are high-performance operational amplifiers combining excellent dc and ac characteristics. Some of the features include very low noise, high output-drive capability, high unity-gain and maximum-output-swing bandwidths, low distortion, and high slew rate.

HCPL-201

Vendor:AGILENTPackage Cooled:SOP8D/C:02+/03+

2.3V to 2.7V Operation SSTL_2 Class II style data inputs/outputs Differential CLK input RESET control compatible with LVCMOS levels Flow-through architecture for optimum PCB design Drive up to equivalent of 14 SDRAM loads Latch-up performance exceeds 100mA ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0) • Available in TSSOP package

HCPL-201

Vendor:AGILENTPackage Cooled:SOP8D/C:02+/03+

2.3V to 2.7V Operation SSTL_2 Class II style data inputs/outputs Differential CLK input RESET control compatible with LVCMOS levels Flow-through architecture for optimum PCB design Drive up to equivalent of 14 SDRAM loads Latch-up performance exceeds 100mA ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0) • Available in TSSOP package

HCPL-2020PLC

Vendor:HPPackage Cooled:DIPD/C:2005+

NOTES: (1) Binary Twos Complement coding. (2) Ratio of (DistortionRMS + NoiseRMS)/SignalRMS. (3) D/A converter output frequency/signal level (both left and right channels are on). (4) D/A converter sample frequency (8 x 44.1kHz; 8X oversampling per channel). (5) Ratio of NoiseRMS/SignalRMS. Measured using a 40kHz 3rd-order GIC (Generalized Immittance Converter) filter and an A-weighted filter. (6) Bipolar ...

HCPL-2051

HCPL211

Vendor:50000

DESCRIPTION The HOA0901 sensor consists of a dual channel IC detector and an IRED encased in a black thermoplastic housing. The device is typically used with an interrupter strip or disk (code wheel) to encode the rate and direction of mechanical motion. Applications include linear and rotary encoders; it is especially suited for the encoding function in an optical mouse. As the interruptive pattern ...

HCPL-211

Vendor:AGILENTPackage Cooled:SOP8D/C:98+/03+

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Defense Supply Center, Columbus, ATTN: DSCC-VAC, P.O. Box 3990, Columbus, OH 43216-5000, by using the Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

HCPL-216

Vendor:AGILENTPackage Cooled:SOP8D/C:03+

HCPL21E

Vendor:SOP-8Package Cooled:AGILENTD/C:2005+

This device is ideal for applications requiring level translation. When operated from a 3.3 V supply, level translation from 3.3 V inputs to 2.5 V outputs is allowed. Similarly, if the device is operated from a 2.5 V supply and 2.5 V inputs are applied, the device will translate the outputs to 1.8 V. In addition to this, a level translating select pin (SEL) is included. When SEL is low, VCC is reduced i...

HCPL2200

B2: Writing this bit to a 1 protects the upper page of memory. If this bit is set, memory locations F8h to FFh are configured for write-protection. B1: Writing this bit to a 1 protects the upper block of memory. If this bit is set, memory locations 80h to F7h are configured for write-protection. The upper page must be unlocked in order to modify the locking of this portion of memory. B0: Writing this bit t...

HCPL2200000E

Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and transmission line loads. Test conditions for the read cycle use output loading as shown in (a) of AC Test Loads, unless specified otherwise. 5. This part has a voltage regulator that steps down the voltage from 3V to 2V in...

HCPL-2200-000E

Vendor:AVAGOPackage Cooled:SOP-8D/C:08/07+

Double Baud rate bit. When set to a 1, the baud rate is doubled when the serial port is being used in either modes 1, 2 or 3. (Reserved) (Reserved) (Reserved) General-purpose flag bit. General-purpose flag bit. Power Down bit. Setting this bit activates power down operation. Idle mode bit. Setting this bit activates idle mode operation.

HCPL-2200-000E

Vendor:AVAGOPackage Cooled:SOP-8D/C:08/07+

Double Baud rate bit. When set to a 1, the baud rate is doubled when the serial port is being used in either modes 1, 2 or 3. (Reserved) (Reserved) (Reserved) General-purpose flag bit. General-purpose flag bit. Power Down bit. Setting this bit activates power down operation. Idle mode bit. Setting this bit activates idle mode operation.

HCPL2200-000E

Vendor:AVAGOD/C:07无铅

The accurate 30mV overcharging detection voltage ensures safe and full utilization charging. Three different specification values for overcharge protection voltage are provided for various protection requirements. The very low standby current drains little current from the cell while in storage.

HCPL-2200010

Vendor:AgilentPackage Cooled:N/AD/C:01+

Reference level for the relative attenuation arel of the TFS 282 A is the minimum of the pass band attenuation amin. The minimum of the pass band attenuation amin is defined as the insertion loss ae. The centre frequency fc is the arithmetic mean value of the upper and lower frequencies at the 3 dB filter attenuation level relative to the insertion loss ae. The nominal frequency fN is fixed on 282 MHz without ...

HCPL-2200-060E

The wiper settings are controllable through the I2C compatible digital interface, which can also be used to read back the present wiper register control word. The resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the RDAC1 latch.

HCPL-2200300

Vendor:AgilentPackage Cooled:07/08+D/C:5000

After the software data protections 3-byte command code is given, a byte load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. The 128 bytes of data must be loaded into each sector by the same procedure as outlin...

HCPL-2200300

Vendor:AgilentPackage Cooled:07/08+D/C:5000

After the software data protections 3-byte command code is given, a byte load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. The 128 bytes of data must be loaded into each sector by the same procedure as outlin...

HCPL-2200-300E

Vendor:AVAGOPackage Cooled:07+PBD/C:10000

HCPL2200-300E

Vendor:AVAGOD/C:07无铅

The purpose of this paper is to define the terms relating to aperture effects, to develop a mathematical framework to represent these effects, and to predict the errors that will be introduced into the sampled signal as a result of aperture effects.

HCPL2200-300E

Vendor:AVAGOD/C:07无铅

The purpose of this paper is to define the terms relating to aperture effects, to develop a mathematical framework to represent these effects, and to predict the errors that will be introduced into the sampled signal as a result of aperture effects.

HCPL-2200500

Vendor:AgilentPackage Cooled:07/08+D/C:5800

These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.

HCPL-2200500

Vendor:AgilentPackage Cooled:07/08+D/C:5800

These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.

HCPL-2200-500E

Vendor:AVAGOPackage Cooled:07+PBD/C:10000

Data sheet information is generally presented in the following sequence: • Device description • Absolute maximum ratings • Thermal data - thermal resistances • Characteristics, switching characteristics • Electrical characteristics • Dimensions (mechanical data) Additional information on device performance is pro- vided where necessary.

HCPL-2200-500E

Vendor:AVAGOPackage Cooled:07+PBD/C:10000

Data sheet information is generally presented in the following sequence: • Device description • Absolute maximum ratings • Thermal data - thermal resistances • Characteristics, switching characteristics • Electrical characteristics • Dimensions (mechanical data) Additional information on device performance is pro- vided where necessary.

HCPL2200-500E

Vendor:AVAGOD/C:07无铅

Note 8: Care should be taken to include the effects of self heating when setting the maximum output load current. The power dissipation of the LM27 would increase by 1.28mW when IOUT =3.2mA and VOUT =0.4V. With a thermal resistance of 250˚C/W, this power dissipation would cause an increase in the die temperature of about 0.32˚C due to self heating. Self heating is not included in the trip point ac...

HCPL-2200-Y

Vendor:HPPackage Cooled:DIP/8D/C:88+

The IOB, CLB, block SelectRAM, multiplier, and DCM ele- ments all use the same interconnect scheme and the same access to the global routing matrix. Timing models are shared, greatly improving the predictability of the perfor- mance of high-speed designs.

HCPL2201000E

This will result in an input to the crystal of 50% of the rail to rail output of X2. Usually this keeps the drive level into the crystal within the drive specifications of the crystal but the designer should verify this. Overdriving the crystal can cause damage.

HCPL2201-000E

Vendor:AVAGOD/C:07无铅

Logic and internal gate drive supply voltage Oscillator timing resistor input Oscillator timing capacitor input IC power and signal ground Low side gate driver output High voltage floating supply return High side gate driver output High side gate driver floating supply

HCPL2201-000E

Vendor:AVAGOD/C:07无铅

Logic and internal gate drive supply voltage Oscillator timing resistor input Oscillator timing capacitor input IC power and signal ground Low side gate driver output High voltage floating supply return High side gate driver output High side gate driver floating supply

HCPL-2201060

Note 1: TJ = +25 to 150 Note 2: Current is calculated based upon maximum allowable junction temperature. Package current limitation is 30A. Note 3: Repetitive rating; pulse width limited by maximum junction temperature. Note 4: ISD = 12.0A, di/dt 100A/µs, VDD BVDSS, TJ = +150 Note 5: Pulse width 250µs; duty cycle 2% Note 6: Essentially independent of operating temerpature.

HCPL-2201-060E

Vendor:AVAGOPackage Cooled:07+PBD/C:10000

One or more of the following United States patents apply: 4,454,488; 4,616,197; 4,670,681; and 4,760,352. Typically, equipment utilizing this device requires emissions testing and government approval, which is the responsibility of the equipment manufac- turer. 3. Applies over the specified range of operating temperature. 4. Applies over the specified range of operating power supply voltage. 5. The desig...

HCPL-2201300

Vendor:AgilentPackage Cooled:07/08+D/C:1300

The MSA-series is fabricated using HPs 10 GHz fT, 25 GHz f MAX, silicon bipolar MMIC process which uses nitride self-alignment, ion implantation, and gold metalli- zation to achieve excellent performance, uniformity and reliability. The use of an external bias resistor for temperature and current stability also allows bias flexibility.

HCPL2201300E

• International standard package • Moderate frequency IGBT and antiparallel FRED in one package • High current handling capability • Newest generation HDMOSTM process • MOS Gate turn-on - drive simplicity

HCPL-2201-300E

Vendor:AVAGOPackage Cooled:07+PBD/C:10000

Note: Most lens assemblies reverse the viewed scene onto the sensor array, which generally means that pin 1 should be located at the bottom of the p.c. board. To ensure correct display orientation, check the lens specification prior to laying out the printed circuit board.

HCPL-2201-300E

Vendor:AVAGOPackage Cooled:07+PBD/C:10000

Note: Most lens assemblies reverse the viewed scene onto the sensor array, which generally means that pin 1 should be located at the bottom of the p.c. board. To ensure correct display orientation, check the lens specification prior to laying out the printed circuit board.

HCPL2201-300E

Vendor:AVAGOD/C:07无铅

The Texas Instruments HCPL2201-300E and HCPL2201-300EA are TI PanelBus flat panel display products, part of a comprehensive family of end-to-end DVI 1.0 compliant solutions. Targeted primarily at desktop LCD monitors and digital projectors, the HCPL2201-300E/201A finds applications in any design requiring high-speed digital interface.

HCPL-2201500

Vendor:AgilentPackage Cooled:07/08+D/C:1300

The internal circuit is composed of 2 stages including buffer output, which provide high noise immunity and stable output. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V.

HCPL-2201500

Vendor:AgilentPackage Cooled:07/08+D/C:1300

The internal circuit is composed of 2 stages including buffer output, which provide high noise immunity and stable output. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V.

HCPL-2201-500E

Vendor:AVAGOPackage Cooled:07+PBD/C:10000

⁄4 ˝ CMOS imager sensor 2:1 Interlace 1/50 to 1/6000 sec 1V p-p composite video (75Ω) EIA: 320(H) x 240(V) CCIR: 352(H) x 288(V) 3.2mm x 2.5mm >46dB (AGC on ) 260 TV line min 5 VDC 0.5V 10mA (no load) f4.9mm F2.8 FOV 56 x 42 f3.8mm F2.0 FOV 36 x 27.5

HCPL2201-500E

Vendor:AVAGOD/C:07无铅

HCPL-2201560

Note 1. 100KEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and traverse airflow greater than 500lfpm is maintained.

HCPL2202

Vendor:agilentPackage Cooled:08+D/C:15000

The MMA3200 series of dual axis (X and Y) silicon capacitive, micromachined accelerometers features signal conditioning, a 4-pole low pass filter and temperature compensation, and separate outputs for the two axes. Zero-g offset full scale span and filter cut-off are factory set and require no external devices. A full system self-test capability verifies system functionality.

HCPL-2202300

Vendor:AgilentPackage Cooled:07/08+D/C:2000

HCPL-2202-300E

Vendor:AVAGOPackage Cooled:07+PBD/C:10000

The bq2063 supports the smart battery data (SBData) commands and charge-control functions. It communicates data using the system management bus (SMBus) 2-wire protocol or the 1-wire HDQ16 protocol. The data available include the batterys remaining capacity, temperature, voltage, current, and remaining run-time predictions. The bq2063 provides LED drivers and a push-button input to depict remaining battery ...

HCPL-2202500

Vendor:AgilentPackage Cooled:07/08+D/C:2500

• Three differential CPU clock pairs • SMBus support with Byte Write/Block Read/Write capabilities • Spread Spectrum EMI reduction • Dial-A-Frequency® features • Auto Ratio features • 48-pin SSOP package

HCPL-2202-500E

Vendor:AVAGOPackage Cooled:07+PBD/C:10000

The ispGAL22V10 has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP). These two prod- uct terms are common to all registered OLMCs. The Asynchronous Reset sets all registers to zero any time this dedicated product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is assert...

HCPL-2202-560E

Vendor:AVAGOPackage Cooled:07+PBD/C:10000

HCPL2210

The small size and battery-powered operation associated with LCD-equipped apparatus dictate low component count and high efficiency for these circuits. Size con- straints place severe limitations on circuit architecture and long battery life is usually a priority. Handheld portable computers offer an excellent example. The CCFL and its power supply can be responsible for almost 50% of the total battery drain.

HCPL-2210

D/C:00+

Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current  Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt ƒ Operating Junction and Storage Temperature Range Soldering Temperature, for 10 second Mounting torqe, 6-32 or M3 screw

HCPL2211

The HY29DL16x Flash memory array is organized into 39 sectors in two banks. Bank 1 contains eight 8 Kbyte boot/parameter sectors and 3 or 7 larger sectors of 64 Kbytes each, depending on the version of the device. Bank 2 contains the rest of the memory array, organized as 28 or 24 sectors of 64 Kbytes:

HCPL-2211-000E

Vendor:AVAGOPackage Cooled:SOP-8D/C:08/04+

Requiring 15V, +5V and C5.2V supplies, the ADS-944 typically dissipates 2.95 Watts. The unit is offered with a bipolar input range of 1.25V. Models are available for use in either commercial (0 to +70C) or military (C55 to +125C) operating temperature ranges. Typical applications include radar signal analysis, medical/graphic imaging, and FFT spectrum analysis.

HCPL2211-000E

Vendor:AVAGOD/C:07无铅

The design is based on an ARM® microprocessor that controls the entire chip. A number of hardware resources, controlled by ARM, perform digital imaging functions such as JPEG coding/decoding, image resizing, and DMA access to SDRAM. All these compu- tational-intensive functions are implemented in hardware which can be programmed according to user specifications, thus allowing ARM to be free for other ...

HCPL-2211-020E

Vendor:AVAGOPackage Cooled:07+PBD/C:10000

HCPL2211300

1. Externally detect a write to the low-power address. You select this address which can be any address in the 16 Mbyte addressing range of the MC68SEC000. A write to the low-power address can be detected by polling A23CA0, R/W, and FC2CFC0. When the low-power address is detected, R/W is a logic low, and the function codes have a five (101) on their output, the processor is writing to the low-power add...

HCPL-2211300

Vendor:AgilentPackage Cooled:07/08+D/C:5000

For early-write cycles, the data is latched on the first falling edge of xCAS. Only the DQs that have the corresponding xCAS low are written into. Each xCAS must meet tCAS minimum in order to ensure writing into the storage cell. In order to latch a new address and new data, both xCAS pins must go high and meet tCP .

HCPL-2211300

Vendor:AgilentPackage Cooled:07/08+D/C:5000

For early-write cycles, the data is latched on the first falling edge of xCAS. Only the DQs that have the corresponding xCAS low are written into. Each xCAS must meet tCAS minimum in order to ensure writing into the storage cell. In order to latch a new address and new data, both xCAS pins must go high and meet tCP .

HCPL2211300E

DEVICE OPERATIONS The following operations can be performed using the appropriate bus cycles: Read Array (Random, and Page Modes), Write command, Output Dis- able, Standby, Reset/Power Down and Block Locking. See Table 8. Read. Read operations are used to output the contents of the Memory Array, the Electronic Sig- nature, the Status Register, the CFI, the Block Protection Status or the Configurati...

HCPL-2211-300E

Vendor:AVAGOPackage Cooled:07+PBD/C:10000

The 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O offers a multi-partition, dual-operation flash architecture that enables the device to read from one partition while programming or erasing in another partition. This Read-While-Write or Read-While-Erase capability makes it possible to achieve higher data throughput rates as compared to single partition devices and it allows two processors to interleav...