I1-507A-2

Vendor:105Package Cooled:HARD/C:N/A

FEATURES High performance and low-cost solution for USB keyboard with hub solution USB Specification Compliance − Conforms to USB specification Rev. 1.1 − Conforms to HID Class specification Rev. 1.0 − Supports 1 device address for hub, 1 device address for keyboard − Supports 2 endpoints of hub, 3 endpoints for keyboard 8-bit micro-processor − RISC-like architecture ͨ...

I1-507A-5

Vendor:105Package Cooled:HARD/C:N/A

10%. The max. current within the varistor voltage change of less than 10% when impulse current (8 20 s) applied . The max. current within the varistor voltage change of less than 10% when impulse current (8 20 s) applied two times with an interval of 5 minutes.

I1-508-2

Package Cooled:DIP

Note 1: Not tested in production. Set by design and characterization. 2: When using the device in the daisy chain configuration, maximum clock frequency is determined by a combination of propagation delay time (tDO 80 ns), data input setup time (tSU 40 ns), SCK high time (tHI 40 ns), and SCK rise and fall times of 5 ns. Maximum fSCK is, therefore, 5.8 MHz.

I1-508A-5

Vendor:205Package Cooled:HARRISD/C:N/A

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications me...

I1-508A-7

Vendor:HARRISPackage Cooled:DIPD/C:89+

The Fairchild family of Star*Power FETs includes a series of devices in various voltage, current and package styles. The portfolio consists of Star*Power and Star*Power Gold products. Star*Power FETs are optimized for total dose and rDS(ON) while exhibiting SEE capability at full rated voltage up to an LET of 37. Star*Power Gold FETs have been optimized for SEE and Gate Charge combining SEE performanc...

I1-508A-7

Vendor:HARRISPackage Cooled:DIPD/C:89+

The Fairchild family of Star*Power FETs includes a series of devices in various voltage, current and package styles. The portfolio consists of Star*Power and Star*Power Gold products. Star*Power FETs are optimized for total dose and rDS(ON) while exhibiting SEE capability at full rated voltage up to an LET of 37. Star*Power Gold FETs have been optimized for SEE and Gate Charge combining SEE performanc...

I1-509-2

Vendor:HARRISPackage Cooled:DIP16陶瓷D/C:87+

I1-509-4

Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maxi- mum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged expo- sure to extreme conditions may affect device reliability.

I1-509-5

Vendor:505Package Cooled:HARRISD/C:N/A

The Hardware Integrity function uses transmission line theory to measure the arrival time and electrical characteristics of the wave reflected back from an incident test wave launched on the media. With these measurements, opens, shorts, and degraded cable quality can be located along the wire, and lead the network manager to the location of the problem.

I1-509-8

I1-509A-5

Vendor:305Package Cooled:HARRISD/C:N/A

beyond those indicated may adversely affect device reliability. Functional operation under absoluteCmaximumCrated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions. 2. Tested to EIA/JESD22CA114CA

I1-516/883

Vendor:HARPackage Cooled:CDIP-28PD/C:9249

60µV Maximum Offset Voltage 300pA Maximum Input Bias Current 135µA Supply Current per Amplifier Rail-to-Rail Output Swing 120dB Minimum Voltage Gain, VS = 15V 0.8µV/C Maximum VOS Drift 14nV/Hz Input Noise Voltage 2.7V to 18V Supply Voltage Operation Operating Temperature Range: C 40C to 85C Space Saving 3mm 3mm DFN Package

I1-516/883

Vendor:HARPackage Cooled:CDIP-28PD/C:9249

60µV Maximum Offset Voltage 300pA Maximum Input Bias Current 135µA Supply Current per Amplifier Rail-to-Rail Output Swing 120dB Minimum Voltage Gain, VS = 15V 0.8µV/C Maximum VOS Drift 14nV/Hz Input Noise Voltage 2.7V to 18V Supply Voltage Operation Operating Temperature Range: C 40C to 85C Space Saving 3mm 3mm DFN Package

I1-516-8

Vendor:HARD/C:DIP

I15184A

This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of circuits described. No patent licences are implied Hyundai Semiconductor Rev.00 / Sep.97

I1-518-5

Vendor:105Package Cooled:HARD/C:N/A

Compatible with: • Bellcore GR-30-CORE, SR-TSV-002476, ANSI/TIA/EIA-716, TIA/EIA-777; • ETSI ETS 300 778-1 (FSK only variant) & -2; • BT (British Telecom) SIN227 & SIN242 Bellcore CPE Alerting Signal (CAS), ETSI Dual Tone Alerting Signal (DT-AS), BT Idle State and Loop State Tone Alert Signal detection 1200 baud Bell 202 and CCITT V.23 FSK demodulation Separate differential i...

I1-518-5

Vendor:105Package Cooled:HARD/C:N/A

Compatible with: • Bellcore GR-30-CORE, SR-TSV-002476, ANSI/TIA/EIA-716, TIA/EIA-777; • ETSI ETS 300 778-1 (FSK only variant) & -2; • BT (British Telecom) SIN227 & SIN242 Bellcore CPE Alerting Signal (CAS), ETSI Dual Tone Alerting Signal (DT-AS), BT Idle State and Loop State Tone Alert Signal detection 1200 baud Bell 202 and CCITT V.23 FSK demodulation Separate differential i...

I151B

Vendor:TEXASPackage Cooled:SOP-16

Loss of Lock indicator output. 4 Logic 1 indicates loss of lock. Logic 0 indicates locked condition. Narrow Bandwidth enable. LVCMOS/LVTTL: Logic 1 - Narrow loop bandwidth, RIN = 2100kΩ. Logic 0 - Wide bandwidth, RIN = 100kΩ. Do Not Connect.

I151B

Vendor:TEXASPackage Cooled:SOP-16

Loss of Lock indicator output. 4 Logic 1 indicates loss of lock. Logic 0 indicates locked condition. Narrow Bandwidth enable. LVCMOS/LVTTL: Logic 1 - Narrow loop bandwidth, RIN = 2100kΩ. Logic 0 - Wide bandwidth, RIN = 100kΩ. Do Not Connect.

I15217

Vendor:QFP-52Package Cooled:LIMBURGD/C:2004+

Entering SIMD mode also has an effect on the way data is trans- ferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the band- width between memory and the processing elements. When using the DAGs to transfer data in SIMD mode,...

I15217

Vendor:QFP-52Package Cooled:LIMBURGD/C:2004+

Entering SIMD mode also has an effect on the way data is trans- ferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the band- width between memory and the processing elements. When using the DAGs to transfer data in SIMD mode,...

I1-524-5

Vendor:105Package Cooled:HARD/C:N/A

I15307

Vendor:DIALOGPackage Cooled:PLCC

Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages.

I15307

Vendor:DIALOGPackage Cooled:PLCC

Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages.

I1-546/883

Vendor:HARPackage Cooled:DIPD/C:2007+

Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor package must be the correct size to ensure proper solder connection inter- face between the board and the package. With the correct pad geometry, the packages will selfCalign when subjected to

I1-546-2

Vendor:HARRISD/C:DIP

I1-549/883

I1-549/883

I1-5618A-5

Vendor:HARRISPackage Cooled:DIP18陶瓷D/C:84+

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described her...

I1-5618A-5

Vendor:HARRISPackage Cooled:DIP18陶瓷D/C:84+

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described her...

I1-562-5

Vendor:N/APackage Cooled:200D/C:N/A

I1-562-5

Vendor:N/APackage Cooled:200D/C:N/A

I1-562A/883

Vendor:HARRISD/C:CDIP

I1-562A-5

Vendor:HARPackage Cooled:DIPD/C:N/A

Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at Vcc = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V, control inputs only); A and B pins do not contribute to Icc. 4. This current applies to the control inputs only and represent the current required to switch internal capacitance at the spe...

I1-562A-5

Vendor:HARPackage Cooled:DIPD/C:N/A

Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at Vcc = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V, control inputs only); A and B pins do not contribute to Icc. 4. This current applies to the control inputs only and represent the current required to switch internal capacitance at the spe...

I1-562A-8

Vendor:HARRISD/C:CDIP

I156-4AB

Vendor:ALCATELPackage Cooled:PQFP-208D/C:1

This method of determining odd / even field information provides for superior noise immunity. Noise during the pre- equalizing pulses does not affect the output since the field decision is made at the beginning of the vertical interval. This noise immunity is displayed in Figure 4 in which an extra pre- equalizing pulse has been added to the video input with no negative effect on the odd/even field information.

I15660-5

Vendor:HARRISPackage Cooled:DIPD/C:86+

I15680V-5

Vendor:HARRISPackage Cooled:DIP12

I1-574AJD-5

Vendor:HARPackage Cooled:DIPD/C:N/A

As long as store input is low, data is continuously transferred from the counter to the display. Data in the counter will be latched and displayed when store input is high. Store can be changed in coincidence with the positive transition of the count input.

I1-574AKD-5

Vendor:HARPackage Cooled:DIPD/C:N/A

These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be asserted on the same cycle as the address. BWs are associated with addresses and apply to subsequent data. BWa# controls DQa, DQPa pins; BWb# controls DQb, DQPb pins; BWc# controls DQc, DQPc pins; BWd# controls DQd, DQPd pins.

I1-6518B-5

I1-6518B-5

I1674AJD-5

Vendor:HARRISPackage Cooled:DIP

I1714421152101

Vendor:vikayPackage Cooled:vikayD/C:dc99

Turn-On Time: In the circuit of Figure 1, turning Q1 on applies a low voltage to the STBY control (pin 2) and disables the regulator ouput. Correspondingly, turning Q1 off removes the low-voltage signal and enables the output. Once enabled, the output will typically experience a 10C15ms delay followed by a predictable ramp-up of voltage. The regulator should provide a fully regulated output voltage wit...

I1-774JD-5

Vendor:HARRISD/C:97

Hynix HYMP512S64MP8 series is designed for high speed and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 4- bit prefetche...

I1A746

Incorporates VDDQ, VTT Regulators Internal Switching Standby Regulator for VDDQ All External Power MOSFETs Are N−Channel Adjustable VDDQ VTT Tracks VDDQ/2 Fixed Switching Frequency of 250 kHz for VDDQ in Normal Mode Doubled Switching Frequency (500 kHz) for Standby Mode Soft−Start Protection for VDDQ Undervoltage Monitor Short−Circuit Protection for Both VDDQ and VTT Outputs Housed ...

I1N4762A

Vendor:OND/C:DO-41

I2001

Vendor:INTERPIONPackage Cooled:SOP-10D/C:0329.

The Advanced Interrupt Controller (AIC) controls the internal interrupt sources from the internal peripherals and the four external interrupt lines (including the FIQ), to provide an interrupt and/or fast interrupt request to the ARM7TDMI. It integrates an 8-level priority controller and, using the Auto-vectoring feature, reduces the interrupt latency time.

I2001 HYNIX SOP-8 0519+

I20103-01

Vendor:IMPD/C:05+

The TSH300 is a voltage feedback amplifier featuring ultra-low input voltage and current noise. This feature, associated with a large bandwidth, large slew rate and a good linearity, makes the TSH300 a good choice for high-speed data acquisition systems where sensitivity and signal integrity are the main priorities.

I20110-01

Vendor:IMPPackage Cooled:TQFP1010-64D/C:98+/99+

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable fail...

I20110-01

Vendor:IMPPackage Cooled:TQFP1010-64D/C:98+/99+

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable fail...

I2-0200-5

I2032VE110LT48

Vendor:LATTICEPackage Cooled:TQFP

other possibility: VREF = VregLogic, VGND = VregLogic/2 For power saving one might connect the Vgnd resistor divider chain from VregLogic onto a port B output. This output should be driving VSS during the conversion and driving high impedance in the ADC off state.

I2032VE-110LT48

Vendor:LATTICEPackage Cooled:QFP48D/C:06+

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed.

I2032VE-110LT48I

Vendor:LATTICEPackage Cooled:QFP48D/C:06+

The SC16C554B/554DB is a 4-channel Universal Asynchronous Receiver and Transmitter (QUART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s. It comes with an Intel® or Motorola® interface.

I2032VE135LT48

Vendor:LATTICEPackage Cooled:QFP-48D/C:05

Drain-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 4.5V Continuous Drain Current, VGS @ 4.5V Pulsed Drain Current Maximum Power Dissipation Maximum Power Dissipation Linear Derating Factor Junction and Storage Temperature Range

I2032VE135LT48

Vendor:LATTICEPackage Cooled:QFP-48D/C:05

Drain-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 4.5V Continuous Drain Current, VGS @ 4.5V Pulsed Drain Current Maximum Power Dissipation Maximum Power Dissipation Linear Derating Factor Junction and Storage Temperature Range

I2032VE-200LT48

Vendor:LATTICEPackage Cooled:QFP0707-48D/C:00+

The MAX 3000A architecture includes four dedicated inputs that can be used as generalCpurpose inputs or as highCspeed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin. Figure 1 shows the architecture of MAX 3000A devices.

I2032VE-225LT48

D/C:01+

When the Transmit FIFO is bypassed (FIFOBYP is LOW), the TXFULL output changes after the rising edge of REFCLK. TXFULL is asserted when the trans- mitter is BUSY (not accepting a new data or command characters) and deas- serted when new characters can be accepted.

I20641E-135L

D/C:N/A

I2064VE-100LB100

Vendor:LATTICEPackage Cooled:BGA1010D/C:00+

tors output sets the trip voltage. Therefore, the trip volt- age is related to the output voltage. These comparators have 4mV internal hysteresis. Additional hysteresis can be generated with two resis- tors, using positive feedback (Figure 1). Use the follow- ing procedure to calculate resistor values: 1) Find the trip points of the comparator using these for- mulas:

I2101IB

Vendor:INTERSILD/C:07+

Note: A shoot-through prevention logic prevents LO1,2,3 and HO1,2,3 for each channel from turning on simultaneously. Note 1: UVCC is not latched, when VCC>UVCC, FAULT returns to high impedance. Note 2: When ITRIP <VITRIP, FAULT returns to high-impedance after RCIN pin becomes greater than 8V (@ VCC = 15V)

I2111

I21152-AB

Vendor:N/APackage Cooled:4900

I2128DB

I2128VE-180L

Vendor:LATTICEPackage Cooled:06+D/C:800

On-chip factory firmware supports in-circuit serial download and debug modes (via UART), as well as single-pin emulation mode via the EA pin. The ADuC846 is supported by a QuickStart™ development system featuring low cost software and hardware development tools.

I2128VE-180L

Vendor:LATTICEPackage Cooled:06+D/C:800

On-chip factory firmware supports in-circuit serial download and debug modes (via UART), as well as single-pin emulation mode via the EA pin. The ADuC846 is supported by a QuickStart™ development system featuring low cost software and hardware development tools.

I21440-AC

Vendor:N/APackage Cooled:4900

I2192VE

Vendor:LATTICEPackage Cooled:N/AD/C:08+

I2192VE-100L

Vendor:LATTICEPackage Cooled:06+D/C:800

I2-200-5

Vendor:HARRISD/C:08+

This chip, when properly assembled, displays characteristics similar to the TL052. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform.

I2-200-5

Vendor:HARRISD/C:08+

This chip, when properly assembled, displays characteristics similar to the TL052. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform.

I2200-5

Vendor:HARPackage Cooled:CAN10D/C:02+

3.1.1 SPI bus While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission should be starting from pulling SSB to "low" level, enabling MTV038 to receiving mode, and retain "low" level until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1.

I2200-5

Vendor:HARPackage Cooled:CAN10D/C:02+

3.1.1 SPI bus While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission should be starting from pulling SSB to "low" level, enabling MTV038 to receiving mode, and retain "low" level until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1.

I22LV10-10LK

Vendor:LATTICEPackage Cooled:99D/C:SSOP

Wide operation from... 1.8 to 15V Low Standby Current.. 1 µA Low Current Consumption 5.5mA high Speed Operation . 1MHz Incorporates soft start circuit Incorporates a stand-by function Incorporate a times-latch short circuit detection circuit (SCP) Totem-pole type output with adjustable on/off current (for NPN transistor) The error amplifier gain is set inside the IC, so peripheral components are m...

I22LV1015LK

Vendor:LatticePackage Cooled:SSOPD/C:2000

Device Description The following information is provided: part number, semiconductor materials used, sequence of zones, technology used, device type and, if necessary con- struction. Also, information on the typical Applications and spe- cial Features is given Absolute Maximum Ratings The absolute maximum ratings indicate the maximum permissible operational and environmental condi- tions. Exceeding...

I22LV10-5LK

Vendor:LATTICEPackage Cooled:SSOP28D/C:99+

[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

I2-301-5

Vendor:HARRISD/C:08+

I2505

Vendor:IRPackage Cooled:08+D/C:1200

I2544

The 28F400B3, 28F800/008B3, 28F160/016B3, 38F320/032B3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

I2674-503

Vendor:HARRISPackage Cooled:PLCC

I277-OCF

I28F640J3A120

Vendor:INTELPackage Cooled:04+D/C:BGA

I28F640J3A120

Vendor:INTELPackage Cooled:04+D/C:BGA

I29245

Vendor:DIALOGPackage Cooled:SMD

Enable pin for the Boot ROM or an external register. Pin has an internal 5 k O pull-up resistor. Bus command and byte enable are multiplexed on the same PCI pins. These bits provide the bus command during the address phase of the transaction. They provide the byte enable during the data phase. Byte enable determines which byte lines carry valid data. Bit 0 coincides with byte 0. Bit 1 coincides with byte 1, ...

I29274ABC

Vendor:DIALOGPackage Cooled:DIP

I2CH2FM

I3001

Vendor:INTERPIONPackage Cooled:SOP-8D/C:0229.

COMPRESSED GCI MODE In GCI compressed mode, one GCI frame consists of 8 GCI time slots, the Data Upstream Interface transmits four 8-bit bytes per GCI time slot. They are: - Two voice data bytes from the A-law or µ-law compressor for two different channel, for easy description, we name the two channels as channel A and channel B. The compressed voice data bytes for channel A and B are 8-bit wide...

I3001

Vendor:INTERPIONPackage Cooled:SOP-8D/C:0229.

COMPRESSED GCI MODE In GCI compressed mode, one GCI frame consists of 8 GCI time slots, the Data Upstream Interface transmits four 8-bit bytes per GCI time slot. They are: - Two voice data bytes from the A-law or µ-law compressor for two different channel, for easy description, we name the two channels as channel A and channel B. The compressed voice data bytes for channel A and B are 8-bit wide...

I3002L

Note 1: Performance from application circuit shown in Figures 3 - 5 guaranteed by design and alternate testing methods, but not 100% tested as shown in production. Note 2: For the UCC3941-3, VOUT = 3.47V and VGD = 9.3V. For the UCC3941-5, VOUT = 5.25V, VGD = 9.3V. For the UCC3941- ADJ, FB = 1.315V, VGD = 9.3V.

I3002L

Note 1: Performance from application circuit shown in Figures 3 - 5 guaranteed by design and alternate testing methods, but not 100% tested as shown in production. Note 2: For the UCC3941-3, VOUT = 3.47V and VGD = 9.3V. For the UCC3941-5, VOUT = 5.25V, VGD = 9.3V. For the UCC3941- ADJ, FB = 1.315V, VGD = 9.3V.

I3010-13.000-9

D/C:07+

This is a dual-purpose pin. During Master Reset, a HIGH on BE will select Big Endian operation. In this case, depending on the bus size, the most significant byte or word on Port A is transferred to Port B first. A LOW on BE will select Little Endian operation. In this case, the least significant byte or word on Port A is transferred to Port B first. After Master Reset, this pin selects the timing mode. A...

I3010-13.000-9

D/C:07+

This is a dual-purpose pin. During Master Reset, a HIGH on BE will select Big Endian operation. In this case, depending on the bus size, the most significant byte or word on Port A is transferred to Port B first. A LOW on BE will select Little Endian operation. In this case, the least significant byte or word on Port A is transferred to Port B first. After Master Reset, this pin selects the timing mode. A...

I30447

Vendor:哈利斯Package Cooled:N/AD/C:9+

I3080

Vendor:INTERSILPackage Cooled:SMDD/C:00/01+

FEATURES High Accuracy, Supports IEC 687/1036 Less than 0.1% Error over a Dynamic Range of 1000 to 1 An On-Chip User Programmable Threshold for Line Voltage SAG Detection and PSU Supervisory The ADE7756 Supplies Sampled Waveform Data (20 Bits) and Active Energy (40 Bits) Digital Power, Phase and Input Offset Calibration An On-Chip Temperature Sensor ( 3 C Typical after Calibration) An SPI-Compatib...

I3101

Vendor:INTERPIONPackage Cooled:SOP-8D/C:0502.

NOTES: 1. For a loaded output the measurements are observed after an RC filter consisting of a 1 kΩ resistor and a 0.01 µF capacitor to ground. 2. These limits define the range of operation for which the part will meet specification. 3. Within the supply range of 4.75 and 5.25 volts, the device operates as a fully calibrated linear accelerometer. Beyond these supply limits the device may ope...

I3-1818A-5

Vendor:HARRISPackage Cooled:100

Signal Processor (DSP) TMS320C6701 C 8.3-, 6.7-, 6-ns Instruction Cycle Time C 120-, 150-, 167-MHz Clock Rate C Eight 32-Bit Instructions/Cycle C 1 GFLOPS C TMS320C6201 Fixed-Point DSP Pin-Compatible VelociTI™ Advanced Very Long Instruction Word (VLIW) C67x CPU Core C Eight Highly Independent Functional Units: C Four ALUs (Floating- and Fixed-Point) C Two ALUs (Fixed-Point) C Two Multiplier...

I3-201-5

Vendor:HARRISPackage Cooled:DIP/16

The parts incorporate a power-on reset circuit to ensure that the DAC output powers up to 0 V (AD5620/AD5640/AD5660-1-2) or midscale (AD5620-3 and AD5660-3) and remains there until a valid write takes place. The parts contain a power-down feature that reduces the current consumption of the device to 480 nA at 5 V and provides software-selectable output loads while in power-down mode. The power consumpt...