IXFR200N10P

Vendor:IXYSPackage Cooled:TO-

The CP3SP33 connectivity processor is an advanced mi- crocomputer with system timing, interrupt logic, instruction cache, data memory, and I/O ports included on-chip, mak- ing it well-suited to a wide range of embedded applications. The block diagram on page 1 shows the major on-chip com- ponents of the CP3SP33.

IXFR24N50 IX

IXFR26N50

Vendor:500Package Cooled:IXYS

SM6610 series is high-accuracy temperature sensor IC in the ultra small package. By using CMOS circuit, it realizes low voltage and low current consumption. The power down function contributes to decrease the current consumption of application set by activating intermittent function easily.

IXFR44N50Q

Vendor:500Package Cooled:IXYS

The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable for big MOS- FET or IGBT drive which, combined with the other features, makes the device an excellent low-cost solu- tion for EN61000-3-2 compliant SMPS's up to 300W.

IXFR44N80P

Vendor:IXYSPackage Cooled:TO-

The TLC.58.. series is a clear, non diffused 5 mm LED for high end applications where supreme luminous intensity and a very small emission angle is required. These lamps with clear untinted plastic case utilize the highly developed ultrabright AlInGaP and GaP technologies. The very small viewing angle of these devices provide a very high luminous intensity.

IXFR55N50

Vendor:IXYS CORPORATIOND/C:05+

The IS80C51/31 is designed with 4K x 8 ROM (IS80C51 only); 128 x 8 RAM; 32 programmable I/O lines; a serial I/O port for either multiprocessor communications, I/O expansion or full duplex UART; two 16-bit timer/counters; a six-source, two-priority-level, nested interrupt structure; and an on-chip oscillator and clock circuit. The IS80C51/31 can be expanded using standard TTL compatible memory.

IXFT10N100

Vendor:IXYSPackage Cooled:TOD/C:07+

The sensor provides a self-test feature allowing the verification of the mechanical and electrical integrity of the accelerometer at any time before or after installation. A fourth plate is used in the g-cell as a self-test plate. When a logic high input to the self-test pin is applied, a calibrated potential is applied across the self-test plate and the moveable plate. The resulting electrostatic force (...

IXFT120N15P

Vendor:TO-268Package Cooled:7850D/C:IXYS

This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html. All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality...

IXFT12N100

Vendor:IXYSPackage Cooled:TOD/C:07+

4.6 USB Endpoint 0 Control and Status Register (0xC090: R/W) 4.7 USB Endpoint 1 Control and Status Register (0xC092: R/W) 4.8 USB Endpoint 2 Control and Status Register (0xC094: R/W) 4.9 USB Endpoint 3 Control and Status Register (0xC096: R/W)

IXFT12N100F

Vendor:IXYSPackage Cooled:TOD/C:07+

27 MHz master clock (internal PLL reference clock) Generated clocks • 27 MHz output • 33.8688 MHz output • 384fs output • 512fs output • 768fs output Sampling frequency fs • 44.1/48 kHz Output disable function Low jitter output: 100 ps (typ, 15pF load) Supply voltage: 3.3 V 24-pin VSOP package

IXFT12N100F

Vendor:IXYSPackage Cooled:TOD/C:07+

27 MHz master clock (internal PLL reference clock) Generated clocks • 27 MHz output • 33.8688 MHz output • 384fs output • 512fs output • 768fs output Sampling frequency fs • 44.1/48 kHz Output disable function Low jitter output: 100 ps (typ, 15pF load) Supply voltage: 3.3 V 24-pin VSOP package

IXFT12N100Q

Vendor:IXYS

under the control of the WR, CS, and DAC channel address pins, A0 to A7. It also has a 3-wire serial interface, which is compatible with SPI®, QSPI™, MICROWIRE™, and DSP interface standards and can handle clock speeds of up to 50 MHz.

IXFT12N100Q

Vendor:IXYS

under the control of the WR, CS, and DAC channel address pins, A0 to A7. It also has a 3-wire serial interface, which is compatible with SPI®, QSPI™, MICROWIRE™, and DSP interface standards and can handle clock speeds of up to 50 MHz.

IXFT13N80Q

Vendor:IXYSPackage Cooled:TOD/C:07+

Run: CPU on, peripherals on Idle: CPU off, peripherals on Sleep: CPU off, peripherals off Idle mode currents down to 5.8 µA typical Sleep mode current down to 0.1 µA typical Timer1 Oscillator: 1.1 µA, 32 kHz, 2V Watchdog Timer: 2.1 µA Two-Speed Oscillator Start-up

IXFT13N90

Vendor:IXYSPackage Cooled:TOD/C:07+

d) Figure 4 shows the load terminated at point A. This point could be connected to a number of places depending on the application. For ex- ample: Connection to ground will test the high side device. Connection to DC BUS will test the low side device. It could also be connected to the center point of a capacitive divider (UPS systems).

IXFT140N10P

Vendor:IXYSPackage Cooled:TOD/C:07+

Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IS61SF25616 and controlled by the ADV (burst address advance) input pin.

IXFT140N10P

Vendor:IXYSPackage Cooled:TOD/C:07+

Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IS61SF25616 and controlled by the ADV (burst address advance) input pin.

IXFT15N100Q

Vendor:IXYSPackage Cooled:TOD/C:07+

It is possible to program this family such that the maximum Junction Temperature rating is exceeded. The package qJA is 115 C/W. Use the CyClocksRT power estimation feature to verify that the programmed configuration meets the Junction Temperature and Package Power Dissipation maximum ratings.

IXFT15N80Q

Vendor:IXYSPackage Cooled:TOD/C:07+

I2C interface select / I2C RESET (active low, asynchronous). If ISEL is high, then the I2C interface is active. Default values for the I2C registers can be found in the I2C register descriptions section. If ISEL is low, then I2C is disabled and the chip configuration is specified by the configuration pins (BSEL, DSEL, EDGE, VREF) and state pin (PD). If ISEL is brought low and then back high, the I2C sta...

IXFT15N80Q

Vendor:IXYSPackage Cooled:TOD/C:07+

I2C interface select / I2C RESET (active low, asynchronous). If ISEL is high, then the I2C interface is active. Default values for the I2C registers can be found in the I2C register descriptions section. If ISEL is low, then I2C is disabled and the chip configuration is specified by the configuration pins (BSEL, DSEL, EDGE, VREF) and state pin (PD). If ISEL is brought low and then back high, the I2C sta...

IXFT16N80P

Vendor:TO-268Package Cooled:7850D/C:IXYS

capacitor used to provide the positive power supply for the sink drive outputs for a power-down condition. This allows predictable braking, if desired. Using a 4.7 µF capacitor will provide 6.5 V gate drive for 300 ms. If the power-down brak- ing option is not needed (i.e., BRKSEL = 0), then this pin should be tied to VREG.

IXFT16N90Q

Vendor:IXYSPackage Cooled:TOD/C:07+

Previous generations of DC-DC converter controllers were designed with fixed output voltages adjustable only by means of a set of external resistors. In a high volume produc- tion environment (such as with personal computers), how- ever, a CPU voltage change would require a CPU board re- design to accommodate the new voltage requirement. The 5-bit DAC in the RC5051 reads the voltage ID code that ...

IXFT16N90Q

Vendor:IXYSPackage Cooled:TOD/C:07+

Previous generations of DC-DC converter controllers were designed with fixed output voltages adjustable only by means of a set of external resistors. In a high volume produc- tion environment (such as with personal computers), how- ever, a CPU voltage change would require a CPU board re- design to accommodate the new voltage requirement. The 5-bit DAC in the RC5051 reads the voltage ID code that ...

IXFT20N80Q

Vendor:IXYSPackage Cooled:TOD/C:07+

NOTES: 1. W is high for read cycle. 2. All timings are referenced from the last valid address to the first transitioning address. 3. Addresses valid prior to or coincident with E going low. 4. At any given voltage and temperature, tEHQZ (max) is less than tELQX (min), and tGHQZ (max) is less than tGLQX (min), both for a given device and from device to device. 5. Transition is measured 500 mV from steadyC...

IXFT21N50Q

Vendor:IXYSPackage Cooled:TOD/C:07+

The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device.

IXFT21N50Q

Vendor:IXYSPackage Cooled:TOD/C:07+

The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device.

IXFT24N50

Vendor:IXYSPackage Cooled:TOD/C:07+

Other operating features include an on/off inhibit, output voltage adjust (trim), margin up/down controls, and the ability to start up into an existing output voltage or prebias. For improved load regulation, an output voltage sense is provided. A non-latching over-current trip and overtemperature shutdown feature protects against load faults.

IXFT26N50

Vendor:IXYSPackage Cooled:TOD/C:07+

The IXFT26N50A contains an additional output, VOUT1, suitable for directly driving the base of an external NPN transistor. Fig- ure 7 shows a configuration which can be used to provide +5 V with boosted current drive. A 1 Ω current sensing resistor limits the current at 0.5 A.

IXFT26N50Q

Vendor:IXYS CORPORATIOND/C:05+

The 16 1 Mux selects one of sixteen inputs E0 through E15 specified by four binary select inputs A B C and D The true data is output on Y and the inverted data on W Propa- gation delays are the same for both inputs and addresses and are specified for 50 pF loading Outputs conform to the standard 8 mA LS totem pole drive standard

IXFT26N60

Vendor:IXYSPackage Cooled:TOD/C:07+

The TPS6113x devices provide a complete power supply solution for products powered by either a one-cell Li-Ion or Li-Polymer or a two up to four-cell Alkaline, NiCd or NiMH batteries. The device can gen- erate two regulated output voltages that are either adjusted by an external resistor divider or fixed internally on the chip. It also provides a simple and efficient buck-boost solution for generating 3.3 V ...

IXFT26N60P

Vendor:IXYSPackage Cooled:TOD/C:07+

An interrupt signal from an external RTC causes the firmware to compare the total energy consumed since the last interrupt to the value stored in data EEPROM and update the value if the consumed power is greater. This provides a record for tracking peak demand for one month. The default value for the interval is 30 minutes.

IXFT26N60P

Vendor:IXYSPackage Cooled:TOD/C:07+

An interrupt signal from an external RTC causes the firmware to compare the total energy consumed since the last interrupt to the value stored in data EEPROM and update the value if the consumed power is greater. This provides a record for tracking peak demand for one month. The default value for the interval is 30 minutes.

IXFT26N60Q

Vendor:IXYSPackage Cooled:TOD/C:07+

Added section 4.15.3 - In-System-Programming (ISP) of FLASH ROM Devices. Added section 4.15.4 - UART Interface. Added section 4.15.5 - DDC2Bi Interface. In sections 4.3.2 - ADC Characteristics and 4.4.1 - DVI Receiver Characteristics clarified that input formats with resolutions higher than that supported by the LCD panel are supported as recovery modes only. • Pins 143 ~ 146: changed xxx_SD...

IXFT28N50F

Vendor:IXYSPackage Cooled:TOD/C:07+

- Commands are entered on each positive CLK edge - Data and data mask are referenced to both edges of DQS - 4-bank operations are controlled by BA0, BA1 (Bank Address) - /CAS latency- 2.0/2.5 (programmable) - Burst length- 2/4/8 (programmable) - Burst type- sequential / interleave (programmable) - Auto precharge / All bank precharge is controlled by A10 - 8192 refresh cycles /64ms (4 banks concurrent refresh)

IXFT30N50

Vendor:IXYSPackage Cooled:TOD/C:07+

The 6B Series delivers sensor-to-host signal-conditioning for remote applications. Software-configurable for a wide variety of sensor types, including: analog input, analog output, and digital I/O, the 6B Series is intended for remote data acquisition, machine monitoring, remote energy management and process monitoring and control applications.

IXFT30N50P

Vendor:TO-268Package Cooled:7850D/C:IXYS

These highly stable timers are capable of producing accurate time delays or oscillation. In the time delay mode of operation, the time is precisely controlled by one external resistor and capacitor. For a stable operation as an oscillator, the freeCrunning frequency and the duty cycle are both accurately controlled with two external resistors and one capacitor. The output structure can source or sink ...

IXFT30N60P

Vendor:TO-268Package Cooled:7850D/C:IXYS

This signal is asserted to indicate either 0 or a maximum of 4 morebytes are present in the tristate receive FIFO. The indication of the receive FIFO level is programmable, as is the polarity of this signal. Signal is updated on the rising edge of RFCLK. The RCA signal is tristated in UTOPIA level-2 mode (MPHYEN asserted) and driven as per the multi-phy protocol. Pin #: 69

IXFT32N50

Vendor:IXYSPackage Cooled:TOD/C:07+

Memory encompasses 16 KB of Flash for program storage, 256 bytes of SRAM for data storage, and up to 2 KB of EEPROM emulated using the Flash. Program Flash utilizes four protec- tion levels on blocks of 64 bytes, allowing customized software IP protection.

IXFT36N60P

Vendor:TO-268Package Cooled:7850D/C:IXYS

Providing two banks of four outputs, the PI6C2308A is a 3.3V zero- delay buffer designed to distribute clock signals in applications including PC, workstation, datacom, telecom, and high-performance systems. Each bank of four outputs can be controlled by the select inputs as shown in the Select Input Decoding Table.

IXFT40N30Q

Vendor:IXYSPackage Cooled:TOD/C:07+

The signal on the current sense input pin is also connected to the input of an over-current comparator. If the amplitude of the current sense signal exceeds 1.25 V, the comparator detects an overload condition and immediately terminates the output pulse. The propagation delay from CSNS to output, in an over-current condition, is typically 170 ns.

IXFT44N50P

Vendor:TO-268Package Cooled:7850D/C:IXYS

Bias Supply (Input): This input pin supplies power to operate the switch and internal circuitry. The input range for VBIAS is 1.6V to 5.5V. When switched voltage (VIN) is between 1.6V to 5.5V and the use of a single supply is desired, connect VBIAS to VIN externally.

IXFT44N50P

Vendor:TO-268Package Cooled:7850D/C:IXYS

Bias Supply (Input): This input pin supplies power to operate the switch and internal circuitry. The input range for VBIAS is 1.6V to 5.5V. When switched voltage (VIN) is between 1.6V to 5.5V and the use of a single supply is desired, connect VBIAS to VIN externally.

IXFT4N100

Vendor:IXYSPackage Cooled:TOD/C:07+

External circuitry consists of an opamp, a common PLD, and a quad fet switch, which can fit into a footprint of roughly 1 square inch (6.5 sq. cm). The device also can control two status LEDs, and includes in addition 8 addressable output drive lines and 4 readable spare input lines which can be used to control LEDs, LCDs, or other panel functions without requiring additional control lines from the host CP...

IXFT4N100Q

Vendor:TO-268Package Cooled:7850D/C:IXYS

Amplifier dissipation reaches a maximum when the peaks of the ac output waveform are approximately 63% of the power supply voltage. For this sine wave amplitude, the instanta- neous output voltage hovers near the crucial half-supply- voltage value for a large portion of the ac cycle.

IXFT50N20

Vendor:IXYSPackage Cooled:TOD/C:07+

The LVDS standard provides a minimum differential output voltage magnitude of 247mV into a 100 Ohm load and receipt of 100mV signals with up to 1V of ground potential difference between a transmitter and receiver. The PI90LVB024 doubles the output drive current to achieve Bus LVDS signaling levels with a 50 Ohm load.

IXFT50N20

Vendor:IXYSPackage Cooled:TOD/C:07+

The LVDS standard provides a minimum differential output voltage magnitude of 247mV into a 100 Ohm load and receipt of 100mV signals with up to 1V of ground potential difference between a transmitter and receiver. The PI90LVB024 doubles the output drive current to achieve Bus LVDS signaling levels with a 50 Ohm load.

IXFT50N20 IXY

IXFT52N30Q

Vendor:IXYSPackage Cooled:TOD/C:07+

Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).

IXFT58N20

Vendor:IXYSPackage Cooled:TOD/C:07+

This is a dual function pin. In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to the FIFO memory. FF/IR is synchronized to the LOW-to-HIGH transition of CLKA.

IXFT60N25Q

Vendor:IXYSPackage Cooled:TOD/C:07+

IXFT66N20Q

Vendor:IXYSPackage Cooled:TOD/C:07+

(2) Master Clock (MCK) Input 1-bit audio signals such as PWM or PDM to the DIN1 and DIN2 pins. By setting the SEL pin to H, master clock (MCK) synchronizes the audio signal inputs (DIN1 and DIN2). In case of SEL = L, input signals go into the amplifier circuits by own timing. Therefore, it requires careful design of PCB patterns from DSP to NJU8714. The setup time and the hold time should be kept in t...

IXFT68N20

Vendor:IXYSPackage Cooled:TOD/C:07+

The traditional procedure for providing hold-up during power loss is to buffer the device with enough bulk capacitance to allow a controlled shutdown to occur or an alternative power source to be brought on line. The problem with this approach is that very large capacitor banks are required because the capacitors are charged at the relatively low voltage at which power fails.

IXFT69N30P

Vendor:TO-268Package Cooled:7850D/C:IXYS

IXFT6N100F

Vendor:1200

To minimize noise, the analog and digital circuits in the ISD1000A Series devices use separate power busses. These voltage busses are brought out to separate pins and should be tied together as close to the supply as possible. In addition, these supplies should be decoupled as close to the package as possible.

IXFT70N15

Vendor:IXYS CORPORATIOND/C:05+

The crystal is the frequency reference of the VCXO and the overall performance of the circuit depends on the characteristics of it. It is important that the crystal meets all required specifications if the VCXO is expected to work reliably. ICS works with crystal vendors to define, build, and certify crystals that meet these requirements, and the crystal vendors maintain an inventory of these devices...

IXFT74N20

Vendor:IXYSPackage Cooled:TOD/C:07+

The Read operation outputs the data in order from the initial accessed address. While SCK is input, the address will be incremented automatically until end (top) of the address space, then the internal address pointer automatically increments to beginning (bottom) of the address space (00000h), and data out stream will continue. The read data stream is continuous through all addresses until terminated by a ...

IXFT75N10Q

Vendor:IXYSPackage Cooled:TOD/C:07+

(5) Nominal capacitance The capacitance is expressed in three digit codes and in units of pico farads (pF). The first and second digits identity the first and second significant figures of the capacitance. The third digit identifies the multiplier. R designates a decimal point.

IXFT7N90Q

Vendor:IXYSPackage Cooled:TOD/C:07+

• Auto precharge/precharge all banks by A10 flag • Possible to assert random column address every clock cycle • Interleaved auto refresh mode • Programmable burst lengths and sequences •- 1,2,4,8,full page for Sequential type •- 1,2,4,8 for Interleave type • Programmable /CAS latency ; 2,3 clocks • Support clock suspend/power down mode by CKE0 • Data...

IXFT80N085

Vendor:IXYSPackage Cooled:TOD/C:07+

These three terminal positive regulators are supplied in a hermetically sealed metal package whose outline is similar to the industry standard TO-220 plastic package. All protective features are designed into the circuit, including thermal shutdown, current limiting and safe-area control. With heat sinking, they can deliver over 3.0 amps of output current. These units feature 2% initial voltage tolerance, ...

IXFT80N15Q

Vendor:IXYSPackage Cooled:TOD/C:07+

STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions TA = 25C, VDD = VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.

IXFT80N15Q

Vendor:IXYSPackage Cooled:TOD/C:07+

STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions TA = 25C, VDD = VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.

IXFT80N20Q

Vendor:600

• 24-Bit SPI for Control and Fault Reporting, 3.3 V/5.0 V Compatible • Outputs Are Current Limited (0.9 A to 2.5 A) to Drive Incandescent Lamps • Output Voltage Clamp of +50 V During Inductive Switching • On/Off Control of Open Load Detect Current (LED Application) • VPWR Standby Current < 10 µA

IXFT9N80Q

Vendor:IXYSPackage Cooled:TOD/C:07+

Control Register A password protected read or write array command at address FFFFh reads or writes the Control Register. Since the control register contains information relating to the password protection, it is necessary to use the Array passwords to access the control register.

IXFTK44N60

Package Cooled:TO-247

IXFV22N50P

TAOperating free-air temperature−4085C ‡ Defined by the signal-integrity requirements and design-goal priorities. NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

IXFV26N50P

Hynix HYMD132G725B(L)4-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

IXFV30N60P

The TLE 4117 is a 3 terminal positive adjustable or fixed voltage regulator. It is capable to supply 800 mA output current. The fixed voltage devices are available for 1.8 V, 2.5 V, 3.3 V and 5 V output voltage. The adjustable device requires 2 external resistors to define an output voltage between 1.25 V and 40 V. The TLE 4117 is packaged in surface mounted D-Pak package.

IXFV36N50PS

The HYM72V16M636TU6 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 128Mbytes memory. The HYM72V16M636TU6 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.

IXFX100N25

Vendor:500Package Cooled:IXYS

TRI-STATE ® is a registered trademark of National Semiconductor Corporation. MICROWIRE/PLUS™, COP8™, MICROWIRE™ and WATCHDOG™ are trademarks of National Semiconductor Corporation. iceMASTER ® is a registered trademark of MetaLink Corporation.

IXFX100N25

Vendor:500Package Cooled:IXYS

TRI-STATE ® is a registered trademark of National Semiconductor Corporation. MICROWIRE/PLUS™, COP8™, MICROWIRE™ and WATCHDOG™ are trademarks of National Semiconductor Corporation. iceMASTER ® is a registered trademark of MetaLink Corporation.

IXFX120N20

Vendor:300

Vdd=2.3V~2.7V, TA = 0C to 70C(C) / -25C to 85C(E), unless otherwise specified -85 #SymbolParameter Min.Max. Read Cycle 1tRCRead Cycle Time85- 2tAAAddress Access Time-85 3tACSChip Select Access Time-85 4tOEOutput Enable to Output Valid-30 5tBA/LB, /UB Access Time-85 6tCLZChip Select to Output in Low Z10- 7tOLZOutput Enable to Output in Low Z5- 8tBLZ/LB, /UB Enable to Output in Low Z10- ...

IXFX120N25

Vendor:500Package Cooled:IXYS

The AT8xC51SND1C provides the necessary features for human interface like timers, keyboard port, serial or parallel interface (USB, TWI, SPI, IDE), ADC input, I2S output, and all external memory interface (NAND or NOR Flash, SmartMedia, MultiMedia, DataFlash cards).

IXFX120N25P

Vendor:IXYSPackage Cooled:TO

The OPA675 and OPA676 are wideband monolithic operational amplifiers with two independent differen- tial inputs. Either input can be selected by an external logic signal. The OPA675 is compatible with ECL logic while the OPA676 is TTL compatible. Both amplifiers are externally compensated and feature very fast input selection speed: ECL = 4ns, TTL = 6ns. This amplifier features fully symmetrical diffe...

IXFX14N100

Vendor:IXYPackage Cooled:TO-3

The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that att...

IXFX15N100

Vendor:500Package Cooled:IXYS

Low power consumption and flexible power management allow selective shutdown of DAC functions, thus extending battery life in portable applications. Couple this design solution with the industrys smallest package, the TI proprietary MicroStar Junior using only 25 mm2 of board area, powerful portable stereo audio designs are easily realizable in a cost effective, space saving total analog solution.

IXFX16N90

Vendor:IXYSPackage Cooled:TO

Caution: The BiCMOS inherent to the design of this component increases the component's susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation, which may be induced by ESD.

IXFX180N06

Vendor:IXYSPackage Cooled:TO

After the initial change on powerCup, subsequent changes in the Dallastat EEPROM memory cells will occur only if the wiper position of the part is moved greater than 12.5% of the total resistance range. Any wiper movement after initial powerCup which is less than 12.5% will not be recorded in the EEPROM memory cells. Since the Dallastat contains a 64CtoC1 multiplexer, a change of greater than 12.5% c...

IXFX180N10

Vendor:500Package Cooled:IXYS

2. Timer Data Reading When the I/O termianl is "L" and the CE tarminal is "H", timer data can read out. The output is LSB first and the output data strings is shown below. The timer data is transferred from timer counter to shift register at rising edge of the chip enable on the CE terminal, and output the LSB of the timer data from the DATA terminal. Afterward the timer data in the...

IXFX180N15P

Vendor:IXYSPackage Cooled:TO

1. IGBT has MOS structure and its gate is insulated by thin silicon oxide. So please handle carefully to protect the device from electrostatic charge. 2. Gate drive voltage during on-period must be applied to satisfy the rating of maximum pulse collector current. And peak reverse gate current during turn-off must become less than 25 mA. (In general, when RG (off) = 68Ω, it is satisfied.) 3. The ...

IXFX200N10P

Vendor:400

The IXFX200N10P is a synchronous, integrated FET 1A step-down regulator with internal compensation. It operates with an input voltage range from 2.5V to 5.5V, which accommodates supplies of 3.3V, 5V, or a Li-Ion battery source. The output can be externally set from 0.8V to VIN with a resistive divider.

IXFX21N100Q

Vendor:500Package Cooled:IXYS

I , Q = 1 Vp-p implies that themagnitude of the signal at each input pin IVIN, IREF, QVIN, QREF is equal to500 mVp-p. USB = upper sideband. LSB =lower sideband. Maximum noise values areassured by statistical characterization only, not production testing. Thevalues specified are over the entire temperature range, TA = C40C to 85C. For a listing of impedances at various frequencies, see Table 1. After opt...

IXFX21N100Q

Vendor:500Package Cooled:IXYS

I , Q = 1 Vp-p implies that themagnitude of the signal at each input pin IVIN, IREF, QVIN, QREF is equal to500 mVp-p. USB = upper sideband. LSB =lower sideband. Maximum noise values areassured by statistical characterization only, not production testing. Thevalues specified are over the entire temperature range, TA = C40C to 85C. For a listing of impedances at various frequencies, see Table 1. After opt...

IXFX24N100F

Vendor:500Package Cooled:IXYS

The bq2050H determines battery capacity by moni- toring the amount of current input to or removed from a rechargeable battery. The bq2050H meas- ures discharge and charge currents, measures bat- tery voltage, estimates self-discharge, monitors the battery for low battery-voltage thresholds, and com- pensates for temperature and discharge rate. Cur- rent measurement is measured by monitoring the voltage acro...

IXFX24N90Q

Vendor:500Package Cooled:IXYS

One of the biggest contributors to waveform degradation is improper grounding. In reference to the test jig, the grounding is best done with one or more large ground planes that are directly connected to the ground pin of the test socket. The Philips Semiconductors AC Test Jigs, both DIP and SO styles, are constructed as a four layer PC board with the 2 internal layers as ground planes. Ground planes ar...

IXFX25N60

Vendor:IXYPackage Cooled:TO-3

Eighteen address bits are required to decode 1 of 262 144 storage cell locations. Nine row-address bits are set up on A0 through A8 and latched onto the chip by RAS. Then, nine column-address bits are set up on A0 through A8 and latched onto the chip by the first xCAS. All addresses must be stable on or before the falling edge of RAS and xCAS. RAS is similar to a chip enable in that it activates the sense...

IXFX25N90

Vendor:500Package Cooled:IXYS

The Set Default command resets all conditions to the power on default states. The HT82K628A will respond with ACK, clears its output buffer, sets the default key types (scan code set 3 operation only) and typematic rate/delay, and clears the last typematic key then contin- ues scanning.

IXFX26N60

Vendor:IXYPackage Cooled:TO-3

All input pins. Input pins XHD and CKI. Input pins SLNP and XVD. Input pins XCLR, RGT, STBY, HP4, TST3 and TST4. Output pins HCK1 and HCK2. All output pins other than those listed in ∗5, ∗7 and ∗8. Output pin CKO. However, set the input level of input pin CKI to 0V or VDD during measurement. Output pin RPD.

IXFX26N90

Vendor:3500

Capacitors and Inductors 0.6 A Continuous Current Per Switch Low-side: RDSon < 1.5 W Versus Total Temperature Range High-side: RDSon < 2.0 W Versus Total Temperature Range Very Low Quiescent Current IS < 20 µA in Standby Mode Outputs Short-circuit Protected Overtemperature Prewarning and Protection Undervoltage and Overvoltage Protection Various Diagnosis Functions Such as Shorte...

IXFX27N80

Vendor:IXYPackage Cooled:TO-3

bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70V3579 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) remains at 3.3V.

IXFX27N80Q

The CD54/74FCT373, 373AT, and 533 octal transparent latches use a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output-HIGH level to two diode drops below VCC. This resultant lowering of output swing (0V to 3.7V) reduces power bus ringing (a source of EMI) and minimizes VCC bounce and ground bounce and their effects during simultaneo...

IXFX44N50F

*Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maxi- mum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

IXFX44N60

Vendor:IXYSPackage Cooled:04+D/C:TO-3P

All Data I/O Ports − 5-V Input Down To 3.3-V Output Level Shift With 3.3-V VCC − 5-V/3.3-V Input Down To 2.5-V Output Level Shift With 2.5-V VCC 5-V Tolerant I/Os With Device Powered-Up or Powered-Down Bidirectional Data Flow, With Near-Zero Propagation Delay Low ON-State Resistance (ron) Characteristics (ron = 5 Ω Typical) Low Input/Output Capacitance Minimizes Loading (Cio(OFF) = ...

IXFX48N50Q

Vendor:IXYSPackage Cooled:08+D/C:2000

TI warrants performance of its products to the specifications applicable at the time of sale in accordance with TIs standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

IXFX48N60P

Vendor:IXYSPackage Cooled:TO

These enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertexs well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inher- ent in MOS devices. Characteristic of all MOS structures, these devices are free from t...

IXFX48N60P

Vendor:IXYSPackage Cooled:TO

These enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertexs well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inher- ent in MOS devices. Characteristic of all MOS structures, these devices are free from t...

IXFX50N50

Vendor:500Package Cooled:IXYS

Minimum Breakdown Voltage: The minimum voltage the device will exhibit at a specified current Working Peak Reverse Voltage: The maximum peak voltage that can be applied over the operating temperature range Average Rectified Output Current: Output Current Averaged over a full cycle with a 50 Hz or 60 Hz sine-wave input and a 180 degree conduction angle Maximum Forward Voltage: The maximum forward voltage the...

IXFX50N60

Vendor:IXYPackage Cooled:TO-3

6. As it might be a cause of degradation of destruction to apply static electricity to this component, do not apply static electricity or excessive voltage while assembling and measuring. And do not transport this component with bare hand.

IXFX55N50

Vendor:500Package Cooled:IXYSD/C:N/A

The integrated high performance USB transceivers allow the ISP1563 to handle all Hi-Speed USB transfer speed modes: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The ISP1563 provides four downstream ports, allowing simultaneous connection of USB devices at different speeds.

IXFX55N50

Vendor:500Package Cooled:IXYSD/C:N/A

The integrated high performance USB transceivers allow the ISP1563 to handle all Hi-Speed USB transfer speed modes: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The ISP1563 provides four downstream ports, allowing simultaneous connection of USB devices at different speeds.

IXFX60N55Q2

Vendor:500Package Cooled:IXYS

By leaving both the RCLK and RSER outputs unconnected or tied to VCC, the entire Receive PLL is turned off. Even though the Receive PLL may be turned off, the Link Fault Indi- cator (LFI) will still reflect the state of the Carrier Detect (CD) input. This feature can be used for aggressive power manage- ment.