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The CY2DL814 is ideal for both level translations from single ended to LVDS and/or for the distribution of LVDS-based clock signals. The Cypress CY2DL814 has configurable input and output functions. The input can be selectable for LVPECL/LVTTL or LVDS signals while the output drivers support standard and high drive LVDS. Drive either a 50-ohm or 100-ohm line with a single part number/device.

J17904

J18779

J18NF3LL

Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 0.96mH, IAS = 62A, VDD = 50V, RG = 25 Ω, Starting TJ = 25C 3. ISD 62A, di/dt 300A/µs, VDD BVDSS, Starting TJ = 25C 4. Pulse Test : Pulse width 300µs, Duty cycle 2% 5. Essentially independent of operating temperature

J195131241

Vendor:HPackage Cooled:01+D/C:83

Application areas include transducer amplifiers, DC gain blocks and all the conventional op-amp circuits which now can be more easily implemented in single power supply systems. For example, these circuits can be directly supplied with off the standard +5V which is used in logic systems and will easily provide the required interface electronics without requiring any additional power supply.

J1952M

Vendor:S+MPackage Cooled:N/AD/C:3J4

Operating temperature range is: C40C to +85C. Guaranteed by design. Sample tested to ensure compliance. 3ICP is internally modified to maintain constant loop gain over the frequency range. 4TA = 25C; AVDD = DVDD = VVCO = 3.3 V; P = 32. 5These characteristics are guaranteed for VCO Core Power = 15 mA. 6Jumping from 1.6 GHz to 1.95 GHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz. 7Using 50 Ω ...

J1958M

Vendor:EPCOSPackage Cooled:SIP-5D/C:06+

Indefinite short circuit protection and overload protection are provided by sensing output load current and restricting the output current to approximately 125% of full load output current. Since the output current is sensed in the secondary stage, the result is a predictable, constant output current control with no foldback char- acteristics. MHF converters are provided with internal filtering

J1981

J1981M

Vendor:EPCOSPackage Cooled:N/AD/C:96

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE is active (low). In the isolation mode (OE high), A data can be stored in one register and /or B data can be stored in the other register.

J1981M

Vendor:EPCOSPackage Cooled:N/AD/C:96

J1M982B-1

Vendor:MSCPackage Cooled:TOT23-5PD/C:6+

J1N3024B

J1N3032B

The FAN2500/01 family of micropower low-dropout voltage regulators utilize CMOS technology to offer a new level of cost-effective performance in GSM and TDMA cellular handsets, Laptop and Notebook portable computers, and other portable devices. Features include extremely low power consumption and low shutdown current, low dropout voltage, exceptional loop stability able to accommodate a

J1N4148-1

Power247™ PowerEdge™ PowerSaver™ PowerTrench® QFET® QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ µSerDes™ SILENT SWITCHER® SMART START™ SPM™

J1N4946

J1N5802

J1N5806

J1N6101

Vendor:SGPackage Cooled:DIP-16D/C:6+

J1N6508

Vendor:SGPackage Cooled:DIP-14D/C:6+

J1N748A

J1N759A-1

J20-0015

Storage Temperature, TS Operating Temperature, TA Lead Solder Temperature, max. (1.6 mm below seating plane) Average Forward Current, IF Reverse Input Voltage, VR Input Power Dissipation, PI Collector Current, IC Collector-Emitter Voltage, VCEO Emitter-Collector Voltage, VECO Collector Power Dissipation Total Power Dissipation Isolation Voltage, Viso (AC for 1 minute, R.H. = 40 ~ 60%)

J20-0043

J200Q5-02

J2026-AD00

Vendor:NECPackage Cooled:光纤D/C:1996+

Maximum Average Forward Rectified Current @TA = 50 (Note 1) Peak Forward Surge Current, 8.3 ms Single Half Sine-wave Superimposed on Rated Load (JEDEC method ) Maximum Instantaneous Forward Voltage @ 6.0A Maximum DC Reverse Current @ TA=25 at Rated DC Blocking Voltage @ TA=100

J2026-CD10

Vendor:NECD/C:1997+

The J2026-CD10 is an N-Channel Power MOS FET with low on- state resistance and ultra high-speed switching characteristics. Because high-speed switching is possible, the IC can be efficiently set thereby saving energy. The small SOP-8 package makes high density mounting possible.

J2039H3C

Vendor:PULSE ENGINEERINGD/C:05+

Delay from CKI Rising Edge to ALE Rising Edge Delay from CKI Rising Edge to ALE Falling Edge Delay from CK2 Rising Edge to ALE Rising Edge Delay from CK2 Falling Edge to ALE Falling Edge ALE Pulse Width Setup of Address Valid before ALE Falling Edge Hold of Address Valid after ALE Falling Edge

J2042H3B

J2045H3A

J2045H3C

Vendor:PULSEPackage Cooled:04+D/C:793

Output 1 (OUT1) can deliver a maximum of 40 mA, from a 1-V input, with output 2 (OUT2) not loaded. OUT2 can deliver a maximum of 20 mA, from a 1-V input, with OUT1 not loaded. Both outputs can be loaded in the same time, but the total output current of the first voltage doubler must not exceed 40 mA. For example, the load at OUT1 is 20 mA and the load at output 2 is 10 mA.

J211/D74Z

J212E3

Vendor:silPackage Cooled:silD/C:dc0524

The Hynix HYM71V16M655HC(L)T8 Series are 16Mx64bits Synchronous DRAM Modules. The modules are composed of eight 16Mx8bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 144pin glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on the PCB.

J22059177

Vendor:GPSPackage Cooled:DIP

PLL-based buffer ICs may be required to follow a spread- spectrum modulated reference clock for frequencies greater than 66MHz. Spread spectrum modulation limits peak EMI emissions by intentionally introducing jitter onto a clock signal, effectively spreading the peak energy over a range of frequencies.

J22059177

Vendor:GPSPackage Cooled:DIP

J220A029

Package Cooled:06+D/C:800

• For upper-leg IGBTS : Drive circuit, High voltage isolated high-speed level shifting, Control circuit under-voltage (UV) protection. Note : Bootstrap supply scheme can be applied. • For lower-leg IGBTS : Drive circuit, Control circuit under-voltage protection (UV), Short-circuit protection (SC). • Fault signaling : Corresponding to a SC fault (Low-side IGBT) or a UV fault (Low-side IGB...

J220A029

Package Cooled:06+D/C:800

J22AB944

Package Cooled:06+D/C:800

As your new, mixed-logic (5V and 3.3V) design evolves and your current require- ments change, your new DC/DC converter will not. DATELs BCP-5/15-3.3/15-D24 (18-36V input) and BCP-5/15-3.3/15-D48 (36-75V input) are fully isolated DC/DC converters providing both 5V and 3.3V outputs. Housed in standard "half-brick" packages (2.3" x 2.4" x 0.525"), the BCPs can support any combination...

J22AD014

Vendor:HPPackage Cooled:N/AD/C:2

The ADP3419 includes an anticross-conduction protection circuit, undervoltage lockout to hold the switches off until the driver has sufficient voltage for proper operation, a crowbar input that turns on the low-side MOSFET independently of the input signal state, and a low-side MOSFET disable pin to provide higher efficiency at light loads. The SD pin shuts off both the high-side and the low-side MOSFE...

J2317

J2371-18

Package Cooled:SI

After a power-on reset, the output is inactive for half an oscillator cycle. During this time, the supply voltage capacitor can be charged so that current limitation is guaranteed in the event of a short-circuit when the IC is switched on for the first time.

J2483-0D00

Vendor:NEC

The C6202/02B/03/04 device has a powerful and diverse set of peripherals. The peripheral set includes multichannel buffered serial ports (McBSPs), general-purpose timers, a 32-bit expansion bus (XB) that offers ease of interface to synchronous or asynchronous industry-standard host bus protocols, and a glueless 32-bit external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchrono...

J25MF30L

Vendor:STPackage Cooled:06+D/C:11000

Notes: 1. Tested on a sample basis. 2. Test conditions assume signal transition times of 10 ns or less, timing reference levels of 1.5V, input levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance for 85-, 100-, 120-, and 150-ns speeds. CL = 30 pF for 70-ns speed.

J25MF30L

Vendor:STPackage Cooled:06+D/C:11000

J25MF3LL

Vendor:STPackage Cooled:06+D/C:12000

Receive analog outputs and the output for receive gain adjustment. VFRO is the receive filter output. AOUT+ and AOUTC are differential analog signal outputs which can directly drive ZL (= 350 W + 120 nF) or a 1.2 kW load. Refer to Fig.1 for gain adjustment. However, these outputs are in high impedance state during power-down.

J25MF3LL

Vendor:STPackage Cooled:06+D/C:12000

J2607A

Vendor:HPD/C:2003

J2679-0A01

Vendor:NECPackage Cooled:光纤D/C:1997+

J26T2110

D/C:07+

Peak and hold mode with minimum peak time: When the channel is turned on the current rises to the programmed peak current level. Then the channel is internally turned off, the current regulator changes to hold current values and a timer is started for a constant off-time. After this time the channel is inter- nally turned on again until the hold current value is reached and then again turned off for the fixe...

J270/D26Z

J270/D27Z

J270-TR1

J270-TRI

Vendor:VISHAYPackage Cooled:TO-92

J2806

Package Cooled:SI

Hynix HYMD216726A(L)6-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

J2888

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable fail...

J2893.0A00

This new IRK serie of MAGN-A-paks modules uses high voltage power thyristor/thyristor and thyristor/diode in seven basic configurations. The semiconductors are elec- trically isolated from the metal base, allowing common heatsinks and compact assemblies to be built. They can be interconnected to form single phase or three phase bridges or as AC-switches when modules are connected in anti-parallel mod...

J291129351

Vendor:HPackage Cooled:01+D/C:1

The normalized gain plots in the Typical Performance Characteristics section show different feedback resistors (Rf) for different gains. These values of Rf are recommended for obtaining the highest bandwidth with minimal peaking. The resistor Rt provides DC bias for the non-inverting input.

J2919

Vendor:SILICONIXPackage Cooled:TO92

J293131371

Vendor:HPackage Cooled:01+D/C:12

Clear Channel Assessment (CCA) is an output used to signal that the channel is clear to transmit. The CCA algorithm is user programmable and makes its decision as a function of RSSI, Energy detect (ED), Carrier Sense (CRS) and the CCA watch dog timer. The CCA algorithm and its programmable features are described in the data sheet. Logic 0 = Channel is clear to transmit. Logic 1 = Channel is NOT clear to...

J2954-TR6

Vendor:雷达D/C:圆轮

J2969

Vendor:VISHAYPackage Cooled:TO-92

FEATURES C3 dB Bandwidth of 2.2 GHz for AV = 12 dB Single Resistor Programmable Gain 0 dB AV 26 dB Differential Interface Low Noise Input Stage 2.7 nV/Hz @ AV = 10 dB Low Harmonic Distortion C79 dBc Second @ 70 MHz C81 dBc Third @ 70 MHz OIP3 of 31 dBm @ 70 MHz Single-Supply Operation: 3 V to 5.5 V Low Power Dissipation: 28 mA @ 5 V Adjustable Output Common-Mode Voltage Fast Settling and Overd...

J2976

Package Cooled:SI

The VCXH16244 contains sixteen non-inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/ receiver. The device is nibble (4-bit) controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation.

J2982

Vendor:N/APackage Cooled:DIPD/C:O2

J2991TR5

Vendor:SILICONIXD/C:05+

4. Handshaking with the OR signal is a third method of avoid- ing the window in question. With this technique the rising edge of SO, or the fact that SO signal is HIGH, will cause the OR signal to go LOW. The SO signal is not taken LOW again, advancing the internal pointer to the next data, until the OR signal goes LOW. This ensures that the SO pulse that is initiated in the window will be automa...

J2CCO

Vendor:ROHMPackage Cooled:TO252-3PD/C:6+

Direction of Rotation: When the codewheel rotates in a counter- clockwise direction (when viewed from the encoder end of the motor) channel A will lead channel B. If the codewheel rotates in the clockwise direction channel B will lead channel A.

J2CCO

Vendor:ROHMPackage Cooled:TO252-3PD/C:6+

J2E2YA

Vendor:PLESSEYPackage Cooled:DIP

Current sensing is accomplished by reading the voltage developed across the lower MOSFETs during their conduction intervals. Current sensing provides the needed signals for precision droop, channel-current balancing, load sharing, and over-current protection. This saves cost by taking advantage of the power devices parasitic on resistance.

J2K096BJ104KKF

Vendor:Taiyo YudenD/C:06+

J2K096BJ104MK-F

Vendor:TAIYOPackage Cooled:SMDD/C:09+

J2K096BJ224MK-F

Vendor:TAIYOPackage Cooled:SMDD/C:09+

J2K110BJ104MB-T

D/C:07+

reducing the video output level is to incorporate a dual tuned circuit in the quadrature network. This can easily be done by capacitatively coupling another parallel tuned circuit to the normal quadrature tuned circuit. Fig. 6 shows an example of this form of dual tuned circuit, both sections having the same Q factor and coupling capacitors chosen to give the best linearity (linear phase response). Fig...

J2K110BJ105MA-T

J2K110BJ224MB-T

Vendor:TAIYOPackage Cooled:224-0405 4P

J2K110BJ225MA-T

Vendor:TAIYOPackage Cooled:SMDD/C:09+

J2K212BJ225KD-T

D/C:4599

The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device status bits: RY/ BY pin, I/O7 ...

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