Index "K"D/C:07+
Software compilers support the three different global OLMC modes as different device types. Most compilers also have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the registered mode. All combina- torial outputs with OE controlled by the product term will force the softwa...
D/C:24000
The CD54AC574/3A and CD54ACT574/3A are octal D-type, three-state, positive-edge triggered flip-flops that utilize the Harris Advanced CMOS Logic technology. The eight flip- flops enter data into their registers on the LOW-to-HIGH transition of the clock (CP). The Output Enable (OE) controls the three-state outputs and is independent of the register operation. When the Output Ena...
Vendor:N/APackage Cooled:PLCCD/C:1990
The MTC20136 is a dedicated controller chip, spe- cifically designed to control operations of the ST- MicroelectronicsDynaMiTechipset.The MTC20136 offers direct glueless interfaces to the MTC20135 and MTC20455 DMT/ATM transciever and implements a complete control interface for parameters and commands exchange between transceiver and system management. All real time ADSL-related functions (including ...
Vendor:QFPPackage Cooled:80D/C:KAWASAKI
The AMI signal first enters a fixed equalizer, which is designed to overcome the intersymbol interference caused by long cable lengths and crosstalk. This fixed equalizer is optimized for DS3 application and its effect should be compensated by an external filter circuit similar to Figure 1, for all square shaped signals such as DS3-high or 34 Mbit/s E3. For all new designs, the addition of the filter for DS3...
Package Cooled:SOP16SD/C:2007+
Vendor:KLATENCORPackage Cooled:PLCC68
The KM4132G271B is 8,388,608 bits synchronous high data rate Dynamic RAM organized as 2 x 131,072 words by 32 bits, fabricated with SAMSUNG's high performance CMOS technol- ogy. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length, and programmable latencies allows the same ...
Vendor:KLATENCORPackage Cooled:PLCC68
The KM4132G271B is 8,388,608 bits synchronous high data rate Dynamic RAM organized as 2 x 131,072 words by 32 bits, fabricated with SAMSUNG's high performance CMOS technol- ogy. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length, and programmable latencies allows the same ...
Vendor:ROHMPackage Cooled:N/AD/C:2448
Vendor:kyconPackage Cooled:kyconD/C:dc01
Optimized for 2.5V LVTTL Guaranteed Low Skew < 25ps (max) Very low duty cycle distortion < 300ps (max) High speed propagation delay < 2ns. (max) Up to 200MHz operation Very low CMOS power levels Hot insertable and over-voltage tolerant inputs 1:10 fanout buffer 2.5V VDD Available in TSSOP package
Vendor:KOAPackage Cooled:3225-2R2J
5Ω A/B bi-directional switchΩ Isolation Under Power-Off Conditions Over-voltage tolerant Latch-up performance exceeds 100mA VCC = 2.3V - 3.6V, normal range ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0) • Available in SSOP, TSSOP, and TVSOP packages
Package Cooled:PLCCD/C:10
Vendor:COSMOPackage Cooled:DIP-6D/C:2008+
FEATURES Complete Microphone Conditioner in an 8-Lead Package Single +5 V Operation Preset Noise Gate Threshold Compression Ratio Set by External Resistor Automatic Limiting Feature Prevents ADC Overload Adjustable Release Time Low Noise and Distortion 20 kHz Bandwidth ( 1 dB) Low Cost
Vendor:COSMOPackage Cooled:DIP-6D/C:2008+
FEATURES Complete Microphone Conditioner in an 8-Lead Package Single +5 V Operation Preset Noise Gate Threshold Compression Ratio Set by External Resistor Automatic Limiting Feature Prevents ADC Overload Adjustable Release Time Low Noise and Distortion 20 kHz Bandwidth ( 1 dB) Low Cost
Vendor:COSMOPackage Cooled:DIP-6D/C:2008+
Series 32000 and TRI-STATE are registered trademarks of National Semiconductor Corporation MICROWIRE PLUSTM and WATCHDOGTM are trademarks of National Semiconductor Corporation UNIX is a registered trademark of AT T Bell Laboratories IBM and PC-AT are registered trademarks of International Business Machines Corp SunOSTM is a trademark of Sun Microsystems
Vendor:COSMOPackage Cooled:DIP-6D/C:2008+
The MT8985 master clock (C4i) is a 4.096 MHz allowing serial data link configuration at 2.048 Mb/s to be implemented. The MT8985 frame synchronization pulse can be formatted according to ST-BUS or GCI interface specifications; i.e., the frame pulse can be active in HIGH (GCI) or LOW (ST-BUS). The MT8985 device automatically detects the presence of an input frame pulse and identifies the type of backplane pre...
Vendor:COSMO.Package Cooled:光耦-6
For more details on the ARCNET protocol engine and traditional dipulse signaling schemes, please refer to the ARCNET Local Area Network Standard, available from Standard Microsystems Corporation or the ARCNET Designer's Handbook, available from Datapoint Corporation.
D/C:98
This pin controls the operation mode of the interface. If EN = 1, the interface is in normal mode, with the transmission path from TXD to LIN and from LIN to Rx both active. If EN = 0, the device is switched to sleep mode and no transmission is possible. In sleep mode, the LIN bus pin is connected to VS with a weak pull-up current source. The device can transmit only after being woken up (see Inhibit Outp...
Vendor:7Package Cooled:KODAKD/C:N/A
The transmit path interpolation filter provides an upsampling factor of 16 with an output signal bandwidth up to 4.35 MHz. Carrier frequencies up to 65 MHz with 26 bits of frequency tuning resolution can be generated by the direct digital synthesizer (DDS). The transmit DAC resolution is 12 bits and can run at sampling rates as high as 232 MSPS. Analog output scaling from 0 dB to 7.5 dB in 0.5 dB steps...
Vendor:8Package Cooled:KODAKD/C:N/A
For alternating current, such as that from the mains, average power also must account for power factor, which is the phase relationship between voltage and current. In simple terms, average AC power is V I cos, where V and I are average rms voltage and current, and is the phase angle between the two. Instanta- neous sampling does not directly use power factor; the value of the phase angle is essenti...
Vendor:220Package Cooled:KODAKD/C:N/A
Vendor:KPackage Cooled:CDIP镜D/C:01+
The MIC5306 is a micropower, µCap low dropout regulator designed for optimal performance in a small space. It is capable of sourcing 150mA of output current and only draws 16µA of operating current. This high performance LDO offers fast transient response and good PSRR while consuming a minimum of current.
Vendor:KPackage Cooled:CDIP镜D/C:01+
The MIC5306 is a micropower, µCap low dropout regulator designed for optimal performance in a small space. It is capable of sourcing 150mA of output current and only draws 16µA of operating current. This high performance LDO offers fast transient response and good PSRR while consuming a minimum of current.
Vendor:23Package Cooled:KODAKD/C:N/A
The 3-megapixel CMOS image sensor features Digital- ClarityMicrons breakthrough low-noise CMOS imaging technology that achieves CCD image quality (based on signal-to-noise ratio and low-light sensitiv- ity) while maintaining the inherent size, cost, and inte- gration advantages of CMOS.
Vendor:LittelfuseD/C:08+
1.1 Scope. This specification covers the performance requirements for an N-channel, enhancement-mode, MOSFET, radiation hardened (total dose only), power transistor. Two levels of product assurance are provided for each device type as specified in MIL-PRF-19500, with avalanche energy maximum rating (EAS) and maximum avalanche current (IAS).
Vendor:LittelfuseD/C:08+
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Vendor:littel fusePackage Cooled:littel fuseD/C:dc06
Package Cooled:DIP
Each FAST data sheet spells out the test circuit used to check AC performance, the waveforms, measurement points, rep rate, test loads, etc., but these are only the quantifiable variables involved in this testing. There is another more complex side to the issue test jigs and equipment setups.
Vendor:KESENESPackage Cooled:LL34D/C:07+(P/B-Free)
Caution: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied.
Vendor:850
Notes 1. Device is considered as a two terminal device: Pins 1,2 3 and 4 are shorted together and Pins 5,6,7 and 8 are shorted together. 2. Common mode transient immunity at output high is the maximum tolerable (positive) dVcm/dt on the leading edge of the com- mon mode impulse signal, Vcm, to assure that the output will remain high. Common mode transient immunity at output low is the maximum tolerable ...
Vendor:N/APackage Cooled:N/AD/C:N/A
Specifications in standard type face are for TJ = 25˚C and those with boldface type apply over the full Operating Tempera- ture Range (TJ = −40˚C to +125˚C) Unless otherwise specified. VIN = 12V and IL = 0A, unless otherwise specified.
Vendor:NSPackage Cooled:DIPD/C:0728vgc+
Vendor:NSPackage Cooled:DIP8D/C:00+
Vendor:KECD/C:06+
The FM809/810 are supervisor circuits that monitor power supply or other system voltages and issue reset pulse whenever the voltage being monitored is out of tolerance. Once asserted, the reset pulse is guaranteed to be valid for a minimum of 140ms (256ms typical). FM809xx offers active low push-pull type of reset while FM810xx offers active high push-pull type. Several threshold voltages are offered t...
Vendor:KLNPackage Cooled:DIPD/C:08+
The UV erasable version can be erased and repro- grammed to any of the configuration modes. Microchip's PICSTART® Plus and PRO MATE® pro- grammers both support the PIC12CE67X. Third party programmers also are available; refer to the Microchip Third Party Guide for a list of sources.
Vendor:JRCPackage Cooled:PQFPD/C:95+
BYTE LOAD: A byte load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Byte loads are used to enter the 64 bytes of a page to be programmed or the software codes for data protection and chip erasure.
Vendor:kyconPackage Cooled:kyconD/C:dc03
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Vendor:KLEERPackage Cooled:QFND/C:07+
Vendor:ROHMPackage Cooled:module
The SK-2900 Series of quartz crystal oscillators provide DPECL Fast Edge compatible signals. This device is to operate using positive voltage and uses multiple ground pins for improved signal integrity. This device is intended to operate on positive voltage for PECL applications.
Vendor:ROHMPackage Cooled:module
The SK-2900 Series of quartz crystal oscillators provide DPECL Fast Edge compatible signals. This device is to operate using positive voltage and uses multiple ground pins for improved signal integrity. This device is intended to operate on positive voltage for PECL applications.
Vendor:902
Vendor:#N/APackage Cooled:N/AD/C:124
• Selects between 1 of 2 inputs, and provides 12 precision, low skew LVDS output copies • Guaranteed AC performance over temperature and voltage: C DC to >1GHz throughput C <975ps propagation delay CLK0-to-Q C <250ps rise/fall time C <25ps output-to-output skew • Ultra-low jitter design: C <1psRMS random jitter C <10psPP total jitter (clock) C <1psRMS...
Vendor:#N/APackage Cooled:N/AD/C:124
• Selects between 1 of 2 inputs, and provides 12 precision, low skew LVDS output copies • Guaranteed AC performance over temperature and voltage: C DC to >1GHz throughput C <975ps propagation delay CLK0-to-Q C <250ps rise/fall time C <25ps output-to-output skew • Ultra-low jitter design: C <1psRMS random jitter C <10psPP total jitter (clock) C <1psRMS...
Vendor:MOTPackage Cooled:SOP8D/C:06+
The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW).
Vendor:MOTD/C:05+
Sending the WREN op-code causes the internal Write Enable Latch to be set. A flag bit in the status register, called WEL, indicates the state of the latch. WEL=1 indicates that writes are permitted. Attempting to write the WEL bit in the status register has no affect. Completing any write operation (rising edge of /CS) will automatically clear the Write Enable Latch and prevent further writes without...
Vendor:MOTD/C:05+
Sending the WREN op-code causes the internal Write Enable Latch to be set. A flag bit in the status register, called WEL, indicates the state of the latch. WEL=1 indicates that writes are permitted. Attempting to write the WEL bit in the status register has no affect. Completing any write operation (rising edge of /CS) will automatically clear the Write Enable Latch and prevent further writes without...
Stresses above those listed under "Absolute Maximum Ratings" may causes permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Stresses above those listed under "Absolute Maximum Ratings" may causes permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D/C:07+
• Plastic package has Underwriters Laboratories Flammability Classification 94V-0 • Ideal for surface mount automotive applications • High temperature metallurgically bonded construction • Cavity-free glass passivated junction • Capable of meeting environmental standards of MIL-S-19500 • Built-in strain relief • Easy pick and place • Fast switching for ...
Vendor:KUNMING
Vendor:N/APackage Cooled:SOP24D/C:03+
Notes: 1. The dominant wavelength, ëd, is derived from the CIE chromaticity diagram and represents the single wavelength which defines the color of the device. 2. The radiant intensity, Ie, in watts per steradian, may be found from the equation Ie = IV/V, where IV is the luminous intensity in candelas and çV is luminous efficacy in lumens/watt. 3. T-13/4. 4. T-1.
Vendor:N/APackage Cooled:SSOPD/C:0011+
Vendor:MXPackage Cooled:BGA48D/C:07+
Vendor:ITTPackage Cooled:06+D/C:30
Vendor:XIRCOMPackage Cooled:0037+D/C:TQFP
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.The information presented in this document does not form part of any quo- tation or contract, is believed to be accurate and reliable and may be changed without notice. No lia- bility will be accepted by the publisher for any consequence of its use. Publication thereof does not convey...
Vendor:SECPackage Cooled:SOJD/C:98+
All typical values are at 25C and with 3.3 V supply unless otherwise noted. tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device. tsk(o) is the magnitude of the time difference between the tPLH and tPHL of any two outputs of a single device. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devi...
Vendor:GERMANYPackage Cooled:06+D/C:QFP
The micro-controller system of commands complies with the system of commands of the MCS-51 family. The microchip is initialized (reset) automatically when turning power on, when the guard timer is overflowed or effected by the RST signal (voltage active low level) if the external synchronization signal is applied or during the quartz connection.
D/C:01
See Designing An EZ-ICE-Compatible Target System in the ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as well as the Designing an EZ-ICE-Compatible System section of this data sheet for the exact specifications of the EZ-ICE target board connector.
Vendor:FLEXPackage Cooled:0610+D/C:QFP
Vendor:STPackage Cooled:PLCC44D/C:07/08+
Vendor:sgsPackage Cooled:sgsD/C:dc94
The RF5189 is a linear, medium-power, high-efficiency amplifier IC designed specifically for battery-powered WLAN applications such as PC cards, mini PCI, and compact flash applications. The device is manufactured on an advanced Gallium Arsenide Heterojunction Bipolar Transistor (HBT) process, and has been designed for use as the final RF amplifier in 2.5GHz WLAN and other spread-spectrum transmitter...
Vendor:STPackage Cooled:PLCC
Voltage Control Oscillator (bit LCD= 0). This pin is used to control the internal oscillator frequency by DC voltage input from external low pass filter. Pixel Clock Input (bit LCD= 1). This is a clock input pin. MTV038 can be driven by an external pixel clock source for all the logics inside. The frequency of XIN must be the integral time of pin HFLB.
Vendor:STPackage Cooled:SOP-20D/C:N/A
All four clock outputs of the FS6011 may be tristated to facilitate circuit board testing. To place the outputs in tristate mode, follow this sequence: 1. force XIN low (i.e. ground) 2. apply power to the device 3. wait until the internal power-on reset has deasserted 4. apply a negative-going transition to the PSEL0 pin Outputs may be re-enabled by removing and reapplying power to the FS6011. To r...
o Integrated 16-Bit DAC and 32-Channel SHA with SRAM and Sequencer o 32 Voltage Outputs o 0.005% Output Linearity o 200µV Output Resolution o Flexible Output Voltage Range o Remote Ground Sensing o Fast Sequential Loading: 1.3µs per Register o Burst and Immediate Mode Addressing o No External Components Required for Setting Gain and Offset o Integrated Output Clamp Diodes o Three Out...
Vendor:SAMSUNGPackage Cooled:N/AD/C:98+
0 V dc Bias +0.5 V dc Bias DC to 100 MHz; VDD = 2.5 V 10% 500 MHz; VDD = 2.5 V 10% 1000 MHz; VDD = 2.5 V 10% 100 MHz60 500 MHz43 1000 MHz34 100 MHz51 500 MHz37.5 1000 MHz31 DC to 100 MHz20 500 MHz23 1000 MHz25 DC to 100 MHz18 500 MHz17 1000 MHz15 50% CTRL to 90% RF 50% CTRL to 10% RF 10% to 90% RF 90% to 10% RF 1000 MHz 900 MHz/901 MHz, 4 dBm30
Vendor:SOP32Package Cooled:100D/C:SAM
A special mode is introduced to reduce EMI. With pin OSEL connected to GND the internal oscillator is switched off and an external sinusoidal frequency could be applied on OSCIN. The peak to peak voltage of this signal can be reduced down to 60mV.
Package Cooled:KOREAD/C:DIP
Vendor:SAMSUNGPackage Cooled:PLCCD/C:00+
The GND terminals of the ISL6537A provide the return path for the VTT LDO, and switching MOSFET gate drivers. High ground currents are conducted directly through the exposed paddle of the QFN package which must be electrically connected to the ground plane through a path as low in inductance as possible.
Vendor:SAMSUNGPackage Cooled:PLCCD/C:00+
The GND terminals of the ISL6537A provide the return path for the VTT LDO, and switching MOSFET gate drivers. High ground currents are conducted directly through the exposed paddle of the QFN package which must be electrically connected to the ground plane through a path as low in inductance as possible.