L04-150B020-D04(150UH)

Vendor:/Package Cooled:/D/C:/

L04-150B020-D04(150UH)

Vendor:/Package Cooled:/D/C:/

L04-15A7130-F08

L041S153(D153)

Vendor:BIPackage Cooled:ZIP-4D/C:01+

In-Circuit Serial Programming (ICSP™) Internal 4 MHz oscillator with programmable calibration Selectable clockout Power-on Reset (POR) Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation Programmable code protection Power saving SLEEP mode Interrupt-on-pin change (GP0, GP1, GP3) Internal pull-ups on I/O ...

L04-33A7120-C70(33UH)

Vendor:/Package Cooled:/D/C:/

L043A

Vendor:PHILIPSPackage Cooled:LCC D/C:2005

When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC registers. This puts the external registers into a static state allowing data to be read without register values changing during the read process. Normal updates to the internal registers continue while in this state. External updates are halted when a 1 is written into the read bit, B6 of the Control ...

L044A260

Vendor:INTELPackage Cooled:BGAD/C:96

Configuration EPROMs for FLEX Devices Data Sheet BitBlaster Serial Download Cable Data Sheet ByteBlaster Parallel Port Download Cable Data Sheet Application Note 33 (Configuring FLEX 8000 Devices) Application Note 38 (Configuring Multiple FLEX 8000 Devices)

L044A260

Vendor:INTELPackage Cooled:BGAD/C:96

Configuration EPROMs for FLEX Devices Data Sheet BitBlaster Serial Download Cable Data Sheet ByteBlaster Parallel Port Download Cable Data Sheet Application Note 33 (Configuring FLEX 8000 Devices) Application Note 38 (Configuring Multiple FLEX 8000 Devices)

L049AA03

Vendor:LATTICE

L04ME

Package Cooled:SMD-8D/C:03 04

L05-0100020-G11

L05-0500080-L28

L050B

Vendor:NSCPackage Cooled:QFN-10

The AV9155 is a low cost frequency generator designed spe- cifically for desktop and notebook PC applications. Its CPU clocks provide all necessary CPU frequencies for 286, 386 and 486 systems, including support for the latest speeds of proces- sors. The device uses a 14.318 MHz crystal to generate the CPU and all peripheral clocks for integrated desktop motherboards.

L051S103

Vendor:BIPackage Cooled:ZIP-4D/C:00+

Handsets and Telecommunications Applications Two Differential Microphone Inputs Differential Earphone Outputs and One Single-Ended Earphone Output Earphone and Microphone Mute Programmable Transmit, Receive, and Sidetone Paths With Extended Gain and Attenuation Ranges Programmable for 15-Bit Linear Data or 8-Bit Companded (µ-law and A-law) Mode Supports PCM Clock Rates of 128 kHz and 2.048 MHz Pu...

L0603100JFWTR

Vendor:700000Package Cooled:AVXD/C:2008

L0603100JFWTR

Vendor:700000Package Cooled:AVXD/C:2008

L0603100JGWTR

Vendor:700000Package Cooled:AVXD/C:2008

The ratiometric linear Hall effect sensor each contain a monolithic integrated circuit on a single chip. The circuit incorporates a quadratic Hall sensing element which minimizes the effects of mechanical and thermal stress on the Hall element and temperature compensating circuitry to compensate for the inherent Hall element sensitivity change over temperature current. These ratiometric linear Hall effect ...

L0603120JFWTR

Vendor:700000Package Cooled:AVXD/C:2008

L0603150JFWTR

Vendor:AVXPackage Cooled:O603D/C:/

L06031R2DFWTR

Vendor:AVXPackage Cooled:O603D/C:/

q ACTIVE 18-Line TERMINATOR q 2pF CAPACITANCE PER LINE IMPORTANT FOR SCSI FAST-20 q ON-CHIP TERMINATION RESISTORS q ALL TERMINATIONS DISCONNECT WITH SINGLE LOGIC SIGNAL q 325mA CURRENT SINKING FOR ACTIVE NEGATION q 22.4mA PER LINE DURING ASSERTION

L06031R5CFWTR

Vendor:700000Package Cooled:AVXD/C:2008

In order to conserve power, the OTG Supplement allows an A-device to leave VBUS turned off when the bus is not being used. Then, when the B-device wants to use the bus, it follows the SRP pulsing protocol to request that the A-device supply power to VBUS. In the configuration in Figure 1, the OTG Host would be considered the A-device, and the USB20H04 Hub would be considered the B-device.

L06031R5DFWTR

Vendor:AVXPackage Cooled:O603D/C:/

Protect Register Clear (PRCLEAR) The PRCLEAR instruction clears the address stored in the Protect Register and therefore enables all registers for the WRITE and WRALL instruction The PRE and PE pins must be held high while loading the instruction sequence howev- er after loading the PRCLEAR instruction the PRE and PE pins become dont care Note that a PREN instruction must immediately precede a PRCLEAR ...

L06031R8DFWTR

Vendor:AVXPackage Cooled:O603D/C:/

L06032R2DFWTR

Vendor:AVXPackage Cooled:O603D/C:/

Dimensions are in inches. Metric equivalents are given for general information only. The location of the tab locator within the limits indicated will be determined by the tab and flange dimensions of the device being checked. Gauging procedure. The device being measured shall be inserted until its seating plane is .125 .010 inch (3.18 0.25 mm) from the seating surface of the gauge. A force of 8 .5 ounces ...

L06032R2DFWTR

Vendor:AVXPackage Cooled:O603D/C:/

Dimensions are in inches. Metric equivalents are given for general information only. The location of the tab locator within the limits indicated will be determined by the tab and flange dimensions of the device being checked. Gauging procedure. The device being measured shall be inserted until its seating plane is .125 .010 inch (3.18 0.25 mm) from the seating surface of the gauge. A force of 8 .5 ounces ...

L06033R3DFWTR

Vendor:700000Package Cooled:AVXD/C:2008

5V Reference Generation 5V Standby Reference Generation IDE Reset/Buffered PCI Reset Outputs Power OK Signal Generation Power Sequencing Power Supply Turn On Circuitry Resume Reset Signal Generation Hard Drive Front Panel LED Voltage Translation for DDC to VGA Monitor SMBus Isolation Circuitry CNR Dynamic Down Control

L06033R3DFWTR

Vendor:700000Package Cooled:AVXD/C:2008

5V Reference Generation 5V Standby Reference Generation IDE Reset/Buffered PCI Reset Outputs Power OK Signal Generation Power Sequencing Power Supply Turn On Circuitry Resume Reset Signal Generation Hard Drive Front Panel LED Voltage Translation for DDC to VGA Monitor SMBus Isolation Circuitry CNR Dynamic Down Control

L06033R9DFWTR

Vendor:AVXPackage Cooled:O603D/C:/

Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum is used in this data sheet. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. c. MODE = 3 V and/or DISABLE = 3 V and/or TERMPWR = 0 V. d. Guaranteed by design, not subject to production test. e. VCM applied simultaneously to Line PLUS and Line MINUS pin...

L06033R9DFWTR

Vendor:AVXPackage Cooled:O603D/C:/

Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum is used in this data sheet. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. c. MODE = 3 V and/or DISABLE = 3 V and/or TERMPWR = 0 V. d. Guaranteed by design, not subject to production test. e. VCM applied simultaneously to Line PLUS and Line MINUS pin...

L06034R7DGSTR

Vendor:AVXD/C:06+

L06035R6DFWTR

Vendor:AVXPackage Cooled:O603D/C:/

• Semiconductor laser and photodetector are integrated through using micro-mirror. • Focus error signal detection: SSD method • Tracking error signal detection: 3-beam method • Low-power semiconductor laser included • Built-in I-V conversion amplifier

L06035R6DFWTR

Vendor:AVXPackage Cooled:O603D/C:/

• Semiconductor laser and photodetector are integrated through using micro-mirror. • Focus error signal detection: SSD method • Tracking error signal detection: 3-beam method • Low-power semiconductor laser included • Built-in I-V conversion amplifier

L06038R2DFWTR

Vendor:AVXPackage Cooled:O603D/C:/

ICC reduced to 40 0 mA Ideal buffer for MOS microprocessor or memory Eight edge-triggered D flip-flops Buffered common clock Buffered asynchronous master reset TTL input and output level compatible TTL levels accept CMOS levels IOL e 48 mA (Com) 32 mA (Mil) NSC 54 74FCT273 is pin and functionally equivalent to IDT 54 74FCT273 Military product compliant to MIL-STD-883 and Standard Military Drawing 5962...

L06038R2DFWTR

Vendor:AVXPackage Cooled:O603D/C:/

ICC reduced to 40 0 mA Ideal buffer for MOS microprocessor or memory Eight edge-triggered D flip-flops Buffered common clock Buffered asynchronous master reset TTL input and output level compatible TTL levels accept CMOS levels IOL e 48 mA (Com) 32 mA (Mil) NSC 54 74FCT273 is pin and functionally equivalent to IDT 54 74FCT273 Military product compliant to MIL-STD-883 and Standard Military Drawing 5962...

L0612KRX7R9BN153

Vendor:YAGEOPackage Cooled:153-0612

L061470

L061C102LF

L061C103

Vendor:BI TECHNOLOGIESD/C:05+

erase operation, successive attempts to read data from the same memory plane will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.

L061C104LF

L061C222LF

L061C331LF

L061C473LF

L061S102

The serializer enters the high-impedance mode when the DEN pin is driven low. This puts both driver output pins (DO+ and DOC) into a high-impedance state. When you drive DEN high, the serializer returns to the previous state, as long as all other control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F). When the REN pin is driven low, the deserializer enters high-impedance mode. Consequently, the receiv...

L061S821LF

L061S822LF

L063C272LF

L063C472LF

L063C823LF

L063S222LF

L063S391LF

L065DU12RI

Vendor:AMDPackage Cooled:BGAD/C:00+

5. Enables servicing by assigning high, middle or low priority to the channel priority bits. All PWM channels must be assigned the same priority to ensure correct operation. The CPU must ensure that the svmStd3_sync or svmStd3_res channels are initialized after the initialization of PWM channels:

L065DU90KI

Vendor:AMDPackage Cooled:06+D/C:800

L0805100GEWTR

Package Cooled:N/AD/C:08+

L0805100JEW

L0805150JEWTR

Vendor:AVXD/C:05+

Dual Synchronous Controller in 24-Pin Package with 1808 out-of-phase operation LDO Controller with Independent Bias Supply Can be configured as 2-Independent or 2-Phase PWM Controller Programmable Current Sharing in 2-Phase Configu- ration Flexible, Same or Separate Supply Operation Operation from 4V to 25V Input Programmable Switching Frequency up to 400KHz Soft-Start controls all outputs Precision Refe...

L0805180JEWTR

D/C:07+

Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications.

L08051R8CEWTRM0T

D/C:07+

NOTE: 1. These inputs are normally wired to VCC, GND, or unconnected. Internal termination resistors bias unconnected inputs to VCC/2. If these inputs are switched, the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.

L08051R8DEWTR

D/C:07+

The MB3836 is a lithium-ion battery protection IC for three cells series lithium-ion battery pack in a notebook PCs. This IC supports charging at 12.6 V and detects an over-charge, over-discharge, and over-current to control charging and discharging.

L0805220GEWTR

The active polarity of CLPDM and SHP (active high or active low) can be chosen through the serial interface, refer to serial interface for details. The default value of CLPDM and SHP is active low. However, right after power on, this value is unknown. For this reason, it must be set to the appropriate value by using the serial interface, or reset to the default value by the RESET pin. The description and t...

L0805220JEWTR

D/C:72529

The output signals of the SDA 9188-3X are analog. Either RGB or Y, U, V signals can be output, whereby a 6-bit broadband conversion is obtained for all components. Clamping for RGB output signal is performed in an RGB processor (e.g. TDA 4685).

L08052R7CEWTR

D/C:07+

Vo Adjust: This pin is used to trim the output voltage to a value within the range of 10 % of nominal. The adjust- ment method uses an external resistor. The resistor is connected from Vo Adjust to either the (-)Sense or (+)Sense, in order to adjust the output up or down, respectively.

L08052R7DEWTR

D/C:07+

*1 L08052R7DEWTR, L08052R7DEWTR/M, L08052R7DEWTR, L08052R7DEWTR, L08052R7DEWTR/M, L08052R7DEWTR/M, L08052R7DEWTR, L08052R7DEWTR/M, L08052R7DEWTR/M, L08052R7DEWTR *2 L08052R7DEWTR, L08052R7DEWTR *3 Follow the derating curve. When Tj exceeds 150C, the internal circuit cuts off the output. L08052R7DEWTRxxM series is mounted on a standard board (glass epoxy: 20mm 20mm t1.7mm with Cu foil of 1cm2 or more).

L08053R3CEWTR

D/C:07+

The MSK 4370 is a complete 3 Phase IGBT Bridge Brushless Motor Control System in an electrically isolated hermetic package. The hybrid is capable of 10 amps of output current and 500 volts of DC bus voltage. It has the normal features for protecting the bridge. Included is all the bridge drive circuitry, hall sensing circuitry, commutation circuitry and all the current sensing and analog circuitry necessary...

L08053R3DEWTRMDT

Vendor:AVXPackage Cooled:3R3-0805

L08053R9CEWTR

Vendor:AVXD/C:05+

RAB = 5 kΩ, Code = 0x20 RAB = 10 kΩ, Code = 0x20 RAB = 50 kΩ, Code = 0x20 RAB = 100 kΩ, Code = 0x20 VA =1 V rms, RAB = 10 kΩ, VB = 0 V DC, f = 1 kHz VA= 5 V 1 LSB error band, VB = 0, measured at VW VA = 5 V 1 LSB error band, VB = 0, measured at VW VA = 5 V 1 LSB error band, VB = 0, measured at VW RAB = 5 kΩ, f = 1 kHz, Code = 0x20 RAB = 10 kΩ, f = 1 kHz, Co...

L08053R9CEWTRM

D/C:07+

*CPU: PGA 478 for Intel Pentium 4 CPU with Hyper-Threading Technology up to 3.2GHz *Bus Interface: PICMG Bus *Front Side Bus: Supports 400/533/800MHz FSB *Memory: Two DDR sockets supporting DDR-266/333/400 up to 2GB *Chipset: Intel 82865GV/82801EB *I/O Chipset: Winbond W83627 *ISA Bridge: ITE IT8888 (16-bit) *VGA: Intel 82865GV with 1MB/8MB/16MB shared main memory supporting CRT display up to 1600 x 1...

L08053R9DEWTRM0T

D/C:07+

This is the supply voltage for the regulator control circuitry. For the device to regulate, this voltage should be between 0.9 V and 1.3 V (depending on the output current) greater than the output voltage. The control pin current will be about 1.0% of the output current.

L08055R6CEWTR

D/C:07+

Security functions Security functions implemented in the cabinet: -Mechanical case lock as option -Intrusion detection as option -Prepared for Kensington lock for access and theft protection -Eye for padlock for access and theft protection -Seal option -Access protection via SmartCard reader as option Security function implemented in the BIOS: -Boot protection with SmartCard optional -Write protect opti...

L08055R6CEWTR

D/C:07+

Security functions Security functions implemented in the cabinet: -Mechanical case lock as option -Intrusion detection as option -Prepared for Kensington lock for access and theft protection -Eye for padlock for access and theft protection -Seal option -Access protection via SmartCard reader as option Security function implemented in the BIOS: -Boot protection with SmartCard optional -Write protect opti...

L08055R6DEWTR

D/C:07+

MuxIt is a family of general-purpose, multiple-chip building blocks for implementing parallel data serializers and deserializers. The system allows for wide parallel data to be transmitted through a reduced number of transmission lines over distances greater than can be achieved with a single-ended (e.g., LVTTL or LVCMOS) data interface. The number of bits multiplexed per transmission line is user-selecta...

L08056R5DEWTR

Vendor:AVXPackage Cooled:805D/C:07+

For applications requiring powerful I/O capabilities, the Z86319 provides dedicated input and output lines that are grouped into three ports. There are two basic address spaces available to support this configuration: Program Memory, and 125 bytes of general-purpose registers.

L08056R5DEWTRM0T

D/C:07+

Reset Pin. Low input resets the chip. Schmitt Trigger input. Suspend Pin "L": Suspend Mode H: Normal Mode Crystal Oscillator Output, Connect Crystal Resonator. Connect capacitor Crystal Oscillator Input, Connect Crystal Resonator. Connect capacitor System PLL loop filter Pin. Connect 2.7kΩ resistor and 22nF capacitor in series externally. Codec PLL loop filter Pin. Connect 120k͐...

L08058R2DEWTR

The Loop Filter is a low-pass filter. This low-pass filter eliminates high frequency spectral components from a phase error signal produced by the Phase Detector. This ensures low output jitter that meets network jitter requirements. The corner frequency of the Loop Filter is configurable with an external capacitor and resistor connected to the LPF ball and ground as shown in Figure 3.

L080CWR5B

L0814K7

L081C104

L081C223LF

L081C333LF

L081C472

L081C560LF

L081S103

Vendor:BI TECHNOLOGIESD/C:05+

• SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC 3.3V Power Supply User Selectable 3.3V/2.5V I/O 12000 PLD Gates / 256 Macrocells Up to 192 I/O Pins 256 Registers High-Speed Global Interconnect SuperWIDE 32 Generic Logic Block (GLB) Size for Optimum Performance SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc. PCB Efficient B...

L081S183LF

L081S472LF

L081S473

Vendor:biPackage Cooled:biD/C:dc04

The L081S473 operates from 7 to 13.2 volt DC supplies. They are specifically designed for video signal switching which requires extremely low differential phase and gain. Logic inputs are TTL and 5 volt CMOS compatible providing address and chip select functions. When the chip is not selected, the output goes to a high impedance state.

L083C103

1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition X = dont care = LOW-to-HIGH CP transition

L083C123LF

L083C151LF

L083C184LF

L083C202

L083C271

L083C330LF

L083C331LF

L083C332LF

L083C390LF

L083C471LF

L083C511

L083C682LF

L083S102

Protection circuitry is provided onboard for overload condi- tions. In conditions where the device reaches temperatures exceeding the specified maximums, an onboard circuit shuts down the output, where it remains suspended until it has cooled before re-enabling. The user is also free to shut down the device using the Enable control pin at any time.

L083S102LF

L083S152LF