LL2012F8N2K

Note 2: When the input voltage (VI) at any pin exceeds the power supplies (VI < GND or VI > +VS) the current at that pin should be limited to 5 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four.

LL2012-FH12NJ

D/C:07+

The programmable features of the ICS84321 support two in- put modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transi...

LL2012-FH12NJ

D/C:07+

The programmable features of the ICS84321 support two in- put modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transi...

LL2012-FH12NK

Vendor:TOKOPackage Cooled:0805-12NKD/C:08+

100KEP PECL/ECL compatible differential output. PECL/ECL termination is with a 50Ω resistor to VCC C2V. Unused single-ended outputs must have a balanced load. For ACCcoupled applications, the output stage emitter follower must have a DC current path to ground. See Termination section.

LL2012-FH15NJ

D/C:07+

Note 1: The SOIC package used is thermally enhanced through the use of a fused integral leadframe. The power rating is based on a printed circuit board heat spreading capability equivalent to 2 square inches of copper connected to the GND pins. Typical multi-layer boards using power plane construction will provide this heat spreading ability without the need for additional ded- icated copper area. (Ple...

LL2012-FH15NJ

D/C:07+

Note 1: The SOIC package used is thermally enhanced through the use of a fused integral leadframe. The power rating is based on a printed circuit board heat spreading capability equivalent to 2 square inches of copper connected to the GND pins. Typical multi-layer boards using power plane construction will provide this heat spreading ability without the need for additional ded- icated copper area. (Ple...

LL2012-FH18NJ

D/C:07+

At enable voltages greater than 0.4V but less than 0.8V the outputs will remain off but the sleep current may be greater than 1µA. SINK X current matching is greatest percentage delta between output currents with respect to the mean, with VSINK X both at 1V and 5V and RSET = 1.54KΩ. 3Dropout is defined as the SINKX to GND voltage at which the output current sink drops 10% from the nominal value.

LL2012-FH2N2S

Vendor:TOKOPackage Cooled:0805-2N2SD/C:08+

WRITE PROTECT: When the WP pin is low, program and erase operations to all sectors except for the 64-Kbyte top boot sector cannot be performed regardless of the state of the Sector Locking Registers. See the Sector Protection section on page 16 for more details. If the WP pin is high, then hardware write protection for all of the sectors except the top boot sector will be disabled. Register-based sector ...

LL2012-FH33NJ

Vendor:TOKOD/C:08+

LL2012-FH68NJ

D/C:90000

In the normal mode, these devices are functionally equivalent to the F245 and ABT245 octal bus transceivers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPE ™ octal bus transceivers.

LL2012-FH82NJ

Vendor:TOKOPackage Cooled:N/AD/C:08+

The PAL/NTSC pin determines the default values for the DVE control registers. The default register values have been chosen so that standard PAL or NTSC video will appear at the DAC outputs immediately when a valid input digital video data stream is present and Vmute is Low at reset. The Vmute pin controls the "out of reset" operation of the Analog output signals. When "1" at reset, the ...

LL2012-FH82NJ

Vendor:TOKOPackage Cooled:N/AD/C:08+

The PAL/NTSC pin determines the default values for the DVE control registers. The default register values have been chosen so that standard PAL or NTSC video will appear at the DAC outputs immediately when a valid input digital video data stream is present and Vmute is Low at reset. The Vmute pin controls the "out of reset" operation of the Analog output signals. When "1" at reset, the ...

LL2012-FH8N2J

Vendor:TOKOPackage Cooled:0805-8N2SD/C:08+

The MSA power supply noise rejection filter is required on the host PCB to meet data sheet performance. The MSA filter incorporates an inductor which should be rated 400 mADC and 1 Ω series resistance or better. It should not be replaced with a ferrite. The required filter is illustrated in Figure 3.

LL2012-FHL10NJ

Vendor:TOKOPackage Cooled:06+D/C:~39nH:4000， 47nH~3000PCS/reel

LL2012-FHL12NJ

Vendor:TOKOPackage Cooled:06+D/C:~39nH:4000， 47nH~3000PCS/reel

LL2012-FHL1N5S

D/C:07+

The ISTS200_ series of transmissive photointerrupters are single channel switches consisting of a Gallium Arsenide infrared emitting diode coupled to a high speed integrated circuit detector. The output incorporates a Schmitt trigger which provides hysteresis for noise immunity and pulse shaping. The gap in the plastic housing provides a means of interrupting the signal with an opaque material, sw...

LL2012-FHL22NJ

Vendor:TOKOPackage Cooled:06+D/C:~39nH:4000， 47nH~3000PCS/reel

LL2012-FHL56NJ

Vendor:TOKOPackage Cooled:06+D/C:~39nH:4000， 47nH~3000PCS/reel

LL2012-FHL68NJ

Vendor:TOKOPackage Cooled:06+D/C:~39nH:4000， 47nH~3000PCS/reel

Designed primarily for use with vacuum-fluorescent displays, the UCN5818AF and UCN5818EPF smart power BiMOS II drivers combine CMOS shift registers, data latches, and control circuitry, with bipolar high- speed sourcing outputs and DMOS active pull-down circuitry. The high- speed shift register and data latches allow direct interfacing with microproces- sor LSI-based systems. A CMOS serial data output e...

LL2012-FHL68NJ

Vendor:TOKOPackage Cooled:06+D/C:~39nH:4000， 47nH~3000PCS/reel

Designed primarily for use with vacuum-fluorescent displays, the UCN5818AF and UCN5818EPF smart power BiMOS II drivers combine CMOS shift registers, data latches, and control circuitry, with bipolar high- speed sourcing outputs and DMOS active pull-down circuitry. The high- speed shift register and data latches allow direct interfacing with microproces- sor LSI-based systems. A CMOS serial data output e...

LL2012-FHL82NJ

Vendor:TOKOPackage Cooled:06+D/C:~39nH:4000， 47nH~3000PCS/reel

LL2012-FHLR15J

Vendor:TOKOPackage Cooled:06+D/C:~39nH:4000， 47nH~3000PCS/reel

LL2012-FHLR22J

D/C:07+

Positive analog supply pin. This pin should be connected to a quiet voltage source of +3.0V to +3.6V. VA and VD should have a common supply and be separately bypassed with 10 µF to 50 µF capacitors in parallel with 0.1 µF capacitors.

LL2012-FHLR22J

D/C:07+

Positive analog supply pin. This pin should be connected to a quiet voltage source of +3.0V to +3.6V. VA and VD should have a common supply and be separately bypassed with 10 µF to 50 µF capacitors in parallel with 0.1 µF capacitors.

LL2012-FHLR27J

Vendor:TOKOPackage Cooled:06+D/C:~39nH:4000， 47nH~3000PCS/reel

LL2012FHLR33J

The CAT64LC10/20/40 is a 1K/2K/4K-bit Serial EEPROM which is configured as 64/128/256 registers by 16 bits. Each register can be written (or read) serially by using the DI (or DO) pin. The CAT64LC10/20/40 is manufactured using Catalysts advanced CMOS

LL2012-FHLR33J

D/C:07+

D/A Converter Sampling Clock For Y Signal (PCK) Chroma Subcarrier (NTSC : 3.7595MHz, PAL : 4.4336MHz) Burst Flag Pulse Video Composite SYNC signal Line Atternate Pulse For PAL D/A Converter Sampling Clock for C Signal (4Fsc) Y Video Signal Output

LL2012-FHLR33J

D/C:07+

D/A Converter Sampling Clock For Y Signal (PCK) Chroma Subcarrier (NTSC : 3.7595MHz, PAL : 4.4336MHz) Burst Flag Pulse Video Composite SYNC signal Line Atternate Pulse For PAL D/A Converter Sampling Clock for C Signal (4Fsc) Y Video Signal Output

LL2012-FHLR56J

Vendor:TOKOPackage Cooled:06+D/C:~39nH:4000， 47nH~3000PCS/reel

LL2012-FHR12J

Vendor:TOKOPackage Cooled:0805-R12D/C:05+

Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com- mands are masked when /CS is registered high. /CS provides for external bank selection on systems with multiple banks. /CS is considered part of the command code.

LL2012-FHR12J

Vendor:TOKOPackage Cooled:0805-R12D/C:05+

Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com- mands are masked when /CS is registered high. /CS provides for external bank selection on systems with multiple banks. /CS is considered part of the command code.

LL2012-FHR15J(0805-150NH)

LL2012-FHR18J

Vendor:TOKOD/C:05+

a VCA gain of 8 dB and gives C9.8 dBu (250 mV) before limiting. Both have a noise gate threshold of C64 dBu (500 µV), below which downward expansion reduces the gain with a ratio of approximately 1:3. That is, a C3 dB reduction of output signal occurs with a C1 dB reduction of input signal. For applications requiring adjustable noise gate threshold, VCA gain up to 18 dB, and adjustable rotation po...

LL2012-FHR22J

3Msps Sampling ADC with Two Simultaneous Differential Inputs 1.5Msps Throughput per Channel Low Power Dissipation: 14mW (Typ) 3V Single Supply Operation 2.5V Internal Bandgap Reference with External Overdrive 3-Wire Serial Interface Sleep (10µW) Shutdown Mode Nap (3mW) Shutdown Mode 80dB Common Mode Rejection at 100kHz 0V to 2.5V Unipolar Input Range Tiny 10-Lead MS Package

LL2012-FHR27J

Vendor:TOKOPackage Cooled:805D/C:07+

The EM39LV040 provides two software methods to detect the completion of a Program or Erase cycle in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the write operati...

LL2012-FHR39J

D/C:07+

Ground. Oscillator input. Oscillator output. Active high reset. (with internal pull-down resistor) Key scan input 0. (Schmitt-trigger with 10K/33K/50K pull-up resistor) Key scan input 1. (Schmitt-trigger with 10K/33K/50K pull-up resistor) Key scan input 2. (Schmitt-trigger with 10K/33K/50K pull-up resistor) Key scan input 3. (Schmitt-trigger with 10K/33K/50K pull-up resistor) Key scan input 4. (Schmitt-trig...

LL2012-FR10J

D/C:07+

recalls the last state of a pin when it is three-stated, thus reducing system noise in bus-interface applications. Bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connections to VCC or GND.

LL2012-FR10K

D/C:07+

This demonstrates that with more complex devices the con- cept of CPD greatly simplifies the calculation of total power consumption. It becomes an easy task to compute power for different voltages and frequencies by use of Figure 6 and the equations above.

LL2012-FR12J

D/C:07+

The Hynix HYM7V73AC801B H-Series are 8Mx72bits ECC Synchronous DRAM Modules. The modules are composed of nine 8Mx8bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, two 18bits driver ICs in 56pin TSSOP package, one PLL clock driver in 24pin TSSOP package and one 2Kbits EEPROM in 8pin TSSOP package on a 168pin glass-epoxy printed circuit board. A 0.22uF and a 0.0022uF decoupling capacitors per each ...

LL2012-FR12J

D/C:07+

The Hynix HYM7V73AC801B H-Series are 8Mx72bits ECC Synchronous DRAM Modules. The modules are composed of nine 8Mx8bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, two 18bits driver ICs in 56pin TSSOP package, one PLL clock driver in 24pin TSSOP package and one 2Kbits EEPROM in 8pin TSSOP package on a 168pin glass-epoxy printed circuit board. A 0.22uF and a 0.0022uF decoupling capacitors per each ...

LL2012-FR18J

Vendor:TOKOD/C:05+

An output capacitor of at least 10uF must be used to insure stability of the regulator. Additional capacitance may be added as required to improve the dynamic response of the regulator. Solid tantalum and/or ceramic capacitors are recommended.

LL2012-FR18K

D/C:07+

The chip embeds IEEE 802.3 MAC functions for each port and these functions support full and half duplex modes for both 10 and 100 Mbits/s data rates and full duplex for 1000 Mbit/s. Each port includes dedicated receive and transmit FIFOs with necessary logic to implement flow control for both full and half duplex modes. TC9208M uses IEEE 802.3x frame based flow control for full duplex and backpressure for h...

LL2012-FR22K

D/C:07+

Four differential pairs of LVDS outputs Drives 50- or 100-ohm load (selectable) Low input capacitance Low output skew Does not exceed Bellcore 802.3 standards Operation at ⇒ 350 MHz C 700 Mbps Low propagation delay Typical (tpd < 4 ns) Industrial versions available Packages available include TSSOP/SOIC

LL2012-FR27J

D/C:07+

When the device is operating as a timing master, the internal digital PLL is in use. In this mode, an external 20.000 MHz crystal is required for the on-chip crystal oscillator. The DPLL is phase-locked to one of four input reference signals (which can be 8 kHz, 1.544, 2.048, 4.096, 8.192, 16.384 or 19.44 MHz provided on REF0 - 3). The on-chip DPLL operates in normal, holdover or freerun mode and offers jitt...

LL2012-FR27K

Vendor:TOKOD/C:05+

‡ This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow. The PowerPAD must be soldered to a thermal land on the printed-circuit board. See the application note PowerPAD Thermally Enhanced Package (SLMA002)

LL2012-FR33K

Vendor:TOKOD/C:05+

2.1.1 Specifications, standards, and handbooks. The following specifications, standards, and handbooks form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DODISS) and supplement thereto, cited in the solicitation (see 6.2).

LL2012-FR33K(0805-330NH)

LL2012-FR39J

D/C:07+

This 16-bit edge-triggered D-type flip-flop is built using advanced dual metal CMOS technology. The ALVCH16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at ...

LL2012-FR39K

D/C:07+

Slew rate limited drivers on the ISL8487E and ISL81487L reduce EMI, and minimize reflections from improperly terminated transmission lines, or unterminated stubs in multidrop and multipoint applications. Data rates up to 250kbps are achievable with these devices.

LL2012-FR39K

D/C:07+

Slew rate limited drivers on the ISL8487E and ISL81487L reduce EMI, and minimize reflections from improperly terminated transmission lines, or unterminated stubs in multidrop and multipoint applications. Data rates up to 250kbps are achievable with these devices.

LL2012-FR47J

Vendor:TOKOD/C:05+

The DS3150 performs all the functions necessary for interfacing at the physical layer to DS3, E3, and STS-1 lines. The receiver performs clock and data recovery, B3ZS/HDB3 decoding, and loss-of-signal monitoring. The transmitter encodes outgoing data and drives standards-compliant waveforms onto 75Ω coaxial cable. The jitter attenuator can be mapped into the receive path or the transmit path.

LL2012-FR47J

Vendor:TOKOD/C:05+

The DS3150 performs all the functions necessary for interfacing at the physical layer to DS3, E3, and STS-1 lines. The receiver performs clock and data recovery, B3ZS/HDB3 decoding, and loss-of-signal monitoring. The transmitter encodes outgoing data and drives standards-compliant waveforms onto 75Ω coaxial cable. The jitter attenuator can be mapped into the receive path or the transmit path.

LL2012-FR47K

D/C:07+

Note 5: Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress ratings only. Functional operation of the device is only implied at these or any other conditions in excess of those given in the operation sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability

LL2012N180MT

D/C:07+

Selectable loop filter bandwidth of 29 Hz or 922 Hz Less than 24 psrms intrinsic jitter on the 19.44 MHz output clock, compliant with GR-253- CORE OC-3 and G.813 STM-1 specifications Less than 0.6 nspp intrinsic jitter on all PDH output clocks and frame pulses Selectable external master clock source: clock oscillator or crystal Simple hardware control interface

LL2012N4R7KT

Vendor:TOKOPackage Cooled:N/AD/C:08+

B ild / Fig. 9 G renzstrom je Zweig (OV)M . Bel astung au s Leer lauf, VRM = 0,8 VRRM Maximum ove rload on- sta te current per arm I T(OV)M. Surge curren t unde r n o-load condi tion s, VR = 0,8 VRRM a - t A = 3 5 C, verstä rkte Luftkhlu ng / forced cooling b - t A = 4 5 C, Lu ftse lbstkhlu ng / natural cooling

LL2012N8R2KT

Vendor:TOKOPackage Cooled:N/AD/C:08+

The oscillator determines the frequency of the output voltage. This is defined by an external capacitor, C2. It is charged with a constant current, I, until the upper switching threshold is reached. A second current source is then activated which taps a double cur- rent, 2 I, from the charging current. The capacitor, C2 , is thus discharged by the current, I, until the lower switching threshold is reached...

LL244

Vendor:TIPackage Cooled:TSSOP48

LL244

Vendor:TIPackage Cooled:TSSOP48

LL245

Vendor:TIPackage Cooled:TSOP48

Figure 6 is a plot of absolute linearity and relative linearity versus wiper position for the DS1267 at 25C. The specification for absolute linearity of the DS1267 is 0.75 MI typical. The specification for relative linearity of the DS1267 is 0.3 MI typical.

LL24V/C

LL2703

Vendor:IORPackage Cooled:08+D/C:80000

Note: Hitachis serial EEPROM are authorized for using consumer applications such as cellular phone, camcorders, audio equipment. Therefore, please contact Hitachis sales office before using industrial applications such as automotive systems, embedded controllers, and meters.

LL2703

Vendor:IORPackage Cooled:08+D/C:80000

Note: Hitachis serial EEPROM are authorized for using consumer applications such as cellular phone, camcorders, audio equipment. Therefore, please contact Hitachis sales office before using industrial applications such as automotive systems, embedded controllers, and meters.

LL2705

Vendor:IORPackage Cooled:08+D/C:80000

dt of greater than 10 kV/µs. This clamp circuit has a MOSFET that is enhanced when high dV/dt spikes occur between MT1 and MT2 of the TRIAC. When conducting, the FET clamps the base of the pho- totransistors, disabling the firs stage SCR predriver The 600/800 V blocking voltage permits control of off- line voltages up to 240 VAC, with a safety factor of more than two, and is sufficient for as m...

LL3303

Package Cooled:08+D/C:800

The FM pre-amplifier input FMIN (Pin 28) consists of a transistor grounded base circuit (T2) which provides excellent noise performance and large signal behavior. It is recommended to connect a source impedance of 100 W in order to achieve optimal performance. The dc current through the amplifying transitor is reduced by the internal AGC. This means in the case of large input signals, the input ac cur...

LL34LL4148

Vendor:TAIWANPackage Cooled:SOT-34D/C:N/A

The MM54HCT573 MM74HCT573 octal D-type latches and MM54HCT574 MM74HCT574 Octal D-type flip flops ad- vanced silicon-gate CMOS technology which provides the inherent benefits of low power consumption and wide power supply range but are LS-TTL input and output characteristic pin-out compatible The TRI-STATE outputs are capable of driving 15 LS-TTL loads All inputs are protected from damage due to stati...

LL4.7V

The DSP distinguishes between hardware interrupts and soft- ware exceptions, handling them differently. When a software exception occurs, the DSP aborts all other instructions in the instruction pipe. When a hardware interrupt occurs, the DSP continues to execute instructions already in the instruction pipe.

LL4001-4007

Vendor:N/APackage Cooled:N/AD/C:08+09+

Positive driver supply pin for the ADC12DL065s output drivers. This pin should be connected to a voltage source of +2.4V to VD and be bypassed to DR GND with a 0.1 µF capacitor. If the supply for this pin is different from the supply used for VA and VD, it should also be bypassed with a 10 µF capacitor. VDR should never exceed the voltage on VD. All 0.1 µF bypass capacitors should be ...

LL4001G

Package Cooled:1WRD/C:08+

The ADSP-BF535 Blackfin processor is a highly integrated system-on-a-chip solution for the next generation of digital com- munication and portable Internet appliances. By combining industry-standard interfaces with a high performance signal processing core, users can develop cost-effective solutions quickly without the need for costly external components. The ADSP-BF535 Blackfin processor system periph...

LL4004

Vendor:TOSD/C:2000

NOTE : 1.Serial PD interface is standard IIC architecture. 2.Pull-up resistors(4.7K typical value) are required on all open collector bus devices(SCL and SDA). 3.Current sink capability on SCL and SDA (Iol max) must be at least 3mA to maintain a valid low level. 4.Checksum can be obtained by adding the binary values in Byte 0-62, and eliminate all but low order byte. The low order byte would be the `Check...

LL4007

Vendor:东芝

The output at pin 5 is at a ÒhighÓ state when the PLL is out of lock and goes to a ÒlowÓ or conducting state when the PLL is locked. It is an open collector output and requires a pull-up resistor, RL, to +VS for proper operation. In the ÒlowÓ state it can sink up to 5 mA of load current.

LL4107SB00014D2

Vendor:gsPackage Cooled:gsD/C:dc00

C 4 mA output sink and source current C Error checking of the configuration bitstream C Soft startup starts all outputs in slew-limited mode upon power-up C Easy migration to the XC3400 series of HardWire mask programmed devices for high-volume production.

LL4107SB00014D2

Vendor:gsPackage Cooled:gsD/C:dc00

C 4 mA output sink and source current C Error checking of the configuration bitstream C Soft startup starts all outputs in slew-limited mode upon power-up C Easy migration to the XC3400 series of HardWire mask programmed devices for high-volume production.

LL4148 SMD

LL4148(GS08)

Vendor:VISHAY

− Conforms to USB specification Rev. 1.1 − Supports 1 device address and 2 endpoints 8-bit micro-processor − RISC-like architecture − USB optimized instruction set − Single cycle instruction execution − Operation Speed: DC to 24 MHz clock input − Performance: 12 MIPS @ 24MHz I/O ports − 7-port hub Internal memory − 64 bytes of RAM − 1.75...

LL4148-7 VISHAY LL34 99+

LL4148-7-F

Vendor:DIODES ?Package Cooled:04+?D/C:7500

VOLBGATB low voltage to CVINB−VINA = −48 V, −VINB = 0 V VOLBGATB high voltage to −VINB−VINA = 0 V, −VINB = −48 V † All voltages are with respect to RTN unless otherwise stated. ‡ Currents are positive into and negative out of the specified terminal.

LL4148-BJL

LL4148F/SOD80

LL4148FSB00014D2

Vendor:VISHAY

LL4148GS

LL4148-GS08 F

LL4148GS0850

Vendor:vishayPackage Cooled:vishayD/C:dc0410

LL4148GS18

Vendor:vishayPackage Cooled:vishayD/C:dc04

• Packaged in 16 pin SOIC or TSSOP • Uses fundamental 10 - 27 MHz crystal, or clock • Patented PLL with the lowest phase noise • Output clocks up to 156 MHz at 3.3 V • Low phase noise: -132 dBc/Hz at 10 kHz • Output Enable function tri states outputs • Low jitter - 18 ps one sigma • Full swing CMOS outputs with 25 mA drive capability at TTL levels &#...

LL4148GS18

Vendor:vishayPackage Cooled:vishayD/C:dc04

• Packaged in 16 pin SOIC or TSSOP • Uses fundamental 10 - 27 MHz crystal, or clock • Patented PLL with the lowest phase noise • Output clocks up to 156 MHz at 3.3 V • Low phase noise: -132 dBc/Hz at 10 kHz • Output Enable function tri states outputs • Low jitter - 18 ps one sigma • Full swing CMOS outputs with 25 mA drive capability at TTL levels &#...

LL4148-GS18

Vendor:VISHAYPackage Cooled:LL34D/C:08+

For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Infineon AG iGr, may only be used in life-support devices or systems2 with the express written approval of t...

LL4148-GS18

Vendor:VISHAYPackage Cooled:LL34D/C:08+

For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Infineon AG iGr, may only be used in life-support devices or systems2 with the express written approval of t...

LL4148S

LL4148T/R

LL4148-TP-TF

LL4148WS

Vendor:STPackage Cooled:ORG PACKINGD/C:08+

DESCRIPTION These dual channel diode-darlington optocouplers use a pair of light emitting diodes and an integrated high gain photon detectors to provide 2500Volts RMS electrical isolation between input and output. Seperate connection for the photodiode bias and output darlington collector improve the speed up to a hundred times that of a conventional photo- darlington coupler by reducing the base-...

LL4150

Vendor:VISHAYPackage Cooled:LL34D/C:08+

The EZ-KIT Lite is a hardware/software kit offering a complete evaluation environment for the ADSP-218x family: an ADSP- 2189M-based evaluation board with PC monitor software plus assembler, linker, simulator, and PROM splitter software. The ADSP-2189M EZ-KIT Lite is a low cost, easy to use hardware platform on which you can quickly get started with your DSP software design. The EZ-KIT Lite includes th...

LL4150GS08

Vendor:VISHAYD/C:ORIGINAL

Single, Dual, Triple, or Quad Integrated Transmitter, Receiver, and Jitter Attenuators for DS3, E3, and STS-1 Each Port Independently Configurable Perform Receive Clock/Data Recovery and Transmit Waveshaping Hardware or CPU Bus Configuration Options Jitter Attenuators can be Placed in Either the Receive or Transmit Paths Interface to 75W Coaxial Cable at Lengths Up to 380m (DS3), 440m (E3), or 360m (STS-1...

LL4150GS08

Vendor:VISHAYD/C:ORIGINAL

Single, Dual, Triple, or Quad Integrated Transmitter, Receiver, and Jitter Attenuators for DS3, E3, and STS-1 Each Port Independently Configurable Perform Receive Clock/Data Recovery and Transmit Waveshaping Hardware or CPU Bus Configuration Options Jitter Attenuators can be Placed in Either the Receive or Transmit Paths Interface to 75W Coaxial Cable at Lengths Up to 380m (DS3), 440m (E3), or 360m (STS-1...

LL4150-GS08

Vendor:TEMICD/C:05+

The Fairchild Switch FST3245 provides 8-bits of high- speed CMOS TTL-compatible bus switching in a standard 245 pin-out. The low on resistance of the switch allows inputs to be connected to outputs without adding propaga- tion delay or generating additional ground bounce noise.

LL4150GSO8

LL4151

D/C:09+

The COP8SAx instruction set utilizes many single-byte, mul- tifunction instructions. This enables a single instruction to ac- complish multiple functions, such as DRSZ, DCOR, JID, and LOAD/EXCHANGE instructions with post-incrementing and post-decrementing, to name just a few examples. In many cases, the instruction set can simultaneously execute as many as three functions with the same single-byte inst...

LL4151F

Vendor:ittPackage Cooled:ittD/C:dc90

CS falling edge to first SCLK falling edge. SCLK logic high pulse width. SCLK logic low pulse width. Valid data setup time before falling edge of SCLK. Data hold time after SCLK falling edge. Minimum time between the end of data byte transfers. Minimum time between byte transfers during a serial write. CS hold time after SCLK falling edge.

LL4151GS08

Vendor:tfkPackage Cooled:tfkD/C:dc00

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

LL4151GS08

Vendor:tfkPackage Cooled:tfkD/C:dc00

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

LL4154-GS08

The LL4154-GS08 transceiver integrates the coaxial cable interface functions of the Medium Attachment LL4154-GS08nit (MALL4154-GS08) in Ethernet or Cheapernet LAN applications. In an Ethernet 10Base5 network, LL4154-GS08 is mounted on the thick Ethernet coaxial cable and connects to a station through an ALL4154-GS08I cable. For Cheapernet applications, LL4154-GS08 is connected to the Cheapernet coaxial cabl...