LT1215

LT12158

Package Cooled:N/A

LT1215ACN8

A single heat source, centered in the silicon chip is suspended across a cavity. Equally spaced aluminum/polysilicon thermopiles (groups of thermocouples) are located equidistantly on all four sides of the heat source (dual axis). Under zero acceleration, a temperature gradient is symmetrical about the heat source, so that the temperature is the same at all four thermopiles, causing them to output th...

LT1215CN8PBF

The ACQ/ACTQ245 contains eight non-inverting bidirec- tional buffers with 3-STATE outputs and is intended for bus- oriented applications. Current sinking capability is 24 mA at both the A and B ports. The Transmit/Receive (T/R) input determines the direction of data flow through the bidirec- tional transceiver. Transmit (active-HIGH) enables data from A Ports to B Ports; Receive (active-LOW) enables d...

LT1215CS

Vendor:LTPackage Cooled:SOP8D/C:06+

The two single-ended charge-pump power stages operate in the push-pull operating mode (i.e., they operate with a 180C phase shift). Each single-ended charge pump transfers a charge into its flying capacitor (C1 or C2) in one-half of the period. During the other half of the period (transfer phase), the flying capacitor is placed in series with the input to transfer its charge to the load and output capacit...

LT1215CS8PBF

Vendor:ＬＴ

Octal bidirectional bus interface Non-inverting 3-state outputs Multiple package options Complies with JEDEC standard no. 7A ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V s Specified from −40 C to +85 C and from −40 C to +125 C

LT1215CS8TR

Vendor:LTPackage Cooled:9750+D/C:2500

Single Voltage, Range 3V to 3.6V Supply 3-Volt-Only Read and Write Operation Software Protected Programming Fast Read Access Time - 150 ns Low Power Dissipation 15 mA Active Current 50 µA CMOS Standby Current Sector Program Operation Single Cycle Reprogram (Erase and Program) 512 Sectors (128 words/sector) Internal Address and Data Latches for 128 Words Fast Sector Program Cycle Time - 20 m...

LT1215MJ8/883

LT1216CS-T

LT1216CSTR

For readers already familiar with the XC4000/Spartan and XC3000 FPGA Families, this section describes significant differences between them and the XC5200 family. Unless otherwise indicated, comparisons refer to both XC4000/Spartan and XC3000 devices.

LT12171CQ-TR

Vendor:LTD/C:06+

The peripheral logic integrates a PCI bridge, memory controller, DMA controller, PIC interrupt controller, I2O controller, and an I2C controller. The MPC603e core is a full-featured, high-performance processor with floating-point support, memory management, a 16-Kbyte instruction cache, a 16-Kbyte data cache, and

LT12179

Package Cooled:N/A

LT12179CS

Vendor:LTPackage Cooled:SMDD/C:N/A

organized as 32,768 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reli- able process coupled with innovative circuit design tech- niques, yields fast access times with low power consumption.

LT1217CN8PBF

LT1217CS8PBF

Vendor:LINEARD/C:2007

These very small, low cost filters are intended for use with A-D and D-A video converters where some deviation from full ITU-R BT601 standard can be tolerated, ie single pass applications. These filters are designed for use in 4:2:2 sampling systems, ie 13.5 MHz for the luminance (Y) channel and 6.75 MHz for the chrominance (U and V) channels.

LT1217CS8TR

This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.04 / Jun.01Hynix Semiconductor

LT1218

Vendor:LTC

The MT88L70 is a complete 3 Volt, DTMF receiver integrating both the bandsplit filter and digital decoder functions. The filter section uses switched capacitor techniques for high and low group filters; the decoder uses digital counting techniques to detect and decode all 16 DTMF tone-pairs into a 4-bit code. External component count is minimized by on chip provision of a differential input amplifier, clock ...

LT1218LCS8

Vendor:LINEAR

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Defense Supply Center, Columbus, ATTN: DSCC-VAC, P.O. Box 3990, Columbus, OH 43216-5000, by using the Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

LT1218LCS8PBF

These EPROMs and OTP PROMs operate from a single 5-V supply (in the read mode), thus are ideal for use in microprocessor-based systems. One other 13-V supply is needed for programming. All programming signals are TTL level. The device is programmed using the SNAP! Pulse programming algorithm. The SNAP! Pulse programming algorithm uses a VPP of 13 V and a VCC of 6.5 V for a nominal programming time of seve...

LT1219

Vendor:LTPackage Cooled:1

Synchronous circuitry allows for precise cycle control triggered by a positive edge clock transition. Synchronous signals include : all Addresses, all Data Inputs, all Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV), Clock Enable (CKE#), Byte Write Enables (BWa#, BWb#, BWc#, BWd#) and Read/Write (W#). Write operations are controlled by the four Byte Write Enables (BWa# - BWd#) and Read/Write(W#) ...

LT1219CN8

Vendor:LINEAR TECHNOLOGYD/C:05+

The Inhibit pin is an open-collector/drain-negative logic input that is referenced to GND. Applying a low-level ground signal to this input disables the module's output. When the Inhibit control is active, the input current drawn by the regulator is significantly reduced. If the Inhibit pin is left open-circuit, the module will produce an output voltage whenever a valid input source is applied.

LT1219CN8

Vendor:LINEAR TECHNOLOGYD/C:05+

The Inhibit pin is an open-collector/drain-negative logic input that is referenced to GND. Applying a low-level ground signal to this input disables the module's output. When the Inhibit control is active, the input current drawn by the regulator is significantly reduced. If the Inhibit pin is left open-circuit, the module will produce an output voltage whenever a valid input source is applied.

LT1219CS8

Vendor:LINEAR

The LT1219CS8 is a microPower, low-cost operational amplifier available in micropackages. The LT1219CS8 (single version) is available in the SC-70 and SOT23-5 packages. The LT1219CS8 (dual version) is available in the SOT23-8 and WCSP-8 packages. Both are also available in the SO-8. The LT1219CS8 is also available in the DIP-8. The LT1219CS84347 (quad) is available in the SO-14 and the TSSOP-14.

LT1219CT

Vendor:LINEAR

LT1219LCS8TR

!Features 1) Built-in bias resistors enable the configuration of an inverter circuit without connecting external input resistors (see equivalent circuit). 2) The bias resistors consist of thin-film resistors with complete isolation to allow negative biasing of the input. They also have the advantage of almost completely eliminating parasitic effects. 3) Only the on/off conditions need to be set for op...

LT1219LCS8TRPBF

Vendor:N/APackage Cooled:N/AD/C:08+09+

LT121A

Vendor:LINEARPackage Cooled:SOPD/C:30

LT121A1

Vendor:LINEARPackage Cooled:SOP-8D/C:08+

The device is entirely command set compatible with the JEDEC single-power- supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an in- ternal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Re...

LT121A13

Vendor:Linear TechnologyD/C:05+

The LT121A13 is a VFD (Vacuum Fluorescent Display) controller/driver that is driven on a 1/8- to 1/16 duty factor (include key scan). It consists of 12 segment/key scan output lines, 8 grid output lines, 8 segment/grid output drive lines, a display memory, a control circuit, and a key scan circuit. Serial data is input to the LT121A13 through a four-line serial interface.

LT121A5

Vendor:Linear TechnologyD/C:05+

The APA4863 is a stereo bridge-tied audio power am- plifier in various power packages , including SOP , TSSOP and TSSOP-P . When connecting to a 5V volt- age supply , the APA4863 is capable of delivering 2.2W/1.8W/1.2W of continuous RMS power per chan- nel into 3Ω/4Ω/8Ω bridge-tied loads with less than 1% THD+N respectively . When APA4863 operates in the single-ended load , it is capable of...

LT121AHV

Vendor:LTPackage Cooled:SOD/C:04

Negative Input Terminal Positive Input Terminal Positive Remote sense Negative Remote sense Positive Output Terminal Negative Output Terminal Inverter Good Signal Output adjustment trim pin On/Off Control Terminal Current Monitor Signal

LT121AI5/I3

Vendor:LTPackage Cooled:NULLD/C:05+

It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph.

LT121AICS8.

D/C:1

The devices are stable with capacitive loads up to 10 nF, although the 6-MHz bandwidth decreases to 1.8 MHz at this high loading level. As such, the TLE214x and TLE214xA are useful for low-droop sample-and-holds and direct buffering of long cables, including 4-mA to 20-mA current loops.

LT121AIS-5

Vendor:LTPackage Cooled:SMDD/C:20

Memory encompasses 4 KB of Flash for program storage, 256 bytes of SRAM for data storage, and up to 2 KB of EEPROM emulated using the Flash. Program Flash utilizes four protec- tion levels on blocks of 64 bytes, allowing customized software IP protection.

LT121AIS-5

Vendor:LTPackage Cooled:SMDD/C:20

Memory encompasses 4 KB of Flash for program storage, 256 bytes of SRAM for data storage, and up to 2 KB of EEPROM emulated using the Flash. Program Flash utilizes four protec- tion levels on blocks of 64 bytes, allowing customized software IP protection.

LT121AIS8-3

Vendor:LTPackage Cooled:SMDD/C:20

Guaranteed Logic HIGH Level Guaranteed Logic LOW Level Standard Input(4), VCC = Max. Standard I/O(4), VCC = Max. Bus Hold Input(5), VCC = Max. Bus Hold I/O(5), VCC = Max. Standard Input(4), VCC = Min. Standard I/O(4), VCC = Min. Bus Hold Input(5), VCC = Min. Bus Hold I/O(5), VCC = Min. Bus Hold Input(5), VCC = Min.

LT121AIS8-5

Vendor:LINEARPackage Cooled:SMDD/C:1863

The matte tin finish on Sirenzas lead-free package utilizes a post annealing process to mitigate tin whisker formation and is RoHS Product Features compliant per EU Directive 2002/95. This package is also manu- • Now available in Lead Free, RoHS factured with green molding compounds that contain no antimony Compliant, & Green Packaging trioxide nor halogenated fire retardants.

LT121CS8

Vendor:LINEARPackage Cooled:04D/C:300

Notes: (1) Clip mounting (on case), where lead does not overlap heatsink with 0.110" offset (2) Clip mounting (on case), where leads do overlap heatsink (3) Screw mounting with 4-40 screw, where washer diameter is 4.9 mm(0.19") (4) Pulse test,300µs pulse width,1% duty cycle

LT121I33

Vendor:LT

LT121I33

Vendor:LT

LT121I5(1121IS8-5)

Vendor:LINEARPackage Cooled:SOP

LT121IS

Vendor:LTPackage Cooled:NULLD/C:05+

ISP1161A provides two downstream ports for the USB HC and one upstream port for the USB DC. Each downstream port has an overcurrent (OC) detection input pin and power supply switching control output pin. The upstream port has a VBUS detection input pin. ISP1161A also provides separate wake-up input pins and suspended status output pins for the USB HC and the USB DC, respectively. This makes power manageme...

LT121IS-5

Vendor:LTPackage Cooled:SMDD/C:96

• Four Crystal modes, up to 40 MHz • 4x Phase Lock Loop (PLL) C available for crystal and internal oscillators) • Two External RC modes, up to 4 MHz • Two External Clock modes, up to 40 MHz • Internal oscillator block: - 8 user selectable frequencies, from 31 kHz to 8 MHz - Provides a complete range of clock speeds from 31 kHz to 32 MHz when used with PLL - User ...

LT121IS8

Vendor:LINEARPackage Cooled:SMDD/C:2468

8. CPD, measured per function, is used to determine the dynamic power consumption. PD (per package) = VCC ICC + (VCC2 fl CPD + VO2 fO CL + VCC ∆lCC D) where: VCC = supply voltage ∆lCC = flow through current x unit load CL = output load capacitance D = duty cycle of input high fO = output frequency fI= input frequency

LT121IS8

Vendor:LINEARPackage Cooled:SMDD/C:2468

8. CPD, measured per function, is used to determine the dynamic power consumption. PD (per package) = VCC ICC + (VCC2 fl CPD + VO2 fO CL + VCC ∆lCC D) where: VCC = supply voltage ∆lCC = flow through current x unit load CL = output load capacitance D = duty cycle of input high fO = output frequency fI= input frequency

LT121IS8.

Vendor:LTPackage Cooled:SOPD/C:06+

• Superior Performance in Outdoor Environments • Wavelengths Suitable for Color Mixing in Full Color (RGB) Signs • Color to Color Consistency of Radiation Patterns (CBxx to CMxx to HLMP-DGxx Red) Enables Sign Color Uniformity at All Angles

LT121IS8-3

Edition 1998-04-08 Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, 81541 Mnchen © Siemens AG 1998. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information descr...

LT121IS8-5

Available in various package configurations, these two families of detector diodes provide low cost solutions to a wide variety of design problems. Hewlett-Packards manufacturing techniques assure that when two diodes are mounted into a single SOT-323 package, they are taken from adjacent sites on the wafer, assuring the highest possible degree of match.

LT121S1-101

Vendor:3D/C:LCD

This device is a low-cost, high-speed, JFET-input operational amplifier with very low input offset voltage. It requires low supply current yet maintains a large gain-bandwidth product and a fast slew rate. In addition, the matched high-voltage JFET input provides very low input bias and offset currents.

LT121S1-105W1

LT121SL-105

Vendor:10D/C:LCD

LT121SS-105-121

LT121SS-105-W1(1)

LT1220

Vendor:LTC

access for a read or program can begin. The typical num- ber of program and erase cycles is in excess of 10,000 cycles. The optional 16K bytes boot block section includes a repro- gramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is perma- nently protected from being reprogrammed.

LT1220CJ8

Vendor:LTD/C:O9+

This method corresponds more accurately to the method of test and provides a closer estimate of actual error than the other methods. The box method guarantees limits for the temperature error but does not specify the exact shape or slope of the device under test.

LT1220CJ8

Vendor:LTD/C:O9+

This method corresponds more accurately to the method of test and provides a closer estimate of actual error than the other methods. The box method guarantees limits for the temperature error but does not specify the exact shape or slope of the device under test.

LT1220CN8

Vendor:9Package Cooled:LTD/C:N/A

The CMOS XC3000 Class of Logic Cell Array (LCA) families provide a group of high-performance, high-den- sity, digital integrated circuits. Their regular, extendable, flexible, user-programmable array architecture is com- posed of a configuration program store plus three types of configurable elements: a perimeter of I/O Blocks (IOBs), a core array of Configurable Logic Bocks (CLBs) and re- sources for...

LT1220CS8

Note 1 Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices should be operated at these limits The table of Recommended Operating Conditions and Electrical Characteristics provides conditions for actual device operation

LT1220CS8PBF

Vendor:LINEARD/C:2007

The HY29F400s sector erase architecture allows any number of array sectors to be erased and re- programmed without affecting the data contents of other sectors. Device erasure is initiated by executing the Erase command. This initiates an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase cycles, the devic...

LT1220CS8TR

Stress in excess of Absolute Maximum Rat- ings may cause permanent damage. Absolute Maximum Ratings, sometimes referred to as no destruction limits, are normally tested with one parameter at a time exceeding the limits of Output data or Electrical Charac- teristics. If exposed to stress above these limits, function and performance may de- grade in an unspecified manner.

LT1221

Vendor:LTPackage Cooled:SMD-8

(Note 1) (Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG7912A/SG7912 with -55C TA 150C, VIN = -19V, IO = 500mA for the K and IG -Power Packages-, IO = 100mA for the T and L packages, CIN = 2µF, and COUT = 1.0µF. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperatu...

LT1221CN8

Vendor:LTPackage Cooled:DIP-8D/C:03+

• High-speed access time: 8, 10, and 12 ns • CMOS low power operation • Low stand-by power: Less than 5 mA (typ.) CMOS stand-by • TTL compatible interface levels • Single 3.3V power supply • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial temperature availab...

LT1221CN8

Vendor:LTPackage Cooled:DIP-8D/C:03+

• High-speed access time: 8, 10, and 12 ns • CMOS low power operation • Low stand-by power: Less than 5 mA (typ.) CMOS stand-by • TTL compatible interface levels • Single 3.3V power supply • Fully static operation: no clock or refresh required • Three state outputs • Data control for upper and lower bytes • Industrial temperature availab...

LT1221CN8PBF

As with all power integrated circuits, the UDN2987A and UDN2987LW have a maximum allowable output current rating. The 500 mA rating does not imply that operation at that value is permitted or even obtainable. The channel output current trip point is specified as -370 mA, minimum; therefore, attempted operation at current levels greater than -370 mA may cause a fault indication and channel shutdown. ...

LT1221CS

The TL750L, TL751L series are low-dropout regulators. This means that capacitance loading is important to the performance of the regulator because it is a vital part of the control loop. The capacitor value and its equivalent series resistance (ESR) both affect the control loop and must be defined for the load range and temperature range. Figure 1 shows the recommended range of ESR for a given load with a...

LT1221CS8

Vendor:LTPackage Cooled:SOP8D/C:N/A

Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed speci- fications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance character- istics may degrade when the device is not operated under the listed test condit...

LT1222

Vendor:LTC

The PALCE29MA16 has 29 inputs to drive each product term (up to 58 inputs with both TRUE and complement versions available to the AND array) as shown in the block diagram in Figure 1. Of these 29 inputs, 4 are dedicated inputs, 16 are from eight I/O logic macrocells with two feedbacks, 8 are from other I/O logic macro- cells with single feedback and one is the I/OE input.

LT1222CN8

TTL/CMOS input enable pin. Used to control the LOUT0-LOUT2 outputs and acts as a frequency select pin. LEN, DSEL, and LSEL are used together to decode the selection and post divide of the LVDS output bank, see the LVDS Output Post- Divider and Frequency Select Table for proper decoding. Internal 25kΩ pull-up. When disabled, LOUT0-LOUT2 outputs are LOW, and the complimentary outputs are HIGH. The thresh...

LT1222CN8PBF

* Start-up by SPEED key a. function turn off (OFF key) b. wind mode select (MODE key) c. start-up function and wind speed select (SPEED key) d. timer setting (TIMER key) e. swing head or tuner for swing angle (SW1 and SW2 key) f. lighting control (LIGHT key)

LT1222CS

Vendor:LTPackage Cooled:SOP8D/C:06+

Modem Control Output For external modem, these pins are bit7~4 of the modem control output. Memory address mapping of the controller is C800H. Modem Control Input For external modem, these pins are bit3~0 of the modem control input. Memory address mapping of the controller is C800H. +3.3V Power Supply

LT1222CS8

Vendor:LTPackage Cooled:SOP8D/C:N/A

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to an FR4 board using 0.5 sq in pad size. 2. W...

LT1222I

Vendor:LTPackage Cooled:SOP8D/C:100

LT1222I

Vendor:LTPackage Cooled:SOP8D/C:100

LT1222IS8

Vendor:LINEAR TECHNOLOGYD/C:05+

The LT1222IS8 is a CAN physical interface device, dedicated to automotive body electronic multiplexing applications. It operates in differential mode, allowing ground shifts up to 1,5V, reducing RFI disturbances. It offers very low standby current in sleep and standby mode operation and supports communication speeds up to 125kBauds. It is fully protected against harsh automotive environments and the drive...

LT1222IS8

Vendor:LINEAR TECHNOLOGYD/C:05+

The LT1222IS8 is a CAN physical interface device, dedicated to automotive body electronic multiplexing applications. It operates in differential mode, allowing ground shifts up to 1,5V, reducing RFI disturbances. It offers very low standby current in sleep and standby mode operation and supports communication speeds up to 125kBauds. It is fully protected against harsh automotive environments and the drive...

LT1223CN8

Vendor:LTPackage Cooled:DIP-8

Notes: 1. TA is the instant on case temperature. 2. See the last page of this specification for Group A subgroup testing information. 3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 4. VIL (Min.) is equal to C3.0V for pulse durations less than 20 ns. 5. The leakage current is due to the internal pull-up resistor on all pins. 6. Not ...

LT1223CN8/CS8

Vendor:LINEARPackage Cooled:SOP-8D/C:05+

The 128Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 128Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and th...

LT1223CN8/CS8

Vendor:LINEARPackage Cooled:SOP-8D/C:05+

The 128Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 128Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and th...

LT1223CS

Vendor:ADPackage Cooled:SOP8D/C:06+

The GLT41116 is a 65,536 x 16 bit high-performance CMOS dynamic random access memory. The GLT41116 offers Fast Page mode, and has both BYTE WRITE and WORD WRITE access cycles via two CAS pins. The GLT41116 has symmetric address and accepts 256-cycle refresh in 4ms interval.

LT1223CS

Vendor:ADPackage Cooled:SOP8D/C:06+

The GLT41116 is a 65,536 x 16 bit high-performance CMOS dynamic random access memory. The GLT41116 offers Fast Page mode, and has both BYTE WRITE and WORD WRITE access cycles via two CAS pins. The GLT41116 has symmetric address and accepts 256-cycle refresh in 4ms interval.

LT1223CS8

Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do ...

LT1223CS8PBF

Vendor:LINEARD/C:2007

initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions.

LT1223CS8TR

Vendor:LINEARPackage Cooled:SOP8D/C:04+

tsk(pp)Part-to-part skew3ns ‡ Output skew (tsk(o)) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together. Part-to-part skew (tsk(pp)) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same input signals, the same supply voltages, at th...

LT1223CS8TR

Vendor:LINEARPackage Cooled:SOP8D/C:04+

tsk(pp)Part-to-part skew3ns ‡ Output skew (tsk(o)) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together. Part-to-part skew (tsk(pp)) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same input signals, the same supply voltages, at th...

LT1223MJ8/883

Vendor:LTPackage Cooled:06+D/C:800

LT1223MJ8/883

Vendor:LTPackage Cooled:06+D/C:800

LT1224

Vendor:LTC

LT1224CN8-ES

Vendor:LTPackage Cooled:DIP

LT1224CS8TRPBF

Vendor:N/APackage Cooled:N/AD/C:08+09+

This product can also be used on telephone, signal/data lines, security, timing and control interface circuits. For most applications, the product should be located as close as possible to the equipment being protected. A low impedance grounding system is impor- tant to maintain a low voltage clamp between the line-to-ground connection.

LT1224IS8

Vendor:LTPackage Cooled:SMD8

Mechanical stress performance is a greater considera- tion for a UCSP. UCSP solder-joint contact integrity must be considered because the package is attached through direct solder contact to the users PC board. Testing done to characterize the UCSP reliability performance shows that it is capable of performing reliably through environmental stresses. Results of environmental stress tests and additional usage...

LT1225CN8

Vendor:LTPackage Cooled:DIP8D/C:92+

This device contains protection circuitry to guard against damage due to high static volt- ages or electric fields. However, precautions must be taken to avoid applications of any volt- age higher than maximum rated voltages to this highCimpedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an ap- pro...

LT1225CN8PBF

Vendor:N/APackage Cooled:N/AD/C:08+09+

LT1226CN8

Vendor:N/APackage Cooled:100D/C:N/A

! High-speed 8-bit microprocessor interface allowing direct connection to both the 8080 and 6800 ! Serial interface ! Single supply operation, 2.4 - 3.5V ! Maximum 9V LCD driving output voltage ! 2X / 3X / 4X on chip DC-DC converter ! Voltage regulator ! Voltage follower (LCD bias: 1/5 or 1/6) ! On chip oscillator

LT1226IN8

LT1227CS

Vendor:LTPackage Cooled:SOP8D/C:06+

NOTE: *Maximum IF(ON) is the maximum current required to trigger the output. For example, a 1.6mA maximum trigger current would require the LED to be driven at a current greater than 1.6mA to guarantee the device will turn on. A 10% guard band is recom- mended to account for degradation of the LED over its lifetime. The maximum allowable LED drive current is 60mA.

LT1227CS8PBF

Erase Verify Command Following each erase, all bytes must be verified. The erase verify is initiated by writing Erase Verify Command (A0H) to the command latch, while the address to be verified is latched on the falling edge of the WE pulse. The erase verify command must be written to the command latch and each address is latched before each byte is verified. The operation continues for each byte until ...

LT1227CS8TRPBF

Freescale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Freescale Semiconductor does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are n...

LT1227IS8

Vendor:LINEARD/C:04+

A: The value of R JA is measured with the device mounted on 1in2 FR-4 board with 2oz. Copper, in a still air environment with TA=25C. The value in any a given application depends on the user's specific board design. The current rating is based on the t 10s thermal resistance rating. B: Repetitive rating, pulse width limited by junction temperature. C. The R JA is the sum of the thermal impedence from junctio...

LT1228

Vendor:LTC

− Output is software selectable as modulating or nonmodulating frequency − Works as frequency output specified by Timer 1 • Built-in 14-bit clock frequency divider circuit • Two built-in 8-bit programmable countdown timers

LT1228CN8PBF

Note 1: At TA = -40C, DC characteristics are guaranteed by design and characterization. Note 2: CML outputs open. Note 3: RL = 50Ω to VCC. Note 4: AC characteristics are guaranteed by design and characterization. Note 5: Relative to the falling edge of SCLKO+. See Figure 2. Note 6: Measured with 223 - 1 PRBS. Note 7: Jitter BW = 12kHz to 20MHz. Note 8: RATESET = low. Note 9: RATESET = high.