M 16N SAMPLE

Vendor:NSPackage Cooled:SOP.16D/C:06+

M 28 W 640 CT-70 ZA 6

M 53245P

Vendor:MITPackage Cooled:DIP

M C14526BCL

M P7670AS

M TAPC64013ABLL3A

Vendor:LUCENTPackage Cooled:BGAD/C:0036+

M TAPC64013ABLL3A

Vendor:LUCENTPackage Cooled:BGAD/C:0036+

M TAPC64013BBLL3B

Package Cooled:AGERED/C:07+/08+

M TAPC64013BBLL3B

Package Cooled:AGERED/C:07+/08+

M TAPCE64013

Package Cooled:AGERED/C:07+/08+

M TAPCE64013

Package Cooled:AGERED/C:07+/08+

M/5328

M/C0402GRM36C0G270F5027PF50V-1C0GMURATA

M/C06030.1UF25V80-20SAMSUNG

M/C06031000PF50V-10X7R

M/C060310PF50V-5

M/C0603150PF50V-5

M/C06033300PF50V-10

M/C0603390PF50V-10X7R

M/C06036800PF50V-10

M/C0603CL10B102KB0.001UF50V-10X7RSAMSUNG

M/C0603ECJ-1VC1H470J47PF50V-5NP0PANASONIC

M/C0805GRM40X7R334K25U5000.33UF25V-10X7RMURATA

M/C1210C3225X5R1A106KT10UF10V-10X5RTDK

M/C18081000PF1KV(-20)(X7R)

M0001

Vendor:MOTPackage Cooled:03+D/C:800

Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

M001191

Vendor:MOT

DESCRIPTION The CLP30-200B1 is designed to protect telecommunication equipment. It provides both a transient overvoltage protection and an overcurrent protection. The external components (balanced resistors, ring relays contact, ...) needed by the CLP30-200B1 protection concept require very low power rating. This results in a very cost effective protection solution.

M002064

D/C:20

M002-1000

Vendor:SATCOMPackage Cooled:QFPD/C:97+

Due to an integrated 3rd order sigma delta converter, which samples the MPX signal, all further processing is done in the digital domain and therefore very economical. After filtering the highly oversampled output of the A/D converter, the RDS/RBDS demodulator extracts the RDS DataClock , RDS Data Signal and the Quality information. A next RDS/RBDS decoder will synchronize the bitwise RDS stream to a gro...

M003401HH

M003401NH

Vendor:MOTOROLAPackage Cooled:PLCC-28D/C:06+

The CS4398 is a complete stereo 24 bit/192 kHz digital- to-analog system. This D/A system includes digital de- emphasis, half dB step size volume control, ATAPI channel mixing, selectable fast and slow digital interpo- lation filters followed by an oversampled multi-bit delta- sigma modulator that includes mismatch shaping tech- nology that eliminates distortion due to capacitor mismatch. Following this stag...

M003401NH

Vendor:MOTOROLAPackage Cooled:PLCC-28D/C:06+

The CS4398 is a complete stereo 24 bit/192 kHz digital- to-analog system. This D/A system includes digital de- emphasis, half dB step size volume control, ATAPI channel mixing, selectable fast and slow digital interpo- lation filters followed by an oversampled multi-bit delta- sigma modulator that includes mismatch shaping tech- nology that eliminates distortion due to capacitor mismatch. Following this stag...

M0047100

M0048042

Vendor:RKMSPackage Cooled:00+D/C:DIP-40

When this input pin transitions from LOW to HIGH, a playback cycle is initiated. Playback continues until PLAYL is pulled LOW, an end-of-message marker is detected, or the end of the memory space is reached. The device automatically powers down to standby mode upon completion of the playback cycle. This pin has an internal pull-down device. Holding this pin HIGH will increase standby current consumption.

M0098B

Vendor:NEC

M00N1

M00NM4

Vendor:MITELPackage Cooled:SSOPD/C:N/A

The FAN5240 is a single output 2-Phase synchronous buck controller to power AMDs mobile CPU core. The FAN5240 includes a 5-bit digital-to-analog converter (DAC) that adjusts the core PWM output voltage from 0.925VDC to 2.0VDC, which may be changed during operation. Special measures are taken to allow the output to transition with controlled slew rate to comply with AMDs Power Now technology. T...

M00NM4KGQP1T

The initial application of the VCC supply requires a 200-µs wait followed by a minimum of any eight initialization cycles containing a RAS clock. During Power-On, the VCC current is dependent on the input levels of RAS and CAS. It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges.

M010A

Vendor:NULLPackage Cooled:QFPD/C:NULL

The external resistors allow the user to accurately and independently set each amplifier transconductance by applying a voltage to each resistor, without restriction on the voltage range, thus ensuring broad voltage DAC compatibility. Alternatively, the IIN pin can be biased from a current DAC or other current source.

M01101JT52

M0116A00021/AIT

Vendor:INFINEONPackage Cooled:PLCC68D/C:04+

* Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

M0118B11

Die TUHI Serie ist eine Familie von 1.5 W DC/DC Wandler. Sie bieten kostengnstige Lösungen in Indu- strie-, Datenkommunikation-, Medizin- und Telecoman- wendungen wo sehr hohe Anforderungen an die Isolation gestellt sind. Ein 100 % Burn-in und Test der Sicherheitstrennung mit 8000 V garantieren den sehr hohen Qualitätsstandard dieser Produkte.

M0122A

Vendor:NEC

This pin is used to connect the base of an external PNP transistor. The output voltage is controlled by an internal op-amp to maintain it stably at 5V. Since the recommended current of IOUT is 5mA, an output current of up to 600mA can be flowed if HFE of the external transistor is 120 or more.

M012NJ100

M013786

Vendor:EXPRESSPackage Cooled:PLCC84

M0140Y

loop timing applications to assure PLL tracking, especially during GR-253 jitter tolerance testing. The recommended maximum phase detector frequency for loop timing mode is 19.44MHz. When LOL is to be used for system health monitoring, the phase detector frequency should be 5MHz or greater. Low phase detector frequencies make LOL overly sensitive, and higher phase detector frequencies make LOL less ...

M0157AW-D

Vendor:ATMELPackage Cooled:PLCC-32D/C:1999

M0157ML-D

Vendor:TEMICPackage Cooled:PLCC44D/C:01+

The ISTS200_ series of transmissive photointerrupters are single channel switches consisting of a Gallium Arsenide infrared emitting diode coupled to a high speed integrated circuit detector. The output incorporates a Schmitt trigger which provides hysteresis for noise immunity and pulse shaping. The gap in the plastic housing provides a means of interrupting the signal with an opaque material, sw...

M0157ML-D.M0157MQ-B

Vendor:MHSPackage Cooled:PLCC44D/C:94.96

M019E1

D/C:94

The RI output of the CH1817 is diode protected. Therefore, an external pull-up resistor (R>100Kohm) to +5V may be utilized to activate the ring detection circuit when the CH1817 is not connected to power. This can be handy in designs where power consumption is of concern. When circuited in this manner, there is virtually no current draw until a ring signal is present.

M01N60

Vendor:STANSOND/C:03+

Core C ARM7TDMI 32-bit RISC CPU C 32 MIPS @ 36 MHz Temperature Range C Operating temperature range -40 to 105 C Memories C Up to 256 Kbytes FLASH program memory (10,000 cycles endurance, data retention 20 years at 55C) C 16 Kbytes RAM Clock, Reset and Supply Management C 4.5 - 5.5V application supply and I/O interface C Embedded 1.8V regulator for core supply C Embedded oscillator running fr...

M02044C-06-T

Vendor:REELD/C:0422+

n Fully integrated 10 Mbps Ethernet transceiver Comprehensive Auto-Negotiation implementation IEEE 802.3u-compliant MII Full-duplex operation supported on the MII port with independent Transmit (TX) and Receive (RX) channels Optimized for 10BASE-T applications n Compliant with HomePNA specification 1.1 n General Purpose Serial Interface (GPSI)/Serial Peripheral Interface (SPI) n Extensi...

M02044C-06-T

Vendor:REELD/C:0422+

n Fully integrated 10 Mbps Ethernet transceiver Comprehensive Auto-Negotiation implementation IEEE 802.3u-compliant MII Full-duplex operation supported on the MII port with independent Transmit (TX) and Receive (RX) channels Optimized for 10BASE-T applications n Compliant with HomePNA specification 1.1 n General Purpose Serial Interface (GPSI)/Serial Peripheral Interface (SPI) n Extensi...

M02046G-14

D/C:08+/09+

Specifications in standard type face are for TJ = 25˚C and those with boldface type apply over the full Operating Tempera- ture Range (TJ = −40˚C to +125˚C) Unless otherwise specified. VIN = 12V and IL = 0A, unless otherwise specified.

M02046G-15

D/C:08+/09+

M02-0603GC

M02-0603GC SMD LED 0603 Y3329

M02-0603GT-MS V4104

M02066-21

Package Cooled:BGA

This MOSFET is an enhancement-mode silicon-gate power field-effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to be radiation tolerant. The MOSFET is well suited for applications exposed to radiation environments such as switching regulation, switching converters, motor drives, relay drivers and drivers for high-power bipolar switching transistors ...

M02066-22

Vendor:MINPackage Cooled:06+D/C:800

There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level.

M02068-15-T

Vendor:MINDSPEEPackage Cooled:N/AD/C:0547+

They utilize a versatile 3-wire interface that is compatible with SPI™, QSPI™, MICROWIRE™, and DSP interface standards. Data is presented to the part in the format of a 16-bit serial word. Serial data is available on the SDO pin for daisy-chaining pur- poses. Data readback allows the user to read the contents of the DAC register via the SDO pin.

M02-0805GC

M02-0805IT

M02-0805IT(ROHS)

M02-0805OYC

M02-0805QYC

M02-0805QYC

M0211

Data Setup Time Data Hold Time Address Set-up Time Address Hold Time Chip Select to LD1 Set-up Time Chip Select to LD1 Hold Time LD1 Pulse Width LD1 Negative Edge to LD2 Positive Edge LD2 Pulse Width Chip Select to RD Set-Up Time Chip Select to RD Hold Time RD Pulse Width High Z to Data Valid for Readback Data Valid for Readback to High Z R1 Pulse Width R2 Pulse Width

M0211

Data Setup Time Data Hold Time Address Set-up Time Address Hold Time Chip Select to LD1 Set-up Time Chip Select to LD1 Hold Time LD1 Pulse Width LD1 Negative Edge to LD2 Positive Edge LD2 Pulse Width Chip Select to RD Set-Up Time Chip Select to RD Hold Time RD Pulse Width High Z to Data Valid for Readback Data Valid for Readback to High Z R1 Pulse Width R2 Pulse Width

M02-1206QRC

M02394-06269

M02395-06269

M0250B

Vendor:NEC

M02510JT631

Package Cooled:01+

M0262A

Vendor:NEC

VTEMP LOADING The VTEMP output has very weak drive capability (40µA source, 1µA sink). So care should be taken when attaching circuitry to this pin. Capacitive loading may cause the VTEMP output to oscillate. Simply adding a resistor in series as shown in Figure 2 will prevent oscillations from occurring. To determine the value of the resistor follow the guidelines given in Table 1. The sa...

M0264B

Vendor:NEC

The AD581 can be easily connected with power pnp or power Darlington pnp devices to provide much greater output current capability. The circuit shown in Figure 9 delivers a precision 10 volt output with up to 4 amperes supplied to the load. The 0.1 µF capacitor is required only if the load has a significant capacitive component. If the load is purely resistive, improved high frequency supply rejec...

M026P120

Vendor:MITPackage Cooled:50D/C:N/A

M027062-3

Vendor:CHIPEXPRESSPackage Cooled:9712D/C:954

3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.

M027127

Vendor:MITPackage Cooled:SSOP

Initialization of both devices must occur before data trans- mission begins. Initialization refers to synchronization of the Serializer and Deserializer PLLs to local clocks, which may be the same or separate. Afterwards, synchronization of the Deserializer to Serializer occurs. Step 1: When you apply VCC to both Serializer and/or Dese- rializer, the respective outputs enter TRI-STATE ® , and on-c...

M0271-395

Vendor:MITPackage Cooled:1150D/C:N/A

After the calculations are performed for a particular crystal, the oscillator circuit should be tested. The following simple checks will verify the prototype design of a crystal controlled oscillator: • Test the oscillator over worse case conditions of min-max operating voltage and temperature.You can also simulate worse case crystal variations by adding series and parallel resistors. • In...

M028941-25

M02N60

Vendor:STANSOND/C:03+

Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan. ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate,

M0304-OD

Vendor:AMID/C:07+

M0304-OD

Vendor:AMID/C:07+

M-035C

Vendor:NEWTECH

M0377A

Vendor:NECPackage Cooled:CAND/C:06+

DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.

M0377A

Vendor:NECPackage Cooled:CAND/C:06+

DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.

M0377B

Vendor:NECPackage Cooled:CAND/C:02+

These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance3-stateandincreased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly a...

M0377B

Vendor:NECPackage Cooled:CAND/C:02+

These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance3-stateandincreased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly a...

M03AB

Vendor:CHARTECPackage Cooled:SOP20

An output enable (OE) pin is provided to three-state the Q0C8 outputs when OE is asserted. When OE is enabled (LOW), data in the output register will be available to the Q0C8 outputs after tOE. If devices are cascaded, the OE function will only output data on the FIFO that is read enabled.

M03ABDS90W

The UV pin is also used to reset the electronic circuit breaker. If the UV pin is cycled low and high following the trip of the circuit breaker, the circuit breaker is reset and a normal power-up sequence will occur. The response time for this pin is 1.5µs. Add an external capacitor to this pin for additional filtering.

M03ETTE-V3C

Vendor:ACTARISPackage Cooled:04+D/C:TQFP-64P

Note 3 The HALT mode will stop CKI from oscillating in the RC and the crystal configurations Halt test conditions All Inputs tied to VCC L C and G port I Os configured as outputs and programmed low D outputs programmed low the window for UV erasable packages is completely covered with an opaque cover to prevent light from falling onto the die during HALT mode test Parameter refers to HALT mode entered via se...

M03ETTE-V3C

Vendor:ACTARISPackage Cooled:04+D/C:TQFP-64P

Note 3 The HALT mode will stop CKI from oscillating in the RC and the crystal configurations Halt test conditions All Inputs tied to VCC L C and G port I Os configured as outputs and programmed low D outputs programmed low the window for UV erasable packages is completely covered with an opaque cover to prevent light from falling onto the die during HALT mode test Parameter refers to HALT mode entered via se...

M0404A

Vendor:NEC

M04-0805T2GC SMD LED0805 Y3320

M0434B

Vendor:NECD/C:00+

Description plastic lead chip carrier; 44 leads plastic dual in-line package; 40 leads (600 mil) plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm plastic lead chip carrier; 44 leads plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm plastic dual in-line package; 40 leads (600 mil)

M0434B

Vendor:NECD/C:00+

Description plastic lead chip carrier; 44 leads plastic dual in-line package; 40 leads (600 mil) plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm plastic lead chip carrier; 44 leads plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm plastic dual in-line package; 40 leads (600 mil)

M0465W

M047D

Vendor:JRCPackage Cooled:DIP-8D/C:n/a

M049E

Vendor:BGAPackage Cooled:32D/C:EPCOS

Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.