M5033T48

Vendor:LUCENTPackage Cooled:QFP-100D/C:98+

Table 2 shows the interrupt vector and DSP-to-DSP semaphores at reset of each of the peripheral interrupts. The peripheral inter- rupts position in the IMASK and IRPTL register and its vector address depend on its priority level, as shown in Table 2.

M5033T48

Vendor:LUCENTPackage Cooled:QFP-100D/C:98+

Table 2 shows the interrupt vector and DSP-to-DSP semaphores at reset of each of the peripheral interrupts. The peripheral inter- rupts position in the IMASK and IRPTL register and its vector address depend on its priority level, as shown in Table 2.

M5034T72

Vendor:LUCENTPackage Cooled:QFP-100D/C:98+

Collector-to-Emitter Voltage Continuous Collector Current Continuous Collector Current Pulsed Collector Current Clamped Inductive Load Current„ Diode Continuous Forward Current Diode Continuous Forward Current Diode Maximum Forward Current Gate-to-Emitter Voltage Maximum Power Dissipation Maximum Power Dissipation Operating Junction and Storage Temperature Range Soldering Temperatur...

M50350-001FP

Vendor:MITSUBPackage Cooled:QFPD/C:2

DESCRIPTION The TL7700Aseriesaremonolithicintegratedcircuit supplyvoltagesupervisorsspecifically desi-gnedfor use as reset controllers in microcomputer and mi- croprocessor systems. During power-up the device tests the supply voltage and keeps the RESET and RESET outputs active (high and low, respectively) as long as the supply voltage has not reached its nominal voltage value. Taking RESIN low has t...

M5041-15

Vendor:OKIPackage Cooled:DIP/22

The PI74FCT162244T has 24 mA balanced output drivers. It is designed with current limiting resistors at its outputs to control the output edge rate resulting in lower ground bounce and undershoot. This eliminates the need for external terminating resistors for most interface applications.

M5041-16

Vendor:OKIPackage Cooled:DIP

The MIC5306 is a micropower, µCap low dropout regulator designed for optimal performance in a small space. It is capable of sourcing 150mA of output current and only draws 16µA of operating current. This high performance LDO offers fast transient response and good PSRR while consuming a minimum of current.

M50414P

Vendor:MITPackage Cooled:DIPD/C:2005+

Stand Alone Switch On A Chip 8 Ethernet 10/100/1000 ports MII/GMII interface for all ports Trunk group support Four Classes of Service (CoS) selectable for each port and/or checked via IP Header and 802.1Q VLAN Tag Eight port-based VLANs Maximum throughput, non head-of-line blocking architecture Embedded SSRAM packet buffer/address table 8K MAC address table Each port is configurable to 10 full/half dup...

M50421

Vendor:MITPackage Cooled:PLCC-72D/C:631109

This is the clock input to the ISD MicroTAD-16M. It is generated by the master device (microcontroller) and is used to synchronize data transfers in and out of the device through the MISO and MOSI lines. Data is latched into the ISD MicroTAD-16M on the rising edge of SCLK and shifted out of the device on the falling edge of SCLK.

M50421P

NOTES: (1) Referred to output in unity-gain difference configuration. Note that this circuit has a gain of 2 for the op amps offset voltage and noise voltage. (2) Includes effects of amplifiers input bias and offset currents. (3) Limit IIN through 40kΩ resistors to 1mA. (4) 40kΩ resistors are ratio matched but have 20% absolute value. (5) Includes effects of amplifiers input current noise and the...

M50422P

Vendor:MITPackage Cooled:QFPD/C:95+

The ispLEVER® design tool from Lattice allows large complex designs to be efficiently implemented using the Latti- ceECP/EC family of FPGA devices. Synthesis library support for LatticeECP/EC is available for popular logic syn- thesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the Lattice...

M50422PA

Package Cooled:QFPD/C:91

USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power is distributed through more than one hub. Each function must provide its own regulated 3.3 V from the 5-V input or from its own internal power supply.

M50422PA

Package Cooled:QFPD/C:91

USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power is distributed through more than one hub. Each function must provide its own regulated 3.3 V from the 5-V input or from its own internal power supply.

M50423FP

Vendor:1Package Cooled:QFP80D/C:N/A

The Am29SL800D is an 8 Mbit, 1.8 V volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-pin TSOP and 48- ball FBGA packages. The word-wide data (x16) appears on DQ15CDQ0; the byte-wide (x8) data appears on DQ7CDQ0. This device is designed to be programmed and erased in-system with a single 1.8 volt VCC supply. No VPP is for write or erase operations. The ...

M50423FP-601

Vendor:MITSUBISHIPackage Cooled:N/AD/C:N/A

Lipofectamine™ 2000 is tested for the absence of microbial contamination using blood agar plates, Sabaraud dextrose agar plates, and fluid thioglycolate medium, and functionally by transfection of CHO-K1 cells with a luciferase reporter-containing plasmid.

M50427FP

Package Cooled:90D/C:1120

NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage rating...

M5042A1

Vendor:ALID/C:05+

The MIC5031 detects an overcurrent condition by comparing the voltage drop across the external MOSFET to a reference voltage drop created across R1. If VDS exceeds VR1, a comparator (not shown) shuts off the external MOSFET by way of the current limit delay, lockout latch, and logic. The bandgap reference, op amp and NPN create a constant voltage (1.23V) across R2. This results in a constant current, ...

M5042-A1Q

Vendor:21280

Output enable puts data outputs into high impedance state Easily expandable in depth and width Independent Read and Write clocks (permit reading and writing simultaneously) Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64- pin Slim Thin Quad Flat Pack (STQFP) High-performance submicron CMOS technology Industrial temperature range (C40C to +85C) is available

M50430

Vendor:MITPackage Cooled:07+D/C:2040

A DEW-B-based bridge acts as an Access Point (AP) for the 802.11 WLAN and coordi- nates the traffic of the packets that are destined outside the WLAN using IP over Ethernet. In case the WLAN user is mobile, roaming functions are also supported at the DEW-B bridge. Its Dual Ethernet MAC architecture is useful in applications where bridg- ing or routing is required between a public network through high speed...

M50430

Vendor:MITPackage Cooled:07+D/C:2040

A DEW-B-based bridge acts as an Access Point (AP) for the 802.11 WLAN and coordi- nates the traffic of the packets that are destined outside the WLAN using IP over Ethernet. In case the WLAN user is mobile, roaming functions are also supported at the DEW-B bridge. Its Dual Ethernet MAC architecture is useful in applications where bridg- ing or routing is required between a public network through high speed...

M50430-081SP

Vendor:MITPackage Cooled:DIP30

Notes: 1. Load and Line Regulation are specified at a constant junction temperature. Pulse testing with low duty cycle is used. Changes in output voltage due to heating effects must be taken into account separately. 2. Short Circuit protection is only assured up to VIN = 35V. 3. If not tested, shall be guaranteed to the specified limits. The • denotes the specifications which apply over the full ...

M50430-082SP

Vendor:MITPackage Cooled:DIP

100EP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 3. VIHCMR max varies 1:1 with VCCI. The VIHCMR range is referenced to the most positive side of the differential input signal.

M50430-088SP

Vendor:MITPackage Cooled:DIPD/C:2005+

M50430-200SP

Vendor:MITPackage Cooled:DIPD/C:2005+

When a liquid comes in contact with the sensing surface and the appropriate signals are applied to the pins, the sensor provides an output that corresponds with the refractive index of the liquid. The output of the Spreetat sensor is a series of analog voltages, one per clock pulse, from which the refractive index of the liquid is derived when the voltages are digitized and processed with the proper algor...

M50430-230SP

Vendor:MITPackage Cooled:DIP-30D/C:902100

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposuretoabsolute-maximum-rated conditions for extended periods may affect device reliability.

M50430-532P

Vendor:MITPackage Cooled:DIP

Now consider what happens to the inductors current during these two states. In State 1, the input voltage is being applied to one side of the inductor, and the output voltage to the other side. For a buck converter, the input voltage is neces- sarily larger than the output voltage, and so there is a net pos- itive voltage across the inductor. Conversely, in State 2, ground is applied to the side of the...

M50430-540SP

Vendor:MITSUBISHIPackage Cooled:DIPD/C:1997

Note) 1. Measuring methods are based on JAPANESE INDUSTRIAL STANDARD JIS C 7030 measuring methods for transistors. 2. * : ∆Gv f is assured for AQL0.065%. (the measurment method is used by source-grounded circuit.)

M50430-582SP

Vendor:MITPackage Cooled:DIPD/C:2005+

Electrical Characteristics / Ta=25C Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current Cutoff Voltage Forward Transfer Admittance Static Drain to Source on State Resistance Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge

M50430-582SP

Vendor:MITPackage Cooled:DIPD/C:2005+

Electrical Characteristics / Ta=25C Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current Cutoff Voltage Forward Transfer Admittance Static Drain to Source on State Resistance Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge

M50431

Vendor:MITPackage Cooled:06+D/C:5000

All parameters measured at fMAX unless noted otherwise. NOTE 1: Assuming input duty cycle specs from Recommended Operating Conditons table are met. NOTE 2: Assuming external crystal or 50% duty cycle external reference is used. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization....

M50431

Vendor:MITPackage Cooled:06+D/C:5000

All parameters measured at fMAX unless noted otherwise. NOTE 1: Assuming input duty cycle specs from Recommended Operating Conditons table are met. NOTE 2: Assuming external crystal or 50% duty cycle external reference is used. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization....

M50431-100

Vendor:MIT

Solderability: 90% coverage after 5 second dip in 235C solder following 60 second preheat at 120C to 150C and type R flux dip. Resistance To Solder Heat: 10 seconds in 260C solder after preheat and flux per above. Termination: 90/10 Sn/Pb. Terminal Strength: 0.1kg for 30 seconds. Beam Strength: 2.5kg.

M50431-101

Vendor:MIT

Blackfin processors provide world class power management and performance. Blackfin processors are designed in a low power and low voltage design methodology and feature dynamic power management, the ability to independently vary both the voltage and frequency of operation to significantly lower overall power consumption. Varying the voltage and frequency can result in a substantial reduction in power co...

M50431-513

Vendor:MITPackage Cooled:DIPD/C:01+

M50431-513

Vendor:MITPackage Cooled:DIPD/C:01+

M50431-513SP

Vendor:MITSUBISPackage Cooled:06+D/C:800

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltag...

M50431-513SP

Vendor:MITSUBISPackage Cooled:06+D/C:800

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltag...

M50431-517SP

M50431-519

Vendor:MITPackage Cooled:DIPD/C:01+

M50431-519SP

Vendor:MIT

Continuous Drain Current, V GS @ 4.5V Continuous Drain Current, V GS @ 4.5V Pulsed Drain Current  Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt ‚ Junction and Storage Temperature Range

M50431-550SP

Receive Clock Tri-statable. The falling edge of this clock output is coincident with the transitions in the serial received DPSK/QAM data output. The rising edge of RXCLK can be used to latch the valid output data. RXCLK will be valid as long as a carrier is present. In V.23 or V.21 mode a clock which is 16 x 1200/75 or 16 x 300 Hz data rate is output, respectively.

M50431-562SP

Vendor:MIT

The AD5381 is a complete, single-supply, 40-channel, 12-bit DAC available in a 100-lead LQFP package. All 40 channels have an on-chip output amplifier with rail-to-rail operation. The AD5381 includes a programmable internal 1.25 V/2.5 V, 10 ppm/C reference, an on-chip channel monitor function that multiplexes the analog outputs to a common MON_OUT pin for external monitoring, and an output amplifier bo...

M50432-551

Vendor:MITPackage Cooled:DIP

Notes: a. Signals on SX, DX, or INX exceeding V+ or VC will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC board. c. Derate 6 mW/_C above 75_C. d. Derate 12 mW/_C above 75_C. e. Derate 7.6 mW/_C above 75_C.

M50432-551SP

Vendor:MITPackage Cooled:DIPD/C:99

Ideal for space critical applications, the LM4041 precision voltage reference is available in the sub-miniature SC70 and SOT-23 surface-mount packages. The LM4041s advanced design eliminates the need for an external stabilizing capaci- tor while ensuring stability with any capacitive load, thus making the LM4041 easy to use. Further reducing design effort is the availability of a fixed (1.225V) and adj...

M50432-551SP

Vendor:MITPackage Cooled:DIPD/C:99

Ideal for space critical applications, the LM4041 precision voltage reference is available in the sub-miniature SC70 and SOT-23 surface-mount packages. The LM4041s advanced design eliminates the need for an external stabilizing capaci- tor while ensuring stability with any capacitive load, thus making the LM4041 easy to use. Further reducing design effort is the availability of a fixed (1.225V) and adj...

M50432B-232SP

NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. Input and output parameters vary 1:1 with VCC. 10. All loading with 50 Ω to VCC−2.0 volts. 11. VIHCMR min varies 1:1 with VEE, V...

M50433B

Vendor:MITSUISHIPackage Cooled:TSOPD/C:08+

Chip Center: X=0µm, Y=0µm Chip Size: X=7.54mm, Y=2.09mm Chip Thickness: 400µm30µm Bump Size: 78.16µm x 48.10µm Pad Pitch: 70µm(Min.) Bump Height: 15µm(Typ.) Bump Material: Au Voltage boosting polarity : Negative Voltage(VDD Common) Substrate:N

M50433B-014SP

RFR6000 Device Features • Compatibility with QUALCOMM's radioOne ZIF chipset eliminates the entire IF, reducing component count and space • Single- or multiband operation: cellular, PCS, GPS • Single- or multimode operation: cellular CDMA, PCS CDMA and GPS • Full downconversion RF to baseband • Receive path circuitry C GPS LNA C Stepped gain control C Three sets of...

M50433B-014SP

RFR6000 Device Features • Compatibility with QUALCOMM's radioOne ZIF chipset eliminates the entire IF, reducing component count and space • Single- or multiband operation: cellular, PCS, GPS • Single- or multimode operation: cellular CDMA, PCS CDMA and GPS • Full downconversion RF to baseband • Receive path circuitry C GPS LNA C Stepped gain control C Three sets of...

M50433B-21SP

M50433B-232SP

Vendor:DAEWOOD/C:07+

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

M50433B-232SP

Vendor:DAEWOOD/C:07+

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

M50433B-232SP T

M50433B-508SP

Vendor:MIT

tpLZ7nsDisable time, low-level-to-high-impedance output (1) All typical values are at 25C and with a 3.3-V supply voltage. (2) tsk(bb), which only applies to the SN65MLVD129, is the magnitude of the difference between the tPLH and tPHL of two outputs of any bank. (3) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operat...

M50433B-508SP

Vendor:MIT

tpLZ7nsDisable time, low-level-to-high-impedance output (1) All typical values are at 25C and with a 3.3-V supply voltage. (2) tsk(bb), which only applies to the SN65MLVD129, is the magnitude of the difference between the tPLH and tPHL of two outputs of any bank. (3) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operat...

M50433B-509

Vendor:MITSUBISHIPackage Cooled:DIPD/C:400

The voice data memory area of the API8208A can be subdivided into 126 sections. Any combination of these sections will form an individual group for data playback. A maximum of eight groups are available with activation controlled by TG1 toTG4 pins. The SBT pin can be used to trigger multiple groups playback in sequence.

M50433B-509SP

Vendor:MITSUBISHIPackage Cooled:DIPD/C:12

Output Voltage Temperature Coefficient • 150 ppm/C, typical Input to Output Capacitance • 50 pF, typical Current Limit • 125% of full load, typical Isolation • 100 megohm minimum at 500 V Conversion Frequency • 600 kHz typical Inhibit Pin Voltage (unit enabled) • 8 to 11 V

M50433B-509SP

Vendor:MITSUBISHIPackage Cooled:DIPD/C:12

Output Voltage Temperature Coefficient • 150 ppm/C, typical Input to Output Capacitance • 50 pF, typical Current Limit • 125% of full load, typical Isolation • 100 megohm minimum at 500 V Conversion Frequency • 600 kHz typical Inhibit Pin Voltage (unit enabled) • 8 to 11 V

M50433B-514SP

Vendor:MITPackage Cooled:DIPD/C:2005+

Operation of the circuit is straight-forward. The motor advances one step each time the step button is released. If the clockwise input is also pressed, the windings will be energized in the order A-AB-B-BC-C-CD-D-DA. Recall that when power is first applied, no winding is energized, to provide a means to sequence the start-up of several motors in larger systems. For this reason, no output will appear...

M50433B-521SP

Vendor:MITPackage Cooled:DIPD/C:2005+

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except ...

M50433B-531SP

Vendor:MITSUBISHIPackage Cooled:DIP42

A 5% resistor value is recommended. In the OOK mode, this pin is usually driven with a logic-level data input (unshaped data pulses). OOK modulation is practical for data pulses of 200 µs or longer. In the ASK mode, this pin accepts analog modulation (shaped or unshaped data pulses). ASK modulation is practical for data pulses 8.7 µs or longer. This pin must be low in the power-down (sleep) mode. ...

M50433B-531SP

Vendor:MITSUBISHIPackage Cooled:DIP42

A 5% resistor value is recommended. In the OOK mode, this pin is usually driven with a logic-level data input (unshaped data pulses). OOK modulation is practical for data pulses of 200 µs or longer. In the ASK mode, this pin accepts analog modulation (shaped or unshaped data pulses). ASK modulation is practical for data pulses 8.7 µs or longer. This pin must be low in the power-down (sleep) mode. ...

M50433B-537

Vendor:MITSUBISHIPackage Cooled:DIPD/C:300

The EC000 processor core communicates with these modules via an internal bus, providing the opportunity for fully synchronized communication between all modules and allowing interrupts to be handled in parallel with data transfers, greatly improving system performance.

M50433B-537SP

Vendor:MITPackage Cooled:DIP

Hynix HYMD132725B(L)8-M/K/H/L series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 32Mx72 high-speed memory arrays. Hynix HYMD132725B(L)8-M/K/ H/L series consists of eighteen 16Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD132725B(L)8-M/K/H/L series provide a high performance 8-byte interface in 5.25&...

M50433B-556SP

Vendor:.Package Cooled:MITSUBISHID/C:03+

− 25-ns Instruction Cycle Time (40 MHz) − 40-MIPS Performance − Low-Power 3.3-V Design Based on TMS320C2xx DSP CPU Core − Code-Compatible With F243/F241/C242 − Instruction Set and Module Compatible With F240/C240 Flash (LF) and ROM (LC) Device Options − LF240xA: LF2407A, LF2406A, LF2403A, LF2402A − LC240xA: LC2406A, LC2404A, LC2403A, LC2402A On-Chip Memory ...

M50433B-560SP

Vendor:MITSUBISHIPackage Cooled:DIPD/C:9

VCC1 is the positive supply voltage pin for the transmitter output amplifier and the transmitter base-band circuitry. VCC1 is usually connected to the positive supply through a ferrite RF decoupling bead which is bypassed by an RF capacitor on the supply side. See the description of VCC2 (Pin 16) for additional information.

M50433B-562SP

Vendor:MIT

Single Supply for Read and Write: 2.7 to 3.6V (BV), 3.0 to 3.6V (LV) Fast Read Access Time - 70 ns Internal Program Control and Timer Sector Architecture C One 16K Byte Boot Block with Programming Lockout C Two 8K Byte Parameter Blocks C Two Main Memory Blocks (96K, 128K Bytes) Fast Erase Cycle Time - 10 seconds Byte-By-Byte Programming - 30 µs/Byte Typical Hardware Data Protection DATA Polling...

M50433B-610SP

Vendor:MITPackage Cooled:DIP-42

Stop Condition. STOPis identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition termi- nates communication between the ST24/25E64 and the bus master. A STOP condition at the end of a Read command forces the standby state. A

M50433B-610SP

Vendor:MIT

Stop Condition. STOPis identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition termi- nates communication between the ST24/25E64 and the bus master. A STOP condition at the end of a Read command forces the standby state. A

M50433B-631SP

Vendor:MIT

The ADC11DL066 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog in- put signals into 11-bit digital words at 66 Megasamples per second (MSPS), minimum. This converter uses a differential, pipeline architecture with digital error correction and an on- chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic per...

M50433B-715SP

Vendor:MITPackage Cooled:DIP-42D/C:00+

M50433R-521SP

Vendor:hot sellPackage Cooled:DIP40PD/C:8100

M50434

Vendor:DIPPackage Cooled:MITSUBISHID/C:04+

Deadtime control input. The deadtime control comparator has an effective 120mV input offset which limits the minimum output dead time. Dead time may be imposed on the output by setting the dead time control input to a fixed voltage, ranging from 0V to 3.3V.

M50434-025SP

Vendor:MITPackage Cooled:DIP/30

The HT24LC16 has a write protect pin that provides hardware data protection. The write protect pin allows normal read/write operations when the connection is grounded. When the write protect pin is connected to VCC, the write protection feature is enabled and oper- ates as shown in the following table.

M50434-026SP

Vendor:MITPackage Cooled:DIPD/C:2005+

Ports • Input/Output Ports: 4 ports (23 terminals) Data direction programmable in nibble units: 1 port (8 terminals) (If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.) Data direction programmable for each bit individually : 3 ports (15 terminals)

M50434-026SP

Vendor:MITPackage Cooled:DIPD/C:2005+

Ports • Input/Output Ports: 4 ports (23 terminals) Data direction programmable in nibble units: 1 port (8 terminals) (If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.) Data direction programmable for each bit individually : 3 ports (15 terminals)

M50434-120SP

Vendor:MITPackage Cooled:DIPD/C:2005+

Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators 17- 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator Exponen...

M50434-122SP

Vendor:MITPackage Cooled:DIPD/C:2005+

M50435-591SP

Vendor:MIT

NOTES: 1. Inputs are capable of translating the following interface standards. User can select between: Single-ended 2.5V LVTTL levels Single-ended 1.8V LVTTL levels or Differential 2.5V/1.8V LVTTL levels Differential HSTL and eHSTL levels Differential LVEPECL levels 2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQ voltage...

M50435-592

Vendor:DIPPackage Cooled:MITSUBISHID/C:03+

The TPS211xA family of power multiplexers enables seamless transition between two power supplies, such as a battery and a wall adapter, each operating at 2.8−5.5 V and delivering up to 1 A. The TPS211xA family includes extensive protection circuitry, including user-programmable current limiting, thermal protection, inrush current control, seamless supply transition, cross-conduction blocking, and re...

M50435-592SP

Vendor:MIT

Two order forms are included at the back of this manual to facilitate customer order for S3C80C5/C80C8 microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative.

M50435-592SP

Vendor:MIT

Two order forms are included at the back of this manual to facilitate customer order for S3C80C5/C80C8 microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative.

M50435-594

Vendor:MITPackage Cooled:DIPD/C:01+

The DLYBLK input can be used to halt address generation at the end of any address block within a sequence. In addition, DLYBLK can be used to delay an address sequence from restarting if asserted at the end of the final address block gen- erated under One-Shot Mode with Restart. See Application Note 9205 for the timing relationship of DLYBLK to the end of the address block required to halt address sequ...

M50435-594SP

Vendor:MIT

1. Startup includes both the application of a valid input source voltage, or the removal of a ground signal from the Inhibit* control (pin 2) with a valid input source applied. The output of the regulator is effectively off (tri-state), during the period that the Inhibit* control is held low.

M50436

Vendor:MITPackage Cooled:06+D/C:5000

• Cost optimized, full custom circuit design 10BASE-T/100BASE-TX/FX IEEE 802.3u Fast • Ethernet transceiver • Power consumption: <280 mW Unique energy detection • power management circuit to enable intelligent Selectable TX drivers for 1:1 or 1.25:1 • enable additional power reduction transformers to • Legacy interface support

M50436

Vendor:MITPackage Cooled:06+D/C:5000

• Cost optimized, full custom circuit design 10BASE-T/100BASE-TX/FX IEEE 802.3u Fast • Ethernet transceiver • Power consumption: <280 mW Unique energy detection • power management circuit to enable intelligent Selectable TX drivers for 1:1 or 1.25:1 • enable additional power reduction transformers to • Legacy interface support

M50436-518SP

Vendor:.Package Cooled:MITSUBISHID/C:03+

The SMA ZenBlock™ is designed to protect the MOSFET in flyback converters against over-voltages caused by the transformer leakage inductance. The SMA ZenBlock™ combines a zener/TVS with a fast soft-recovery diode in one package, and can be used to replace double diode, RC or RCD snubbers.

M50436-560

Vendor:MITPackage Cooled:DIPD/C:1995

Analog output. The output signal has a maximum amplitude of 2.4 VPP above and below the signal ground voltage (VDD/2). The output load resistance is a minimum of 600 W. During power saving, or power down mode, the output of AOUT is at the voltage level of the signal ground.

M50436560SP

M50436-560SP

Vendor:MITPackage Cooled:DIPD/C:99

Now we can examine the value of < f, ( C ä) >. < f, ä > is by definition f(t0) and the other terms of the expansion do not contribute to the result. Since Ø has been normalized, < f(t0), > is f(t0): the ideal result of the sampling event. If we consider the next term: f'(t0) (t-t0) this is a constant

M50436-560SP-EW

Vendor:MITSUBISHIPackage Cooled:N/AD/C:N/A

The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the users own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits...

M50436-561SP

Vendor:MIT

power consumption. Broadband operation gives you high flexibility for multi-band frequency mappings. The IC is available in a shrinked small-outline 28-pin package (SSO28). The U2893B offers the same functionality with other divider ratios.

M50436-561SP

Vendor:MIT

power consumption. Broadband operation gives you high flexibility for multi-band frequency mappings. The IC is available in a shrinked small-outline 28-pin package (SSO28). The U2893B offers the same functionality with other divider ratios.

M50436-566SP

Vendor:MIT

Guaranteed Zero Reading for 0V Input on All Scales True Polarity at Zero for Precise Null Detection True Differential Input and Reference, Direct Display Drive -LCD ICL7106 -LED lCL7107 Low Noise - Less Than 15 µVP-P On Chip Clock and Reference Low Power Dissipation - Typically Less Than 10mW No Additional Active Circuits Required New Small Outline Surface Mount Package Available Four additional...

M50436-589

Vendor:MITPackage Cooled:DIPD/C:01+

This link option selects the source of the CLKIN input. When this link is in position "A" the CLKIN input is provided by the EVAL-CONTROL BOARD. When this link is in position "B" the CLKIN input is provided via the on-board 25MHz oscillator. When this link is in position "C", an external CLKIN signal must be provided via SK1. When using the on-board generated burst clock, this...

M50436-589

Vendor:MITPackage Cooled:DIPD/C:01+

This link option selects the source of the CLKIN input. When this link is in position "A" the CLKIN input is provided by the EVAL-CONTROL BOARD. When this link is in position "B" the CLKIN input is provided via the on-board 25MHz oscillator. When this link is in position "C", an external CLKIN signal must be provided via SK1. When using the on-board generated burst clock, this...

M50436-589SP

Vendor:MITPackage Cooled:DIPD/C:99

Commands are issued to the CSM using standard microprocessor write timings. The CSM acts as an interface between the external microprocessor and the internal WSM. The available commands are listed in Table 1 and the description of these commands are shown in Table 2. When a program or erase command is issued to the CSM, the WSM controls the internal sequences and the CSM only responds to status reads. Af...

M50436-688

Vendor:MITPackage Cooled:DIPD/C:01+

M50436-688

Vendor:MITPackage Cooled:DIPD/C:01+

M50436-688SP

Vendor:MITSD/C:07/08+

The Micrel M50436-688SP is a high efficiency 2MHz PWM synchro- nous buck regulator. The fast 2MHz operation along with a proprietary compensation scheme allows the smallest pos- sible external components. The M50436-688SP can operate with a 1µF ceramic output capacitor and a small, low DC-resis- tance, 2.2µH inductor, reducing system size and cost while allowing a high level of efficiency.

M50436-689SP

Vendor:MITSUBISHIPackage Cooled:DIP52D/C:94+

The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan architecture and the relationship among the test bus, the TAP controller, and the test registers. As shown, the device contains an 8-bit instruction register and three test-data registers: an 18-bit boundary-scan register, a 2-bit boundary-control register, and a 1-bit bypass register.