M04S01

Notes: (i) For operation below 0 C the external capacitors m ust bave stable characteristics. use either a low ESR tantalum, Os-Con, or ceramic capacitor. (ii) During reflow of SMD package version do not elevate peak temperature of the module, pins or internal components above the stated maximum.

M051501B196LD

Package Cooled:BGAD/C:04+

3. "Maximum allowable voltage" is that value at maximum contact rating and maxi- mum ambient temperature. The graph shown in the data describes the inter-rela- tionship; care should be taken to prevent the total of ambient temperature and the coil temperature rise from exceeding 120C.

M051501B196LD

Package Cooled:BGAD/C:04+

3. "Maximum allowable voltage" is that value at maximum contact rating and maxi- mum ambient temperature. The graph shown in the data describes the inter-rela- tionship; care should be taken to prevent the total of ambient temperature and the coil temperature rise from exceeding 120C.

M0546

Vendor:NECPackage Cooled:铁帽子

The PWR5104 and PWR5105 offer a low-cost alternative to other models currently on the market. In addition, these models utilize high frequency switching in order to maintain a low EMI and RFI environment. Both models incorporate input and output filtering along with six-sided shielding to keep unwanted noise from your circuit.

M0599C/DS08

Optimal frequency response for the M0599C/DS08 occurs with load capacitance in the range of 15 pF. For smaller loads, an external capacitor can be added to maximize the bandwidth of the device. As shown in Figure 1, a small resistor, ROUT , should be included in series with the M0599C/DS08 output to obtain optimal response flatness. For a nominal load of 15 pF, ROUT should be chosen to be approximately 40 ...

M05FBRM03BK

Vendor:0Package Cooled:07＋D/C:1053

M0601PD08A

M0603-1B56NJNT

D/C:07+

The XC7336 can be used in systems with two different supply voltages: 3.3 V and 5 V. Each XC7336 device has separate VCC connections to the internal logic (VCCINT) and to the I/O pads (VCCIO). VCCINT must always be con- nected to a 5 V supply. VCCIO may be connected to either 3.3 V or 5 V, depending on the output interface require- ment.

M0603A

Vendor:NEC

The CMOS XC3000 Class of Logic Cell Array (LCA) families provide a group of high-performance, high-den- sity, digital integrated circuits. Their regular, extendable, flexible, user-programmable array architecture is com- posed of a configuration program store plus three types of configurable elements: a perimeter of I/O Blocks (IOBs), a core array of Configurable Logic Bocks (CLBs) and re- sources for...

M0603N470J050TAX

M062066-21

M06V6-T/87CK38N-1H93

M08-0050-01

Vendor:OKIPackage Cooled:50D/C:N/A

Transmitter Input Reference Voltage. This output biases to VCC-1.3V. It is used when AC coupling the transmitter input. For AC-coupled applications, connect TXVREF-AC to the TXVT pin and bypass with a 0.01µF low ESR capacitors to VCC. See Input Stage section for more details. Maximum sink/source current is 1.5mA.

M080-4D

Vendor:NEWTECH

M081B

D/C:07+

M086B1

M088F1

Vendor:STPackage Cooled:CDIP-40D/C:N/A

Three of the preamplifiers, A, C and D are capable of delivering typically 30 µA of peak current drive while the fourth pre- amplifier B has 6 dB more current drive capability, allowing a 6 dB greater output into the same load impedance, or the same output level into one half the load impedance.

M089B1

Vendor:STPackage Cooled:DIP/16

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution, Inc.

M08T930

M0904

Vendor:MOTD/C:05+

Soldering (10 seconds)+260˚C ESD Susceptibility Human Body Model (Note 3)2 kV Machine Model (Note 3)200V See AN-450 Surface Mounting Methods and Their Effect on Product Reliability for other methods of soldering surface mount devices.

M0920

Vendor:MOTD/C:05+

In addition to transmitting configuration data to the FPGAs, the configuration circuit is also responsible for pausing configuration whenever there is insufficient data available for transmission. This occurs when the flash read bandwidth is lower than the configuration write bandwidth. Configuration is paused by stopping the DCLK to the FPGA, when waiting for data to be read from the flash or for data ...

M0930

Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications.

M093B1

Vendor:STPackage Cooled:DIP40D/C:N/A

product described in this document are for reference only. Upon actual use, therefore, please request that specifications to be separately delivered. Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits

M0CZ500

Vendor:QTCPackage Cooled:DIPD/C:08+

The M0CZ500 and M0CZ500A have separate +AVs and +DVs pins. It is recommended that both +AVs and +DVs be powered from a single source. Other external digital circuits must be powered with a separate +DVs. Layouts of +AVs and +DVs lines must be separated like the GND lines to avoid mutual interference and are connected to a point through an LC filter. There are two digital supplies +DVs1 (pin 30) and +...

M1.6L3.9

M1/6504B/883

Vendor:HARRISPackage Cooled:DIP18陶瓷D/C:91+

M1001

Vendor:MITPackage Cooled:SOP8D/C:02+

Capacitor Table Table 2-1 identifies the characteristics of capacitors from a number of vendors with acceptable ESR and ripple current (rms) ratings. The recommended number of capacitors required at both the input and output buses is identified for each capacitor type.

M1001-10860

M10020

Vendor:MOTOROLAPackage Cooled:ModuleD/C:N/A

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or it...

M10028A

Vendor:elmosPackage Cooled:elmosD/C:dc91

M10036J

Vendor:SOPD/C:03+

Dimensions InchesMillimeters MinMaxMinMax .178.1954.524.95 .170.2104.325.33 .209.2305.315.84 .100 TP2.54 TP .016.0210.410.53 .500.75012.70 19.05 .016.0190.410.48 .0501.27 .2506.35 .1002.54 .0300.76 .028.0480.711.22 .036.0460.911.17 .0100.25 45 TP45 TP

M10053A

M-100-OHM

M1010416-028

The UPC2753GR is a frequency converter manufactured with the NESAT III process. This product consists of an RF input amplifier, Gilbert cell mixer, LO input buffer, IF amplifier with AGC, external filter port, and IF output limiting amplifier. This device was specifically designed for low cost GPS recievers, mobile radios, and PCN applications.

M1011

D/C:08+/09+

The DAC101S101 is a direct replacement for the AD5310 and is one of a family of pin compatible DACs, including the 8-bit DAC081S101 and the 12-bit DAC121S101. The DAC101S101 operates over the extended industrial tem- perature range of −40˚C to +105˚C.

M1-0110-5

− One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55C to 125C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree† Output Swing Includes Both Supply Rails

M1011A

Vendor:STPackage Cooled:SOP-8P

M1011IA

Vendor:STPackage Cooled:06+D/C:500

M1012

M1013

Vendor:STPackage Cooled:08+D/C:50000

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Defense Supply Center Columbus, ATTN: DSCC-VAC, P. O. Box 3990 East Broad Street, Columbus, OH 43216-5000, by using the Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

M1014

M101A1

Vendor:STD/C:05+

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds260 (4) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extend...

M101AC

Vendor:STD/C:05+

• The information in this document is current as of July, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for avail...

M101AI

Vendor:STD/C:05+

A general-purpose data register file is contained in each pro- cessing element. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the ADSP-2136x enhanced Har- vard architecture, allow unconstrained data flow between computation units and internal memory. T...

M101C5800

Vendor:N/APackage Cooled:50D/C:N/A

A hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only refresh cycle. The external address is ignored, and the refresh address is generated internally.

M101I

Vendor:STPackage Cooled:08+D/C:800

Drain-to-Source Breakdown Voltage Gate Threshold Voltage Gate-to-Source Leakage Forward Gate-to-Source Leakage Reverse Zero Gate Voltage Drain Current Static Drain-to-Source à On-State Resistance (TO-3) Static Drain-to-Source à On-State Resistance (SMD-2) Diode Forward Voltage Ã

M101N2

M101S

M1021I

Vendor:STPackage Cooled:SOP16

M1027J

Vendor:MITPackage Cooled:DIP

In ringing mode (Ring relay in position 2), the only protection device involved is the CLP30-200B1. In normal conditions, the CLP30-200B1 operates in region 1 of A1 curve, and is idle. If an overvoltage occurring between TIP (or RING) and GND reaches the internal overvoltage reference (+/- 200V), the CLP30-200B1 acts and the line is short-circuited to GND. At this time the operating point moves to ...

M102A1

D/C:08+/09+

The phase detector and the M divider force the VCO output fre- quency to be 2M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle.

M102AM

M102I/AI

M1031

Vendor:STD/C:05+

Description Chip Select: This active low input activates the device. When high, the device enters low-power standby mode, ignores other inputs, and all outputs are tri-stated. When low, the device internally activates the SCK signal. A falling edge on /CS must occur prior to every op-code. Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge and outpu...

M-1034

Package Cooled:SQFP48D/C:2007+

The MAX1698 evaluation kit (EV kit) is a fully assembled and tested circuit board that contains a boost switch- ing-regulator current source and array of white LEDs. As configured, the circuit is set up to drive 3 banks of 3 series LED arrays at 20mA each; however, a wide vari- ety of other configurations are possible. The IC can be powered from a separate +2.7VDC to +5.5VDC input, while LED power has a wide...

M1035

Vendor:/\\Package Cooled:SOP-8

NCB1206B190TR NCB1206B260TR NCB1206B320TR NCB1206B500TR NCB1206B600TR NCB1206B700TR NCB1206B900TR NCB1206B121TR NCB1206B151TR NCB1206B201TR NCB1206B401TR NCB1206B501TR NCB1206B601TR NCB1206B122TR NCB1206B202TR NCB1206E600TR NCB1206E700TR NCB1210C320TR NCB1210C600TR NCB1210C800TR NCB1210C900TR NCB1210C202TR NCB1806E600TR NCB1806E800TR NCB1806E101TR NCB1806E151TR NCB1812D700TR NCB1812D800TR...

M1035

Vendor:/\\Package Cooled:SOP-8

NCB1206B190TR NCB1206B260TR NCB1206B320TR NCB1206B500TR NCB1206B600TR NCB1206B700TR NCB1206B900TR NCB1206B121TR NCB1206B151TR NCB1206B201TR NCB1206B401TR NCB1206B501TR NCB1206B601TR NCB1206B122TR NCB1206B202TR NCB1206E600TR NCB1206E700TR NCB1210C320TR NCB1210C600TR NCB1210C800TR NCB1210C900TR NCB1210C202TR NCB1806E600TR NCB1806E800TR NCB1806E101TR NCB1806E151TR NCB1812D700TR NCB1812D800TR...

M103AC

Vendor:STD/C:4500

Note 1: Specifications are production tested at TA = +25C. Limits over temperature are guaranteed by design and characterization. Note 2: Tuning gain is measured at VTUNE = 0.4V with a 0.2V step to 0.6V. At low VTUNE, tuning gain is highest. Note 3: Measurements taken on MAX262_ EV kit.

M103IW

Vendor:STD/C:5000

8-bit Resolution 1 Gsps (Min.) Sampling Rate ADC Gain Adjust 2 GHz Full Power Input Bandwidth Fs = 1 Gsps, Fin = 20 MHz: C SINAD = 45 dB (7.4 Effective Bits) SFDR = 58 dBc Fs = 1 Gsps, Fin = 500 MHz: C SINAD = 44 dB (7.2 Effective Bits) SFDR = 56 dBc Fs = 1 Gsps, Fin = 1000 MHz (-3 dB Fs): C SINAD = 42 dB (7.0 Effective Bits) SFDR = 52 dBc 2 Tone IMD: -53 dBc (489 MHz and 490 MHz) at 1 Gsps DNL = 0...

M103IW

Vendor:STD/C:5000

8-bit Resolution 1 Gsps (Min.) Sampling Rate ADC Gain Adjust 2 GHz Full Power Input Bandwidth Fs = 1 Gsps, Fin = 20 MHz: C SINAD = 45 dB (7.4 Effective Bits) SFDR = 58 dBc Fs = 1 Gsps, Fin = 500 MHz: C SINAD = 44 dB (7.2 Effective Bits) SFDR = 56 dBc Fs = 1 Gsps, Fin = 1000 MHz (-3 dB Fs): C SINAD = 42 dB (7.0 Effective Bits) SFDR = 52 dBc 2 Tone IMD: -53 dBc (489 MHz and 490 MHz) at 1 Gsps DNL = 0...

M1041S

Vendor:SKPackage Cooled:TO-220

M1044

Vendor:MITSUBISHIPackage Cooled:SIPD/C:05+

M1-044-2

Vendor:499Package Cooled:HARRIS

M1050-00134

M1-0512-5B

4.4.2 Group B inspection. Group B inspection shall be conducted in accordance with the conditions specified for subgroup testing in appendix E, table VIa (JANS) and table VIb (JAN, JANTX and JANTXV) of MIL-PRF-19500, and herein. Electrical measurements (end-points) and delta requirements shall be in accordance with table III herein.

M1051C

Vendor:STPackage Cooled:SOP-8D/C:1

In the test mode, the normal operation of the SCOPE™ universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990.

M1051C

Vendor:STPackage Cooled:SOP-8D/C:1

In the test mode, the normal operation of the SCOPE™ universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990.

M1053

Vendor:MITSUBISHIPackage Cooled:SIPD/C:05+

Dual MOSFET Drives for Synchronous Rectified Bridge Adaptive Shoot-Through Protection 0.5Ω On-Resistance and 4A Sink Current Capability Supports High Switching Frequency up to 2MHz - Fast Output Rise and Fall Time - Low Propagation Delay

M105B1

Vendor:STPackage Cooled:DIPD/C:92

M105B1

Vendor:STPackage Cooled:DIPD/C:92

M105X7R104M50AT

M1075

NOTES: (1) Refer to Logic Input Compatibility section. (2) Adjustable to zero with external trim potentiometer. (3) FSR means full scale range and is 20V for 10V range, 10V for 5V range for VOUT models; 2mA for IOUT models. (4) To maintain drift spec, internal feedback resistors must be used. (5) Includes the effects of gain, offset and linearity drift. Gain and offset errors externally adjusted to zero at +...

M107RE05

Vendor:INTELPackage Cooled:BGA

Note: 1. H=VIH, L=VIL, X=don't care 2. UB, LB(Upper, Lower Byte enable) These active LOW inputs allow individual bytes to be written or read. When LB is LOW, data is written or read to the lower byte, I/O 1 -I/O 8. When UB is LOW, data is written or read to the upper byte, I/O 9 -I/O 16.

M107RE05

Vendor:INTELPackage Cooled:BGA

Note: 1. H=VIH, L=VIL, X=don't care 2. UB, LB(Upper, Lower Byte enable) These active LOW inputs allow individual bytes to be written or read. When LB is LOW, data is written or read to the lower byte, I/O 1 -I/O 8. When UB is LOW, data is written or read to the upper byte, I/O 9 -I/O 16.

M-108

Vendor:NEWTECH

M1081

Vendor:STPackage Cooled:SOP-14D/C:00+

Input voltages exceeding the input overvoltage shutdown specification listed in the Performance/Functional Specifications will cause the device to shut- down. A built-in hysteresis (2V typical for "D24" models, 4V typical for "D48" models) will not allow the converter to restart until the input voltage is sufficiently reduced.

M1081

Vendor:STPackage Cooled:SOP-14D/C:00+

Input voltages exceeding the input overvoltage shutdown specification listed in the Performance/Functional Specifications will cause the device to shut- down. A built-in hysteresis (2V typical for "D24" models, 4V typical for "D48" models) will not allow the converter to restart until the input voltage is sufficiently reduced.

M109A

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

M10A22LA

M10B11654A-35J

Vendor:EITEMTPackage Cooled:SMDD/C:99+

M10H116FN

M10H186

Hynix HYMD264646B(L)8-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

M10MUD10

M10S0110-125

Vendor:OKIPackage Cooled:QFP-80PD/C:07+

Maximum / minimum signal levels The following table gives the transmitted and re- ceived signal levels for both ATU-R and ATU-C sides. All the levels are referred to the line volt- ages (i.e. after hybrid and transformers in TX di- rection, before hybrid and transformer in RX di- rection). Note that signal amplitudes shown below are for illustration purpose and depending on the trans-

M10S0210-044TS

Vendor:OKIPackage Cooled:QFPD/C:95+

The evaluation board is useful for your design and to have more understanding of the usage and performance of this device. This circuit is the same as TEST CIRCUIT. Note that this board is not prepared to show the recommendation of pattern and parts layout.

M10S0210-072

C Support of ReachDSLTM with digital com- panion chip Cat II functionality: Trellis coding and echo cancellation Dual latency support: fast + interleaved Small footprint packages allow high density board designs Embedded controller with cache for powerful and flexible on chip control of the modem operation

M10S0210-072

C Support of ReachDSLTM with digital com- panion chip Cat II functionality: Trellis coding and echo cancellation Dual latency support: fast + interleaved Small footprint packages allow high density board designs Embedded controller with cache for powerful and flexible on chip control of the modem operation

M10S0210-079

Vendor:OKIPackage Cooled:QFP-80D/C:07+

When the deserializer detects edge transitions at the LVDS input, it attempts to lock to the embedded clock information. The deserializer LOCK output remains high while its PLL locks to the incoming data or SYNC patterns present on the serial input. When the deserializer locks to the LVDS data, the LOCK output goes low. When LOCK is low, the deserializer outputs represent incoming LVDS data. One approach ...

M10S0300-035

Vendor:OKIPackage Cooled:QFP-80D/C:07+

This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.

M10S0300-048

The 2-in-1 Fob has a DS2490 chip in its handle to convert 1-Wire signaling to USB communication. In this way an iButton, 1-Wire chip, or 1-Wire instrument can have a 2-way communication link with its USB host. Any iButton from the lowest cost to the most sophisticated can be mounted in the angled end of the fob. A Java-powered iButton in combination with the 2-in-1 Fob provides the equivalent of a Java ...

M10S0570-084

Vendor:MOTOROLAD/C:17

The PI6C2308A provides 8 copies of a clock signal that has 150ps phase error compared to a reference clock. The skew between the output clock signals for PI6C2308A is less than 200ps. When there are no rising edges on the REF input, the PI6C2308A enters a power down state. In this mode, the PLL is off and all outputs are Hi-Z. This results in less than 12µA of current draw. The Select Input Decoding tab...

M10S1500-028

Vendor:OKIPackage Cooled:QFP

The RC4700 incorporates all system control co-processor (CP0) registers, on-chip. These registers (shown in Figure 1 on page 2) provide the path through which the virtual memory systems page mapping is examined and changed, exceptions are handled and oper- ating modes are controlled (kernel vs. user mode, interrupts enabled or disabled, cache features). In addition, to aid in cache diagnostic testing a...

M10T0106-025

Vendor:OKIPackage Cooled:QFP

Figure 1 shows a typical battery pack application of the bq2050H using the LED display capability as a charge- state indicator. The bq2050H is configured to display capacity in relative display mode. The relative display mode uses the last measured discharge capacity of the battery as the battery full reference. A push-button display feature is available for momentarily enabling the LED display.

M10T0416-028

Vendor:OKIPackage Cooled:QFP100D/C:04+

The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to V S0. The VS offset rating is tested with all supplies biased at 15V differential. Typical ratings at other bias conditions are shown in Figure 54.

M10V976F-50TK

Vendor:OKIPackage Cooled:N/AD/C:1240

The internal circuit is composed of 3 stages in- cluding buffer output, which enables high noise immunity and stable output. All inputs and outputs are equipped with protec- tion circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

M1-10100

Vendor:YCLPackage Cooled:95+

M1101BE

Vendor:MOTPackage Cooled:TO-220D/C:95

The ISP1161A is a single-chip Universal Serial Bus (USB) Host Controller (HC) and Device Controller (DC). The Host Controller portion of the ISP1161A complies with Universal Serial Bus Specification Rev. 2.0, supporting data rates at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The Device Controller portion of the ISP1161A also complies with Universal Serial Bus Specification Rev. 2.0, su...

M1102

Vendor:MOTPackage Cooled:NULLD/C:8607+

Input and output signals to and from the internal clock generation circuit. Connect a ceramic resonator or quartz crystal between Xin and Xout pins to set the oscillation frequency. If an external clock is used, connect the clock source to the Xin pin and leave the Xout pin open.

M1103

Vendor:5600

M1106

Vendor:MOTOROLAPackage Cooled:(LX)high-frequency

The system control co-processor in the MIPS architecture is respon- sible for the virtual memory sub-system, the exception control system and the diagnostics capability of the processor. In the MIPS architec- ture, the system control co-processor (and thus the kernel software) is implementation dependent.