N74F543PC N74F543PC N74F543PC

N74F543SPC N74F543SPC N74F543SPC

N74F544 N74F544 N74F544

N74F544D-T N74F544D-T N74F544DT

N74F545 N74F545 N74F545

N74F545N602

Command Line Editing - A backspace can be used to edit a command line before execution. The backspace key, (Control and H simultaneously on some systems), erases the previous character in the command line. Register S5 allows the user to select a character other than a backspace as the command line editor.

N74F545N-602 N74F545N-602 N74F545N602

N74F547 D/C 92 N74F547 D/C 92 N74F547DC92

N74F552D-T N74F552D-T N74F552DT

N74F552N N74F552N N74F552N

N74F564D9 N74F564D9 N74F564D9

N74F569D N74F569D N74F569D

N74F569D-A

Vendor:大SPackage Cooled:SOPD/C:07+

Power Thyristor/Diode Module PK25FG series are designed for various rectifier circuits and power controls. For your circuit application, following internal connections and wide voltage ratings up to 1600V are available. and electrically isolated mounting base make your mechanical design easy.

N74F569D-A

Vendor:大SPackage Cooled:SOPD/C:07+

Power Thyristor/Diode Module PK25FG series are designed for various rectifier circuits and power controls. For your circuit application, following internal connections and wide voltage ratings up to 1600V are available. and electrically isolated mounting base make your mechanical design easy.

N74F569N602 N74F569N602 N74F569N602

N74F573

Package Cooled:92D/C:4040

2-bit bidirectional input/output lines with pull-high resis- Wake-up tors. Each bit can be determined as NMOS output or or None schmitt trigger input by software instructions. Each bit can also be configured as wake-up input by mask option.

N74F573

Package Cooled:92D/C:4040

2-bit bidirectional input/output lines with pull-high resis- Wake-up tors. Each bit can be determined as NMOS output or or None schmitt trigger input by software instructions. Each bit can also be configured as wake-up input by mask option.

N74F573 N74F573 N74F573

N74F573D/T3 N74F573D/T3 N74F573DT3

N74F573D0 N74F573D0 N74F573D0

N74F573D602 N74F573D602 N74F573D602

N74F573D623 N74F573D623 N74F573D623

N74F573DPHI N74F573DPHI N74F573DPHI

N74F573DT N74F573DT N74F573DT

N74F573DTR N74F573DTR N74F573DTR

N74F573N

Vendor:SD/C:92

The ATF1502ASV is a high-performance, high-density complex programmable logic device (CPLD) that utilizes Atmels proven electrically-erasable technology. With 32 logic macrocells and up to 36 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1502ASVs enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modificatio...

N74F573N.602 N74F573N.602 N74F573N602

N74F573N602 N74F573N602 N74F573N602

N74F573N90 N74F573N90 N74F573N90

N74F573NT N74F573NT N74F573NT

N74F574 N74F574 N74F574

N74F574D/T3 N74F574D/T3 N74F574DT3

N74F574D602 N74F574D602 N74F574D602

N74F574DPHI N74F574DPHI N74F574DPHI

N74F574DT N74F574DT N74F574DT

N74F574DT/R N74F574DT/R N74F574DTR

N74F574DTR N74F574DTR N74F574DTR

N74F574N N74F574N N74F574N

N74F574NT N74F574NT N74F574NT

N74F579

Vendor:SPackage Cooled:SMD

The 74AUP1G79 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

N74F579

Vendor:SPackage Cooled:SMD

The 74AUP1G79 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

N74F579D

For a zero-scale digital output code, the negative input (VIN-) must be 250mV above the positive input (VIN+). The high-performance differential T/H amplifier enables the MAX104 to be used in single-ended input configurations without any degradation in dynamic performance. For a typical single-ended configuration, the analog input signal is coupled to the T/H amplifier stage at the in-phase input pad (VIN...

N74F579D (T/R) N74F579D (T/R) N74F579DTR

N74F579D /T3 N74F579D /T3 N74F579DT3

N74F579D602 N74F579D602 N74F579D602

N74F579D-C

Vendor:SPackage Cooled:SMD

Figure 3 plots power from the power supply, load power, and amplifier power dissipation as a function of output voltage delivered to a resistive load. The power delivered to the load increases with the square of the output voltage (P = I2R), while the power from the power supply increases linearly. The amplifier dissipation (equal to the difference of the first two curves) follows a parabola. If the amp...

N74F579D-C N74F579D-C N74F579DC

N74F579DJ

Vendor:大SPackage Cooled:SOPD/C:07+

Relative Accuracy: 1 LSB Max Differential Nonlinearity: 1 LSB Max 2-mA Full-Scale Current 20%, with VREF = 10 V 0.5 µs Settling Time Midscale or Zero-Scale Reset Four Separate 4Q Multiplying Reference Inputs Reference Bandwidth: 10 MHz Reference Dynamics: -105 dB THD SPI™-Compatible 3-Wire Interface: 50 MHz Double Buffered Registers Enable Simultaneous Multichannel Change Internal Power On...

N74F579DJ

Vendor:大SPackage Cooled:SOPD/C:07+

Relative Accuracy: 1 LSB Max Differential Nonlinearity: 1 LSB Max 2-mA Full-Scale Current 20%, with VREF = 10 V 0.5 µs Settling Time Midscale or Zero-Scale Reset Four Separate 4Q Multiplying Reference Inputs Reference Bandwidth: 10 MHz Reference Dynamics: -105 dB THD SPI™-Compatible 3-Wire Interface: 50 MHz Double Buffered Registers Enable Simultaneous Multichannel Change Internal Power On...

N74F579D-T N74F579D-T N74F579DT

N74F579N602 N74F579N602 N74F579N602

N74F582 N74F582 N74F582

N74F583D N74F583D N74F583D

N74F595 N74F595 N74F595

N74F595D.602-PHI N74F595D.602-PHI N74F595D602PHI

N74F595D-118 N74F595D-118 N74F595D118

N74F595D-PHI N74F595D-PHI N74F595DPHI

N74F598 D/C 92 N74F598 D/C 92 N74F598DC92

N74F604D N74F604D N74F604D

N74F604D-SMD N74F604D-SMD N74F604DSMD

N74F604D-T N74F604D-T N74F604DT

N74F620N N74F620N N74F620N

N74F621D

Ladder Network Accuracy: 1/2 LSB from 0C to + 70C. Ladder Network Resistance Tolerance: 2%. Temperature Coefficient of Resistance: 100PPM/C. Operating Temperature Range: 0C to + 70C. Power Dissipation Rating at + 70C Ambient: 50mW for individual resistor and 1.8 watts total package rating. Standard Resistance Values (R): 25 kilohms, 50 kilohms, 100 kilohms.

N74F621D N74F621D N74F621D

N74F621DT N74F621DT N74F621DT

N74F640D T/R N74F640D T/R N74F640DTR

N74F640D623

C Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel C Double PWM Generation, Capture/Waveform Mode, Up/Down Capability One Four-channel 16-bit PWM Controller (PWMC) One Two-wire Interface (TWI) C Master Mode Support Only, All Two-wire Atmel EEPROMs Supported One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os IEEE 1149.1 JTAG Boundary Scan on ...

N74F640N N74F640N N74F640N

N74F640N602 N74F640N602 N74F640N602

N74F640N-PHI-DN N74F640N-PHI-DN N74F640NPHIDN

N74F641D N74F641D N74F641D

N74F641DT N74F641DT N74F641DT

N74F641N-PHI N74F641N-PHI N74F641NPHI

N74F646(A)D N74F646(A)D N74F646AD

N74F646A N74F646A N74F646A

N74F646AD N74F646AD N74F646AD

N74F646AD/T3 N74F646AD/T3 N74F646ADT3

N74F646ADT N74F646ADT N74F646ADT

N74F646AD-T N74F646AD-T N74F646ADT

N74F646ADT/R N74F646ADT/R N74F646ADTR

N74F646ADWT N74F646ADWT N74F646ADWT

N74F646ADW-T N74F646ADW-T N74F646ADWT

N74F646AN N74F646AN N74F646AN

N74F646AN602 N74F646AN602 N74F646AN602

N74F646D

Vendor:PHIPackage Cooled:SOPD/C:90P1

2.0% output accuracy (25˚C) Low dropout voltage: 250 mV @ 500mA (typ, 5V out) Wide input voltage range (2.7V to 10V) Precision (trimmed) bandgap reference Guaranteed specs for -40˚C to +125˚C 1µA off-state quiescent current Thermal overload protection Foldback current limiting T0-252, SOT-223 and 6-Lead LLP packages Enable pin (LP38693)

N74F646D N74F646D N74F646D

N74F646SCX N74F646SCX N74F646SCX

N74F647D N74F647D N74F647D

N74F648A N74F648A N74F648A

N74F648AN-PHI N74F648AN-PHI N74F648ANPHI

N74F649N N74F649N N74F649N

N74F64D754 N74F64D754 N74F64D754

N74F64NA N74F64NA N74F64NA

N74F64N-D N74F64N-D N74F64ND

N74F64N-SIG-DN N74F64N-SIG-DN N74F64NSIGDN

N74F64ON6O2 N74F64ON6O2 N74F64ON6O2

N74F651AD

The CD54AC373/3A and CD54ACT373/3A are octal trans- parent three-state latches that utilize the Harris Advanced CMOS Logic technology. The outputs are transparent to the inputs when the Latch Enable (LE) is HIGH. When the Latch Enable (LE) goes LOW, the data is latched. The Output Enable (OE) controls the three-state outputs. When the Out- put Enable (OE) is HIGH, the outputs are in the high-imped- an...

N74F651AD N74F651AD N74F651AD

N74F651F N74F651F N74F651F

N74F652A N74F652A N74F652A