NLD322522T-150J

The LPV511 is a micropower operational amplifier that op- erates from a voltage supply range as wide as 2.7V to 12V with guaranteed specifications at 3V, 5V and 12V. The LPV511 exhibits an excellent speed to power ratio, drawing only 880 nA of supply current with a bandwidth of 27 kHz. These specifications make the LPV511 an ideal choice for battery powered systems that require long life through low s...

NLD322522T-1R0J

Vendor:TDKPackage Cooled:3225-1R0JD/C:08+

An analog to digital (A/D) conversion can be accomplished with eight (8) different threshold levels in a successive approximation algorithm; or the OUT pin can be set to trip at some alarm level. The voltage on the sample capacitor will maintain long enough for a single 8-bit conversion, but may need to be refreshed with a new measured reading if the read interval is longer than the specified hold time, tSH.

NLD322522T-1R0J

Vendor:TDKPackage Cooled:3225-1R0JD/C:08+

An analog to digital (A/D) conversion can be accomplished with eight (8) different threshold levels in a successive approximation algorithm; or the OUT pin can be set to trip at some alarm level. The voltage on the sample capacitor will maintain long enough for a single 8-bit conversion, but may need to be refreshed with a new measured reading if the read interval is longer than the specified hold time, tSH.

NLD322522T-221J

D/C:07+

5.4 Undervoltege Detection 1) When Vcc supply voltage becomes below Vuvb(11.4V typ.), all of the IGBTs shut off and F terminal output becomes L. 2) When between BU-MU, BV-MV or BW-MW voltage become below Vuvt(11.4V typ.), top arm IGBT of under voltage detected phase shuts off. In this time, F terminal output doesnt change. Note 1. When VCC supply voltage becomes lower, driving capability of IGBT also...

NLD322522T-3R3K

D/C:07+

The Am29DL320G is a 32 megabit, 3.0 volt-only flash memory device, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ15CDQ0; byte mode data appears on DQ7CDQ0. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers.

NLD322522T-471J

Vendor:TDKPackage Cooled:3225-471JD/C:08+

NLD322522T-4R7J

Vendor:TDKPackage Cooled:3225-4R7JD/C:04+

For AGC with a maximum gain of 24 dB, AGCFIL should be set to 3 V and AGCMAX should be open (see Figure 1). For AGC with a maximum gain of 11 dB, AGCMAX should be set to 0 V. A low-pass filter should be placed between AGCOUT and AMPIN. A 0.1-µF capacitor should be placed from AGCFB to GND. A line-clamp pulse should be applied to HOBP.

NLD322522T-6R8J

Vendor:TDKPackage Cooled:3225-6R8JD/C:08+

Highly integrated analog interface XGA/SXGA TFT LCD Display Controller Handle both 24-bit and 48-bit sampled RGB input up to SXGA (1280x1024) @ 85Hz Support various PC graphics cards Drive 48-bit digital RGB output up to SXGA (1280x1024) @ 75Hz Support various TFT LCD panels Truly Plug and Display no special driver running on PC Implement proprietary SmartDisplay technology for - input mode detection ...

NLD32522T-150J

Vendor:TDKPackage Cooled:3225-150JD/C:08+

Thermal Resistance . . . . . . . . . . . . . . . .jajc Ceramic DIP and FRIT Package . . . . . 80oC/W20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipatio...

NLD32522T-150J

Vendor:TDKPackage Cooled:3225-150JD/C:08+

Thermal Resistance . . . . . . . . . . . . . . . .jajc Ceramic DIP and FRIT Package . . . . . 80oC/W20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipatio...

NLD44H11

NLD44H8

NLD6603A

NLD6623A

NLF150B

NLF150P

NLF151C

NLF151E

NLF201614T-220J

Vendor:TDKPackage Cooled:0805-22UHD/C:2K/R

Collector-emitter Breakdown (BVCEO) SFH600-0, 1, 2, 3, 4 SFH601-1, 2, 3, 4, 5 SFH609-1, 2, 3, 4, 5 Collector-base Breakdown (BVCBO) SFH600-0, 1, 2, 3, 4 SFH601-1, 2, 3, 4, 5 SFH609-1, 2, 3, 4, 5 Emitter-collector Breakdown (BVECO) Collector-emitter Dark Current (ICEO)

NLF322522T-022J

Vendor:TDKPackage Cooled:3225D/C:03+

The HYM72V32656B(L)T8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 256Mbytes mem- ory. The HYM72V32656B(L)T8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and out- puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.

NLF322522T-1R2K

NLF322522T-221K

Vendor:TDKPackage Cooled:3225-221KD/C:08+

The HYM71V65801 X-Series are Dual In-line Memory Modules suitable for easy interchange and addition of 64Mbytes memory. The HYM71V65801 X-Series are offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.

NLF390PB

NLF395E

NLF397C

NLF397P

NLF397PA

NLF398B

NLF398D

NLF398E

NLF398N

NLF398PB

NLF447A

NLF447PA

NLF447PC

NLF448C

NLF448PC

NLF450P

NLF450PD

NLF451PB

NLF451PM

NLF451T

NLF453232T-100K

D/C:07+

Data Output Control The usual state of the data output is the High-Z state. Whenever CAS is inactive (HIGH), Q will float (High-Z). Thus, CAS functions as data output control. After access time, in case of a Read cycle, the output is activated, and it contains the logic „0 or „1. Q is then valid until CAS returns into to inactive state (HIGH). The memory cycle being a Read, Read-Wr...

NLF453232T121K

Dual Synchronous Controller in 24-Pin Package with 1808 out-of-phase operation LDO Controller with Independent Bias Supply Can be configured as 2-Independent or 2-Phase PWM Controller Programmable Current Sharing in 2-Phase Configu- ration Flexible, Same or Separate Supply Operation Operation from 4V to 25V Input Programmable Switching Frequency up to 400KHz Soft-Start controls all outputs Precision Refe...

NLF453232T-121K

Vendor:1812D/C:07+

NOTES: 1. The falling edge of the Vin(C) signals a charge command, while the rising edge signals a spark command. 2. During start mode, stall conditions are prevented. 3. During a stall, the coil is discharged slowly and a quick charge and spark occur on the next spark command.

NLF453232T-121K

Vendor:1812D/C:07+

NOTES: 1. The falling edge of the Vin(C) signals a charge command, while the rising edge signals a spark command. 2. During start mode, stall conditions are prevented. 3. During a stall, the coil is discharged slowly and a quick charge and spark occur on the next spark command.

NLF453232T-150K

Vendor:1812D/C:07+

Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock input. Alternatively, by means of the serial control bits, the device may be configured such that data is clocked into the shift register on the rising edge of SCLK.

NLF453232T-1R0J

Vendor:TDKD/C:4532

• PNP Silicon Epitaxial Planar Transistors • Suited for low level, low noise, low frequency applications in hybrid cicuits. • Low Current, Low Voltage. • As complementary types, BCW60 Series NPN transistors are recommended.

NLF453232T1R0M

NLF453232T-1R0M

D/C:07+

NLF453232T-1R5M

Package Cooled:4532-1R5MD/C:07+

Samsung Electronics' microcontroller business has been awarded full ISO-14001 certification (BVQ1 Certificate No. 9330). All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives.

NLF453232T-220K

Vendor:1812Package Cooled:TDKD/C:07+

NLF453232T-221K

D/C:07+

This series of Zener diodes is packaged in a SOD−523 surface mount package. They are designed to provide voltage regulation protection and are especially attractive in situations where space is at a premium. They are well suited for applications such as cellular phones, hand held portables, and high density PC boards.

NLF453232T-270K(27UH)

NLF453232T-2R2 45322R2

NLF453232T-2R2J

wide band frequency, 1000-2500 MHz excellent amplitude unbalance, 0.2 dB typ. small size, 0.166"x0.150"x0.155" temperature stable, BLUE CELL™ base solder plated leads for excellent solderability small size low cost patent pending

NLF453232T-2R7J

Vendor:TDKPackage Cooled:N/AD/C:04+

• Nonvolatile Storage Without Battery Problems • Directly Replaces 32K x 8 static RAM, Battery Backed RAM or EEPROM • 25ns, 35ns and 45ns Access Times • Store to EEPROM Initiated by Software or AutoStore™ on Power Down • Recall to SRAM by Software or Power Restore • 15mA ICC at 200ns Cycle Time • Unlimited Read, Write and Recall Cycles • 1,000,000 Sto...

NLF453232T-330K

Enhanced Power Management Application Software Transparency Programmable Powerdown Command Save and Restore Commands for 0V Powerdown Auto Powerdown and Wakeup Modes Two External Power Management Pins Consumes No Power While in Powerdown

NLF453232T-331K

D/C:07+

Must be chosen from an inspection lot that has been submitted to and passed group A, subgroup 2, conformance inspection. When the final lead finish is solder or any plating prone to oxidation at high temperature, the samples for life test (group B for JAN, JANTX, and JANTXV) may be pulled prior to the application of final lead finish.

NLF453232T-3R3M

Package Cooled:06+D/C:07+

10,000 cycles/byte, minimum 1,000 cycles/byte, minimum 100,000 cycles/byte, minimum -2.0 V dc to +7.0 V dc -65C to +150C 1.0 W +300C +150C See MIL-STD-1835 13C/W 27C/W -2.0 V dc to +7.0 V dc -2.0 V dc to +13.5 V dc -2.0 V dc to +14.0 V dc -2.0 V dc to +7.0 V dc 200 mA 10 years minimum

NLF453232T-3R3M

D/C:07+

10,000 cycles/byte, minimum 1,000 cycles/byte, minimum 100,000 cycles/byte, minimum -2.0 V dc to +7.0 V dc -65C to +150C 1.0 W +300C +150C See MIL-STD-1835 13C/W 27C/W -2.0 V dc to +7.0 V dc -2.0 V dc to +13.5 V dc -2.0 V dc to +14.0 V dc -2.0 V dc to +7.0 V dc 200 mA 10 years minimum

NLF453232T-3R9J-3

Vendor:TDKD/C:04+

The optional 16K bytes boot block section includes a repro- gramming write lockout feature to provide data integrity. The boot sector is designed to contain user-secure code, and when the feature is enabled, the boot sector is perma- nently protected from being reprogrammed.

NLF453232T-470K

Vendor:1812D/C:07+

• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock) -. Burst length (2, 4, 8) -. Burst type (sequential & interleave) • All...

NLF453232T-471K

D/C:07+

Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 1...

NLF453232T-4R7J

NLF453232T-560K

D/C:07+

VOLTAGE OUTPUT versus APPLIED DIFFERENTIAL PRESSURE The differential voltage output of the sensor is directly proportional to the differential pressure applied. The output voltage of the differential or gauge sensor increases with increasing pressure applied to the pressure side (P1) relative to the vacuum side (P2). Similarly, output voltage increases as increasing vacuum is applied to the vacuum sid...

NLF453232T-561K

Vendor:1812D/C:07+

NLF453232T680J

NLF609C

NLF609E

NLF609PB

NLF609T

NLFC201614T-100K-PFM

D/C:07+

This Schmitt-Trigger input is used to transmit serial data when SD is low. An on-chip protection circuit disables the LED driver if the Txd pin is asserted for longer than 300 µs. The input threshold voltage adapts to and follows the logic voltage swing defined by the applied Vlogic voltage.

NLFC201614T-100K-PFM

D/C:07+

This Schmitt-Trigger input is used to transmit serial data when SD is low. An on-chip protection circuit disables the LED driver if the Txd pin is asserted for longer than 300 µs. The input threshold voltage adapts to and follows the logic voltage swing defined by the applied Vlogic voltage.

NLFC201614T-1R0M-PF

D/C:07+

Current generation microprocessors and their associated circuitry cycle load current from almost zero to several amps in tens of nanoseconds. Output voltage tolerances are tighter and include transient response as part of the specification. The NLFC201614T-1R0M-PF/NLFC201614T-1R0M-PF are specifi- cally designed to meet the fast current load step require-

NLFC201614T-220K-PF

Vendor:TDKD/C:9+

NLFC201614T-2R2M

D/C:07+

Figure 1 shows the ELM331 in an example heating control circuit. A closed contact output occurs whenever the temperature measured by RTEMP falls to a value less than that determined by RSET. It is anticipated that this type of circuit could possibly be used to control temperatures over the range of -40C to +40C.

NLFC201614T-2R2M-PF

Vendor:TDKD/C:9+

NLFC201614T-4R7M-PF

Vendor:TDKPackage Cooled:0805LD/C:05+

NLFC201614T-4R7M-PF

Vendor:TDKPackage Cooled:0805LD/C:05+

NLFC252018T-100K

Vendor:TDKPackage Cooled:N/AD/C:08+

Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: Commander, Defense Supply Center Columbus, ATTN: DSCC- VAC, Post Office Box 3990, Columbus, OH 43216-5000, by using the Standardization Document Improvement Proposal (DD Form 1426) appearing at the end of this document or by letter.

NLFC252018T-100K-PF

D/C:07+

Differential clock input. The NLFC252018T-100K-PF supports both single-ended and fully differential clock input modes. In the single-ended clock input mode, the IDCK+ input (pin 57) should be connected to the single-ended clock source and the IDCK input (pin 56) should be tied to GND. In the differential clock input mode, the NLFC252018T-100K-PF uses the crossover point between the IDCK+ and IDCKC signals ...

NLFC252018T-100K-PF

D/C:07+

Differential clock input. The NLFC252018T-100K-PF supports both single-ended and fully differential clock input modes. In the single-ended clock input mode, the IDCK+ input (pin 57) should be connected to the single-ended clock source and the IDCK input (pin 56) should be tied to GND. In the differential clock input mode, the NLFC252018T-100K-PF uses the crossover point between the IDCK+ and IDCKC signals ...

NLFC252018T-101K

D/C:07+

Logic control inputs can be driven up to +5.5V regardless of the supply voltage. For example, given a 5.0V supply, the control or select pins may be driven low to 0V and high to 5.5V. Driving the control or select pins Rail-toRail® minimizes power consumption.

NLFC252018T-101K-PF

Vendor:TDKPackage Cooled:2520D/C:08+ROHS

The DS1330 256k NV SRAMs are 262,144-bit, fully static, NV SRAMs organized as 32,768 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. Addi...

NLFC252018T-150K

D/C:07+

The ZL30414 has a built-in LOCK detector that measures frequency difference between input reference clock C19i and the VCO frequency. When the VCO frequency is less than 300 ppm apart from the input reference frequency then the LOCK pin is set high. The LOCK pin is pulled low if the frequency difference exceeds 1000 ppm.

NLFC252018T-150K-PF

Vendor:TDKPackage Cooled:2520D/C:08+ROHS

C Datasheet describes Mode 0 Operation 20 MHz Clock Rate Byte Mode and 256-byte Page Mode for Program Operations Sector Architecture: C Eight Sectors with 64K Bytes Each (4M) C 256 Pages per Sector Product Identification Mode Low-voltage Operation C 2.7 (VCC = 2.7V to 3.6V) Sector Write Protection C Protect 1/8, 1/4, 1/2 or Entire Array Write Protect (WP) Pin and Write Disable Instructions for b...

NLFC252018T-1R0K

Vendor:TDKPackage Cooled:2520-1R0KD/C:08+

NLFC252018T-1R0M

D/C:07+

This family is a 16M bit dynamic RAM organized 4,194,304 x 4-bit configuration with Extended Data Out mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time(50, 60 or 70ns) and refresh cycle(2K ref. or 4K ref.) and power consu...

NLFC252018T-1R0M-PF

Vendor:TDKPackage Cooled:2520D/C:08+ROHS

The chipset employs Discrete Multi-Tone modulation as specified in ANSI T1.413. It also supports ETSI TS 101 388 and ITU standards G.992.1 (G.dmt) including Annex A, B and C; G.992.2 (G.lite) annex A, B and C; G.992.3 (ADSL2) including Annex A, B, C, I, J and L; G.992.5 (G.ADSL+) including Annex A, B, C, I, J and Annex L.

NLFC252018T-1R5M-PF

Vendor:TDKPackage Cooled:2520D/C:08+ROHS

GROUND - Is the return for the VBIAS supply. This pin should be connected to the return of the lowside MOSFETs or the bottom of the sense resistor at the bottom of the bridge. The gate drive current must return through this pin, so trace lengths should be kept to a minimum. All grounds should be returned to the bottom of the bridge or sense resistor in a star fashion. This will eliminate ground loops.

NLFC252018T-220J

Package Cooled:25201008D/C:07+

• Controls the exact light power levels coming from the laser and controls the exact power absorbed by the disc during recording. This is not trivial since the laser characteristics (both threshold and gain) are strongly temperature dependent. A first control loop controls the laser power levels based on the signal from a forward sense diode (FS control). This will make the laser virtually ...

NLFC252018T-220K

D/C:07+

ADDRESS: The four least significant address lines are bidirectional three-state signals. In the Idle cycle, they are inputs and are used by the 82C37A to address the control register to be loaded or read. In the Active cycle, they are outputs and provide the lower 4-bits of the output address.

NLFC252018T-220K-PF

Vendor:TDKPackage Cooled:2520D/C:08+ROHS

The existing procedure to add a collection identifier is through a "technical amendment" to the standard, since Annex A is a "normative" annex of the standard. Even though this procedure is more complex and cumbersome than a simple registration procedure, it can be effectively used to handle the requests for registration of sub-repertoires of 10646. A request for identifying a sub-reperto...

NLFC252018T-2R2M

Vendor:TDKPackage Cooled:N/AD/C:08+

The MAX4104/MAX4105/MAX4304/MAX4305 op amps feature ultra-high speed, low noise, and low distortion in a SOT23 package. The unity-gain-stable MAX4104 requires only 20mA of supply current while delivering 625MHz bandwidth and 400V/µs slew rate. The MAX4304, compensated for gains of +2V/V or greater, delivers a 730MHz bandwidth and a 1000V/µs slew rate. The MAX4105 is compensated for a minimum gain...

NLFC252018T-2R2M-PF

Vendor:TDKPackage Cooled:2520D/C:08+ROHS

HN58X24xxx series are two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). They realize high speed, low power consumption and a high level of reliability by employing advanced MNOS memory technology and CMOS process and low voltage circuitry technology. They also have a 64-byte page programming function to make their write operation faster.

NLFC252018T-330K

Vendor:TDKPackage Cooled:N/AD/C:08+

NLFC252018T-330K-PF

Vendor:TDKPackage Cooled:2520D/C:08+ROHS

Erase (ERASE) After the erase instruction is entered, CS must be brought LOW. The falling edge of CS initiates the self-timed internal programming cycle. Bringing CS HIGH after minimum of tcs, will cause DO to indicate the READ/BUSY status of the chip. To explain this, a logical "0" indicates the programming is still in progress while a logical "1" indicates the erase cycle is complete a...

NLFC252018T-3R3M

Vendor:TDKPackage Cooled:N/AD/C:08+

TEST CONDITION 4.75V<VIN<5.25V, 5mA[IO[1.3A: TJ=258C 08C[TJ[1508C 4.75V<VIN<5.25V, IO=10mA VIN=4.75V, 10mA[IO[1.3A IO=1.3A VIN=5.5V Note 3, 5 Note 4, 5 TJ=258C, 10Hz<BW<10KHz, Note 5 VIN=5V, Note 5, f=120Hz 4.75V<VIN<5.25V, 0mA[IO[1.3A, Note 5 VIN[7V, 2mA[IO[1.3A VIN=5V, 0mA[IO[50mA, TJ=258C VIN=5V, 10mA<IO<1.3A, tr/1ms VIN=5V, 1.3A to 10mA, tf/1ms CIN=CO=10mF, X7R ...

NLFC252018T-470K

D/C:07+

Maximum Charge Current Charge Current Load Dependency Trickle Charge Current Trickle Charge Threshold Voltage Input Charger Enable Threshold Voltage Output Charger Enable Threshold Voltage Input/Output Undervoltage Current Limit Recharge Battery Threshold Voltage TIMER Accuracy Recharge Time Low-Battery Trickle Charge Time Junction Temperature in Constant Temperature Mode