Index "N"Vendor:KYOCERAPackage Cooled:TQFP/144D/C:04+
Package Cooled:QFN6
Vendor:0
Vendor:STPackage Cooled:SOP28
Provides single chip solution for Vcore, GTL+ & clock supply 200mA On-Board LDO Regulator Designed to meet the latest Intel specification for Pentium II On-Board DAC programs the output voltage from 1.3V to 3.5V Linear regulator controller on board for 1.5V GTL+ supply Loss-less Short Circuit Protection with HICCUP Synchronous operation allows maximum efficiency patented architecture allows f...
Vendor:TOKINPackage Cooled:0603-102D/C:08+
The output stages switch at half the oscillator frequency, in a push-pull configuration. When the voltage on the RC pin is rising, one of the two outputs is high, but during fall time, both outputs are off. This dead time between the two outputs, along with a slower output rise time than fall time, insures that the two outputs can not be on at the same time. This dead time is typically 60 ns to 200 ns and...
D/C:07+
The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base−emitter resistor. These digital transistors are designed to replace a single device and its external resistor bias network. The BRT eliminates these individual components by integrating them into a single device. In the MUN5111DW1T1 series, ...
D/C:07+
The TPS51020 is a multi-function dual- synchronous step-down controller for notebook system power. The part is specifically designed for high performance, high efficiency applications where the loss associated with a current sense resistor is unacceptable. The TPS51020 utilizes feed forward voltage mode control to attain high efficiency without sacrificing line response. Efficiency at light load co...
D/C:07+
The TPS51020 is a multi-function dual- synchronous step-down controller for notebook system power. The part is specifically designed for high performance, high efficiency applications where the loss associated with a current sense resistor is unacceptable. The TPS51020 utilizes feed forward voltage mode control to attain high efficiency without sacrificing line response. Efficiency at light load co...
Vendor:TOKINPackage Cooled:SMDD/C:08+
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied at these or any other conditions in excess of conditions represented in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods may adversely affect device reliability.
D/C:07+
supplied by the device in the case of charging line capacitance. The Philips Semiconductors data sheet limits for IOS reflect the conditions that the part will see in the system full IOS spikes for extremely short periods of time. Problems could occur if slow test equipment or test methods ground an output for too long a time causing functional failure or damage.
Vendor:TOKINPackage Cooled:603D/C:04+/05+
Analog Input CMRR Leakage Current at 25C Input Impedance ACCURACY No Missing Codes Differential Linearity Error Integral Linearity Error Transition Noise Gain Error2, TMIN to TMAX Gain Error Temperature Drift Offset Error2, TMIN to TMAX Offset Temperature Drift Power Supply Sensitivity
Vendor:TOKINPackage Cooled:603D/C:04+/05+
Analog Input CMRR Leakage Current at 25C Input Impedance ACCURACY No Missing Codes Differential Linearity Error Integral Linearity Error Transition Noise Gain Error2, TMIN to TMAX Gain Error Temperature Drift Offset Error2, TMIN to TMAX Offset Temperature Drift Power Supply Sensitivity
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Package Cooled:08+D/C:07+
The 78P7200 is a single chip line interface IC designed to work with either a 51.84 Mbit/s STS-1, 44.736 Mbit/s DS3 or 34.368 Mbit/s E3 signal. The receiver recovers clock, positive data and negative data from an Alternate Mark Inversion (AMI) signal. The input signal should be B3ZS or HDB3 coded.
Vendor:TOKINPackage Cooled:603D/C:04+/05+
Configurable Logic Blocks (CLBs) provide functional elements for combinatorial and synchronous logic, including basic storage elements. BUFTs (3-state buffers) associated with each CLB element drive dedicated segmentable horizontal routing resources. Block SelectRAM memory modules provide large 18 Kbit storage elements of dual-port RAM. Multiplier blocks are 18-bit x 18-bit dedicated multipliers. D...
Vendor:TOKINPackage Cooled:603D/C:04+/05+
Configurable Logic Blocks (CLBs) provide functional elements for combinatorial and synchronous logic, including basic storage elements. BUFTs (3-state buffers) associated with each CLB element drive dedicated segmentable horizontal routing resources. Block SelectRAM memory modules provide large 18 Kbit storage elements of dual-port RAM. Multiplier blocks are 18-bit x 18-bit dedicated multipliers. D...
D/C:07+
These voltage regulators are monolithic integrated circuits designed as fixed-voltage regulators for a wide variety of applications including local, on-card regulation. These regulators employ internal current limiting, thermal shutdown, and safe-area compensation. With adequate heatsink they can deliver output currents up to 1.5 ampere. Although designed primarily as a fixed voltage regulator, these devices ...
Vendor:TOKINPackage Cooled:0603-401D/C:08+
In-system programmable MAX 7000 devicescalled MAX 7000S devicesinclude the EPM7032S, EPM7064S, EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices. MAX 7000S devices have the enhanced features of MAX 7000E devices as well as JTAG BST circuitry in devices with 128 or more macrocells, ISP, and an open-drain output option. See Table 4.
Vendor:TOKINPackage Cooled:0603-401D/C:08+
In-system programmable MAX 7000 devicescalled MAX 7000S devicesinclude the EPM7032S, EPM7064S, EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices. MAX 7000S devices have the enhanced features of MAX 7000E devices as well as JTAG BST circuitry in devices with 128 or more macrocells, ISP, and an open-drain output option. See Table 4.
D/C:07+
When removing flux with chemicals after soldering, clean only the soldered part of the leads. Do not immerse the entire package in the cleaning solvent. Chemical residue on the LED emitter or the photodetector inside the phototransistor case may adversely affect the optical characteristics of the device and may drastically reduce the collector current. The case is made of polybutylene-terephthalate. Oil or...
Vendor:NISSEIPackage Cooled:2005D/C:500
CAO/ENBL (Current Amplifier Output/Chip Enable): The current loop compensation network is connected between this pin and CAM. The voltage on this pin is the input to the PWM comparator and regulates the output voltage of the system. The GATE output is disabled (held low) unless the voltage on this pin exceeds 1V, allowing the PWM to force zero duty cycle when necessary. The PWM forces maximum duty cyc...
Vendor:STPackage Cooled:TO-2.5P
(2) The technical information described in this book is limited to showing representative characteristics and applied circuits examples of the products. It neither warrants non-infringement of intellectual property right or any other rights owned by our company or a third party, nor grants any license.
Vendor:N/APackage Cooled:DIPD/C:06+
Output pins OUTH and OUTL are connected to input pins VH and VL respectively, depending on the status of the IN pin. One of the output pins is always in tri-state, except when the OE pin is active low, in which case both outputs are in 3- state mode. The isolation of the output FETs from the power supplies enables VH and VL to be set independently, enabling level-shifting to be implemented.
Output pins OUTH and OUTL are connected to input pins VH and VL respectively, depending on the status of the IN pin. One of the output pins is always in tri-state, except when the OE pin is active low, in which case both outputs are in 3- state mode. The isolation of the output FETs from the power supplies enables VH and VL to be set independently, enabling level-shifting to be implemented.
Vendor:KOAPackage Cooled:SOP16
Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst ...
Vendor:SOLUTIONPackage Cooled:BGAD/C:04+
JAPackage thermal impedance(6)165C/W TstgStorage temperature range−65150C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) The algebraic convention,...
Vendor:SolutionsD/C:04+
1. Serial control by I2C bus. 2. 5-inputs, 2-outputs. 3. Video and audio system switches can be controlled independently. 4. 6dB amplifier built in to video system. 5. Built-in Y/C MIX circuit. 6. Slave address can be changed : 90H or 92H. 7. Audio muting possible by external pin. 8. Maintains high impedance even when I2C BUS line (SDA, SCL) power supply is off. 9. Built-in 3 value discrimination function. ...
Package Cooled:NEW
• 0.13µ CMOS design allows industrys lowest power • Advanced power management • Enables notebook and desktop PC products for all segments • Footprint-compatible with 4401, a 10/100 companion chip • Allows one board layout for both Gigabit and Fast Ethernet applications • Power optimized through reduced CPU utilization • Adaptive interrupts minimizes...
Vendor:N/APackage Cooled:SMDD/C:03+
Vendor:OKID/C:95
The record path of the TLV320AIC32 contains integrated microphone bias, digitally-controlled stereo-microphone pre-amp, and automatic gain control (AGC), with mix/mux capability among the multiple analog inputs. The playback path includes mix/mux capability from the stereo DAC and selected inputs, through programmable volume controls, to the various outputs.
Vendor:NECPackage Cooled:TO-92SD/C:00+
Soft phase switching + direct PWM drive PWM control based on both a DC voltage input (the CTL voltage) and a pulse input Provides a 5 V regulator output One Hall-effect sensor FG output Integrating amplifier Automatic recovery constraint protection circuit (on/off = 1/14), RD output Current limiter circuit LVSD circuit Thermal protection circuitt
Vendor:NECPackage Cooled:TO-92SD/C:06+
Note: 10. All the internal timing is referenced to the CPU clock 11. PCI_STP# signal is an input signal that must be made synchronous to PCI_F output. 12. All other clocks continue to run undisturbed. 13. PD# is understood to in a high state. 14. Diagrams shown with respect to 133 MHz. Similar operation when CPU is 100 MHz
Vendor:NECPackage Cooled:TO92D/C:06+
Note: 10. All the internal timing is referenced to the CPU clock 11. PCI_STP# signal is an input signal that must be made synchronous to PCI_F output. 12. All other clocks continue to run undisturbed. 13. PD# is understood to in a high state. 14. Diagrams shown with respect to 133 MHz. Similar operation when CPU is 100 MHz
Vendor:NECPackage Cooled:TO-92SD/C:00+
Often a system will need to know if a watchdog timer reset has occurred. The WTR bit (PCON.4) will be set whenever this occurs, and software can test for this early in the reset sequence if a system fault has occurred. If so, the system may decide to go into a "safe" mode and alert the user to an error condition.
Vendor:NECPackage Cooled:TO-92SD/C:00+
Often a system will need to know if a watchdog timer reset has occurred. The WTR bit (PCON.4) will be set whenever this occurs, and software can test for this early in the reset sequence if a system fault has occurred. If so, the system may decide to go into a "safe" mode and alert the user to an error condition.
Vendor:NECPackage Cooled:TO-92SD/C:00+
Industry Standard MICROWIRE Bus Single Supply Voltage: C 4.5 to 5.5V for M93Cx6 C 2.5 to 5.5V for M93Cx6-W C 1.8 to 5.5V for M93Cx6-R Dual Organization: by Word (x16) or Byte (x8) Programming Instructions that work on: Byte, Word or Entire Memory Self-timed Programming Cycle with Auto- Erase Ready/Busy Signal During Programming Speed: C 1MHz Clock Rate, 10ms Write Time (Current product, ide...
Vendor:ONPackage Cooled:SOT-223D/C:08+
• Low Dropout Voltage: 100mV @ 650mA with FZT749 PNP Transistor • 2.7V to 8V Supply Range • Low Operating Current: 50µA Operating, 0.2µA Shutdown • Low True Chip Enable • Output Accuracy < 2% • Small Package: 5-Pin SOT-23A
Package Cooled:TO92D/C:07+/08+
NOTES: 1. Measured from maximum diameter of the product. 2. Leads having maximum diameter .019 inch (.483 mm) measured in gaging plan .054 inch (1.37 mm) + .001 inch (.025 mm) - .000 inch (.000 mm) below the seating plane of the product shall be within .007 inch (.178 mm) of their true position relative to a maximum width tab. 3. The product may be measured by direct methods or by gauge. 4. Tab ce...
Package Cooled:TO92D/C:07+/08+
NOTES: 1. Measured from maximum diameter of the product. 2. Leads having maximum diameter .019 inch (.483 mm) measured in gaging plan .054 inch (1.37 mm) + .001 inch (.025 mm) - .000 inch (.000 mm) below the seating plane of the product shall be within .007 inch (.178 mm) of their true position relative to a maximum width tab. 3. The product may be measured by direct methods or by gauge. 4. Tab ce...
Vendor:NECPackage Cooled:NECD/C:00+
Picture Structure Improvement including Color Transition Improvement, Luma Peaking/Coring and Luma Contrast Enhancer H/V format conversion with Zoom In/Out (4x to 1/8x) with H/V decimation Letterbox and 4:3 to 16:9 format conversion with programmable 5-segment Panoramic mode Very flexible Sync Generator for Master and Slave modes by Vsync and Hsync signals generation Progressive Display mode (60 Hz...
Vendor:NECPackage Cooled:NECD/C:00+
Picture Structure Improvement including Color Transition Improvement, Luma Peaking/Coring and Luma Contrast Enhancer H/V format conversion with Zoom In/Out (4x to 1/8x) with H/V decimation Letterbox and 4:3 to 16:9 format conversion with programmable 5-segment Panoramic mode Very flexible Sync Generator for Master and Slave modes by Vsync and Hsync signals generation Progressive Display mode (60 Hz...
The EP7311 uses its powerful 32-bit RISC processing engine to implement audio decompression algorithms in software. The nature of the on-board RISC processor, and the availability of efficient C-compilers and other software development tools, ensures that a wide range of audio decompression algorithms can easily be ported to and run on the EP7311
Vendor:STPackage Cooled:SOT-223D/C:0
Filtering The Freescale Semiconductor accelerometers contain an onboard 2--pole switched capacitor filter. A Bessel imple- mentation is used because it provides a maximally flat delay response (linear phase) thus preserving pulse shape integri- ty. Because the filter is realized using switched capacitor techniques, there is no requirement for external passive components (resistors and capacitors) to ...
Vendor:STPackage Cooled:TO223-4D/C:07+
1.1 Scope. This specification covers the performance requirements for NPN, Darlington, silicon, power transistors. Two levels of product assurance are provided for each device type as specified in MIL-PRF-19500. For JAN quality assurance level (see 6.3).
Package Cooled:0805-102D/C:38691
(b) Measured at t<5 secs for a dual device surface mounted on 8 sq cm single sided 2oz copper on FR4 PCB, in still air conditions with all exposed pads attached. The copper area is split down the centre line into two separate areas with one half connected to each half of the dual device.
D/C:38691
(b) Measured at t<5 secs for a dual device surface mounted on 8 sq cm single sided 2oz copper on FR4 PCB, in still air conditions with all exposed pads attached. The copper area is split down the centre line into two separate areas with one half connected to each half of the dual device.
Package Cooled:0805-202D/C:08+
The extremely high maximum data rate is achieved by three internal shift registers, each of 16-bit length and 12-bit width, which perform a serial to parallel conversion between the asynchronous input/output data streams and the memory array. The parallel data transfer from the 16 12-bit input shift register C to an addressed location of the memory array and from the memory array to one of the 16 12-bi...
Vendor:TOKINPackage Cooled:N/AD/C:08+
The MAX7447 is designed to process S-Video and CVBS video signals. The video signal processed by channel A (CVBS video signal) must include a sync pulse. This sync pulse provides the required timing for channels A, B, and C. Channel D allows an asynchro- nous CVBS video signal to be processed with its own local sync separator. This device operates from a single +5V supply and has a nominal cutoff frequency ...
Vendor:TOKINPackage Cooled:N/AD/C:08+
s Fully complies with Universal Serial Bus Specification Rev. 2.0 s Supports CEA−936−A, Mini-USB Analog Carkit Interface s Can transmit and receive serial data at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) data rates s Supports Serial Parallel Interface (SPI) (up to 26 MHz) and I2C-bus (up to 400 kHz) serial interface to access control and status registers s Supports Universal ...
Vendor:TOKINPackage Cooled:N/AD/C:08+
s Fully complies with Universal Serial Bus Specification Rev. 2.0 s Supports CEA−936−A, Mini-USB Analog Carkit Interface s Can transmit and receive serial data at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) data rates s Supports Serial Parallel Interface (SPI) (up to 26 MHz) and I2C-bus (up to 400 kHz) serial interface to access control and status registers s Supports Universal ...
Vendor:TOKIND/C:34840
The DSP includes a flexible, software-programmable phase-locked loop (PLL) clock generator. Three different clock domains (SYSCLK1, SYSCLK2, and SYSCLK3) are generated by dividing down the PLL output. SYSCLK1 is the clock used by the CPU, memory controller, and memories. SYSCLK2 is used by the peripheral subsystem and dMAX. SYSCLK3 is used exclusively for the EMIF.
Vendor:TOKINPackage Cooled:0805-202D/C:08+
Designers using the THS4271 are rewarded with higher dynamic range over a wider frequency band without the stability concerns of decompensated amplifiers. The devices are available in SOIC, MSOP with PowerPAD, and leadless MSOP with PowerPAD packages.
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D/C:2800
The N2012ZA400T06 and N2012ZA400T06 dual power-distribution switches are intended for applications where heavy capacitive loads and short circuits are likely. These devices incorporate in single packages two 135-mΩ N-channel MOSFET high-side power switches for power-distribution systems that require multiple power switches. Each switch is controlled by a logic enable compatible with 5-V and 3-V logi...
D/C:2800
The N2012ZA400T06 and N2012ZA400T06 dual power-distribution switches are intended for applications where heavy capacitive loads and short circuits are likely. These devices incorporate in single packages two 135-mΩ N-channel MOSFET high-side power switches for power-distribution systems that require multiple power switches. Each switch is controlled by a logic enable compatible with 5-V and 3-V logi...
Vendor:TOKINPackage Cooled:N/AD/C:08+
Available in the Texas Instruments NanoStar™ and NanoFree™ Packages Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub-1-V Operable Max tpd of 2.5 ns at 1.8 V Low Power Consumption, 10-µA Max ICC 8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protec...
Vendor:TOKINPackage Cooled:0805-601D/C:08+
† All typical values are at VCC = 5 V, TA = 25C. ‡ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals.
Vendor:TOKINPackage Cooled:0805-601D/C:08+
† All typical values are at VCC = 5 V, TA = 25C. ‡ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals.
D/C:07+
cleared immediately, and remains cleared. If the power is restored (no UVREG or UVREF), and if no OVERTEMP fault exists, then the latched fault remains cleared when the RESET line returns to high. However, FAULT = 1 may still occur because a UVBOOT fault condition may still exist.
Vendor:NECPackage Cooled:SMDD/C:07+
ORDERING INFORMATION The MPX5010 pressure sensor is available in differential and gauge configurations. Devices are available in the basic ele- ment package or with pressure port fittings that provide printed circuit board mounting ease and barbed hose pressure connec- tions.
D/C:3000
This data was taken using the JEDEC standard High-K test PCB. Power rating is determined with a junction temperature of 125C. This is the point where distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or below 125C for best performance and long term reliability.
D/C:3000
This data was taken using the JEDEC standard High-K test PCB. Power rating is determined with a junction temperature of 125C. This is the point where distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or below 125C for best performance and long term reliability.
Package Cooled:08+D/C:07+
Notes a. Room = 25_C, Full = C40 to 85_C. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Typical values for dropout voltage at VOUT w 2 V are measured at VOUT = 3.3 V, while typical values for dropout voltage at VOUT < 2 V are measured at VOUT = 1.8 V...
Vendor:TOKINPackage Cooled:0805-121
Vcc = 2.7V~3.3V, TA = 0C to 70C/ -40C to 85C unless otherwise specified -55-70 #SymbolParameter Max.Min.Max. Min. READ CYCLE 1tRCRead Cycle Time55-70- 2tAAAddress Access Time-55-70 3tACSChip Select Access Time-55-70 4tOEOutput Enable to Output Valid-30-35 5tBA/LB, /UB Access Time-55-70 6tCLZChip Select to Output in Low Z10-10- 7tOLZOutput Enable to Output in Low Z5-5- 8tBLZ/LB, /UB Enable to Out...
D/C:07+
All outputs are capable of driving 2Vpp, AC or DC coupled, into either a single or dual video load. A single video load consists of a series 75Ω impedance matching resistor connected to a ter- minated 75Ω line. This presents a total of 150Ω of loading to the part. A dual load would be two of these in parallel which would present a total of 75Ω to the part. The gain of the Y, C and...
D/C:225000
Vendor:INTELPackage Cooled:99+D/C:24
Data written to the DS1267 over the 3-wire serial interface is stored in the 17-bit I/O shift register (see Figure 2). The 17-bit I/O shift register contains both 8-bit potentiometer wiper position values and the stack select bit. The composition of the I/O shift register is presented in Figure 2. Bit 0 of the I/O shift register contains the stack select bit, which will be discussed in the section entitled &...
Vendor:NIKOSPackage Cooled:SOP-3.9-14PD/C:SOP-3.9-14P
The Hynix HYM76V4M635HGT6 Series are 4Mx64bits Synchronous DRAM Modules. The modules are composed of four 4Mx16bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin glass-epoxy printed circuit board. Two 0.33uF and one 0.1uF decoupling capacitors per each SDRAM are mounted on the PCB.
Vendor:NIKOSPackage Cooled:SOP
ACCURACY (Internal Reference, = 2V, Unless Otherwise Noted) Zero Error (midscale)at 25C Zero Error Drift (midscale) Gain Error(4)at 25C Gain Error Drift(4) Gain Error(5)at 25C Gain Error Drift(5) Power-Supply Rejection of Gain∆VS = 5% Internal REF Tolerance (VREFP C VREFN)Deviation from Ideal Reference Input Resistance
Vendor:NIKOSPackage Cooled:TSSOP28PD/C:03+
NOTE A: The oscillator generates a sawtooth waveform on RC. During the RC rise time, the output stages alternate on time, but both stages are off during the RC fall time. The output stages switch a 1/2 the oscillator frequency, with ensured duty cycle of < 50% for both outputs.
Vendor:SSOP28Package Cooled:1780D/C:NIKOS
x IFAVM rating includes reverse blocking losses at TVJM, VR = 0.8 VRRM, duty cycle d = 0.5 Data according to IEC 60747 and refer to a single diode unless otherwise stated. IXYS reserves the right to change limits, test conditions and dimensions
Vendor:NECPackage Cooled:SOT-23D/C:08+
Each I/O cell contains a 4:1 dynamic MUX controlled by two select lines as well as a 4x4 crossbar switch con- trolled by software for increased routing flexiability (Figure 1). The four data inputs to the MUX (called M0, M1, M2, and M3) come from I/O signals in the GRP and/or adjacent I/O cells. Each MUX data input can access one quarter of the total I/Os. For example, in a 240-I/O ispGDXVA, each dat...
Vendor:NECPackage Cooled:SOT-23D/C:08+
Each I/O cell contains a 4:1 dynamic MUX controlled by two select lines as well as a 4x4 crossbar switch con- trolled by software for increased routing flexiability (Figure 1). The four data inputs to the MUX (called M0, M1, M2, and M3) come from I/O signals in the GRP and/or adjacent I/O cells. Each MUX data input can access one quarter of the total I/Os. For example, in a 240-I/O ispGDXVA, each dat...
Vendor:STPackage Cooled:DIP-20D/C:98+
120/277 VAC dual voltage input with surge-protect- ed, solid-state charging circuitry provides for a reliable charging system. The charging system is furnished with low voltage disconnect, AC lockout, brownout protection, AC indicator lamp and test switch.
Vendor:gvanellaPackage Cooled:gvanellaD/C:dc80+
An interrupt signal from an external RTC causes the firmware to compare the total energy consumed since the last interrupt to the value stored in data EEPROM and update the value if the consumed power is greater. This provides a record for tracking peak demand for one month. The default value for the interval is 30 minutes.
Package Cooled:PDIP48D/C:00+
The Auxiliary Input is multiplexed through to the output amplifier and speaker output pins when CE is HIGH and Playback has ended, or if the device is in overflow. When cascading multiple ISD1000A devices, the AUX IN pin is used to connect a Play- back signal from a following device to the previous output speaker drivers. For noise consid- erations, it is suggested that the Auxiliary Input not be driven whe...
Vendor:STPackage Cooled:DIPD/C:00+
The MAX1857 low-dropout linear regulator operates from a +2.5V to +5.5V supply and delivers a guaran- teed 500mA load current with low 120mV dropout. The high-accuracy (1%) output voltage is preset at an internally trimmed 4.75V or can be adjusted from 1.25V to 5.0V with an external resistive divider.
Vendor:SIPackage Cooled:TO-92D/C:04+
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the N2510 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid perfo...