N82C284

Vendor:INTELD/C:08+

Each DS1991 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (Figure 2.) The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 3. The polynomial is X8 + X5 + X4 + 1. Additional information about the D...

N82C288

Vendor:INTELD/C:08+

BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal (BHE) should be used to enable data onto the most significant half of the data bus, pins D15-D8. Eight bit oriented devices tied to the upper half of the bus would normally use BHE to condition chip select functions. BHE is LOW during T1 for read, write, and interrupt acknowledge cycles when a byte is to be transferred on the high portion ...

N82C288-10

Vendor:INTELPackage Cooled:PLCC20

This family of CMOS analog switches offers low resistance switching performance for analog voltages up to the supply rails and for signal currents up to 80mA. ON resistance is low and stays reasonably constant over the full range of operating signal voltage and current. RON remains exceptionally constant for input voltages between +5V and -5V and currents up to 50mA. Switch impedance also changes very...

N82C321

Vendor:INTELPackage Cooled:PLCC68

N82C42

Vendor:INTERPackage Cooled:PLCC44D/C:PLCC44

Likewise, the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW. The terminal count outputs can be used as the clock input signals to the next higher order circuit in a multistage counter, since they duplicate the clock waveforms. Multistage counters will not be fully synchronous, since there is a slight delay time difference added for each stage that is added.

N82C42EP

Each arbitrary length of data packet consists of 3 portions viz, Row address (R), Column address (C), and Display data (D). Format (a) is suitable for updating small amount of data which will be allocated with a differ- ent row address and column address. Format (b) is recommended for updating data that has the same row address but a different column address. Massive data updating or full screen data change ...

N82C42P

Vendor:1600

• A-Port outputs have equivalent 22-Ω series resistors, so no external resistors are required • Support mixed-mode signal operation (5V input and output voltages with 3.3V VCC) • Support unregulated battery operation down to 2.7V • Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, TA = 25 C • IOFF and power-up 3-state support hot insertion • Bus hold ...

N82C42P

Vendor:1600Package Cooled:CHIPS

• A-Port outputs have equivalent 22-Ω series resistors, so no external resistors are required • Support mixed-mode signal operation (5V input and output voltages with 3.3V VCC) • Support unregulated battery operation down to 2.7V • Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, TA = 25 C • IOFF and power-up 3-state support hot insertion • Bus hold ...

N82C42PESZ907

N82C501

Vendor:1000Package Cooled:intersilD/C:N/A

The ST7263 Microcontrollers form a sub family of the ST7 dedicated to USB applications. The de- vices are based on an industry-standard 8-bit core and feature an enhanced instruction set. They op- erate at a 24MHz or 12 MHz oscillator frequency. Under software control, the ST7263 MCUs may be placed in either Wait or Halt modes, thus reducing power consumption. The enhanced instruction set and addres...

N82C501ADSZ725

NEC's NESG2021M05 is fabricated using NECʼs high voltage Silicon Germanium process (UHS2-HV), and is designed for a wide range of applications including low noise amplifiers, medium power amplifiers, and oscillators.

N82C501AP

Vendor:PLCCPackage Cooled:CHIPSD/C:2004+

Input Voltage Range: 3.0V to 5.5V Regulated 5V Output 250mA Output Current with a 3.6V input 400mA Pulsed Output Current (up to 500ms duration) 60µA (typ.) Quiescent Current PFM Regulation Inductor-less solution: requires only 3 small capacitors < 1µA Typical Shutdown Current 10-pin LLP Package (No Pullback): 3mm x 3mm x 0.75mm

N82C501AP

Vendor:PLCCPackage Cooled:CHIPSD/C:2004+

Input Voltage Range: 3.0V to 5.5V Regulated 5V Output 250mA Output Current with a 3.6V input 400mA Pulsed Output Current (up to 500ms duration) 60µA (typ.) Quiescent Current PFM Regulation Inductor-less solution: requires only 3 small capacitors < 1µA Typical Shutdown Current 10-pin LLP Package (No Pullback): 3mm x 3mm x 0.75mm

N82C50AN

Vendor:NSPackage Cooled:4367

N82C51

N82C5412

N82C542 INTEL 06+ PLCC-28

N82C54N-2

If, after the ISL6118 has latched off, and the fault has asserted and the enable is not deasserted but the OC condition still exists, the ISL6118 (unlike other IC devices) does not send to the controller a continuous string of fault pulses. The ISL6118s single fault signal is sent at the time of latch off.

N82C55

Vendor:1000Package Cooled:intersilD/C:N/A

NOTES: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. (2) Input terminals are diode-clamped to the power supply rails. Input signals that can swing more than 0.3V beyond the supply rails should be current-limited to 10mA or less. (3) Short-circuit to ground, one amplifier per package.

N82C55A

Vendor:INTELPackage Cooled:PLCCD/C:N/A

When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to c...

N82C55A

Vendor:INTELPackage Cooled:PLCCD/C:N/A

When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to c...

N82C59A-2

Vendor:INTELPackage Cooled:PLCCD/C:N/A

N82C59A-2

Vendor:INTELPackage Cooled:PLCCD/C:N/A

N82F020-120

N82H321N

Vendor:SigPackage Cooled:DIP

N82HS137F

Vendor:SPackage Cooled:DIP18陶瓷D/C:83+

N82HS187N

Vendor:SigneticsPackage Cooled:DIP-24D/C:88

4.4.3 Group C inspection. Group C inspection shall be conducted in accordance with the conditions specified for subgroup testing in appendix E, table VII of MIL-PRF-19500 and as follows. Electrical measurements (end-points) and delta requirements shall be in accordance with table III herein.

N82HS189

Vendor:PHILIPSPackage Cooled:DIP

N82HS189AF

Vendor:PHILPackage Cooled:DIP-24D/C:97+

NOTE: 1.Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

N82HS191N3

Vendor:SigneticsPackage Cooled:DIP-24D/C:9005

ITM-M-SR turns a complete video camera into a component of your product. ITM-M-SR, a CMOS type video camera, is specially designed for the cost sensitive consumer electronics application. ITM-M-SR offers the unique benefits such as a low power consumption, low cost, small size together with consistent image quality.

N82HS195A/BRA

Vendor:PHD/C:97

Note 2: The algebraic convention, where the most negative value is a minimum and the most positive value a maximum, is used in this data sheet. Note 3: SC70-packaged parts are 100% tested at +25C. Limits across the full temperature range are guaranteed by design and correlation. Note 4: Flatness is defined as the difference between the maximum and minimum values of on-resistance as measured over the spe...

N82HS195AF

Vendor:PHILPackage Cooled:DIP-20D/C:97+

NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 13. All loading with 50 Ω to VCC−2.0 volts....

N82HS195AF

Vendor:PHILPackage Cooled:DIP-20D/C:97+

NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 13. All loading with 50 Ω to VCC−2.0 volts....

N82HS195AF(87S195 27S41)

Vendor:PHI/S

N82HS195AF/NO6

Vendor:S

N82HS195AN

Package Cooled:DIPD/C:630

The N82HS195AN uses bus cycles of 8 bits each for commands, data, and addresses to execute operations. The operation instructions are listed in the table below. All instructions are synchronized off a high to low transition of #CE. The first low to high transition on SCK will initiate the instruction sequence. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. Any low ...

N82HS195BN

Package Cooled:N/AD/C:DIP

Sector Protection C Any combination of sectors may be locked to prevent program or erase operations within those sectors Temporary Sector Unprotect C Allows changes in locked sectors (requires high voltage on RESET# pin) Internal Erase Algorithm C Automatically erases a sector, any combination of sectors, or the entire chip Internal Programming Algorithm C Automatically programs and verifies da...

N82HS195N

Vendor:PHIPackage Cooled:DIP20D/C:87+

Single-channel isolated signal-conditioning modules. Accepts outputs from Thermocouple, millivolt, volt and current signals. Complete microcomputer-based data acquisition systems. Can be remotely reconfigured for various sensor types and input ranges.

N82HS321

Vendor:PHILIPSPackage Cooled:DIP

• HIGH-DENSITY PROGRAMMABLE LOGIC 8000 PLD Gates 96 I/O Pins, Ten Dedicated Inputs 288 Registers High-Speed Global Interconnects Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic Security Cell Prevents Unauthorized Copying • HIGH PERFORMANCE E2CMOS® TECHNOLOGY fmax = 80 MHz Maximum Operating Frequency ...

N82HS321

Vendor:PHILIPSPackage Cooled:DIP

• HIGH-DENSITY PROGRAMMABLE LOGIC 8000 PLD Gates 96 I/O Pins, Ten Dedicated Inputs 288 Registers High-Speed Global Interconnects Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic Security Cell Prevents Unauthorized Copying • HIGH PERFORMANCE E2CMOS® TECHNOLOGY fmax = 80 MHz Maximum Operating Frequency ...

N82HS321/NO8

Vendor:PHI

N82HS321A/BJA

Vendor:PHILIPSPackage Cooled:DIPD/C:92+

N82HS321A/BJA

Vendor:PHILIPSPackage Cooled:DIPD/C:92+

N82HS321AA

Vendor:PHILIPSPackage Cooled:PLCC28

Referenced to VCCA Voltage VCC Isolation Feature − If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2-V to 3.6-V Power-Supply Range Ioff Supports Partial-Power-Down Mode Operation I/Os Are 4.6-V Tolerant Bus Hold o...

N82HS321AF

Vendor:PHILPackage Cooled:DIP-24D/C:96+

D Auto Selection of S/E or LVD SCSI Termination D 2.7-V to 5.25-V TERMPWR Range D Meets SCSI-1, SCSI-2, SPI-2 (ULTRA-2), SPI-3 (ULTRA-160) and SPI-4 (ULTRA-320) Standards D Differential Failsafe Bias D Thermal Package D On-Chip Thermal Shutdown Circuit D Master/Slave Input D Active Negation D Hot Swap Compatible

N82HS321AF/NO3

Vendor:PHI

N82HS321AN

Vendor:S/PHIPackage Cooled:DIPD/C:04+

• Dual Outputs (Independantly Regulated) • Power-up/Down Sequencing • Input Voltage Range: 36V to 75V • 1500 VDC Isolation • Temp Range: C40 to 100C • High Efficiency: 88% • Fixed Frequency Operation • Over-Current Protection (Both Outputs)

N82HS321AN

Vendor:S/PHIPackage Cooled:DIPD/C:04+

• Dual Outputs (Independantly Regulated) • Power-up/Down Sequencing • Input Voltage Range: 36V to 75V • 1500 VDC Isolation • Temp Range: C40 to 100C • High Efficiency: 88% • Fixed Frequency Operation • Over-Current Protection (Both Outputs)

N82HS321B

Vendor:PHILIPS

N82HS321B

Vendor:PHILIPS

N82HS321BA.N82HS321AA

Vendor:大SPackage Cooled:PLCC28

N82HS321BF

Vendor:PHIPackage Cooled:ＤＩＰ

Widebus  Family Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25C Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Ioff Supports Partial-Power-Down Mode Operation Latch-Up Perf...

N82HS321BF

Vendor:PHIPackage Cooled:ＤＩＰ

Widebus  Family Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25C Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Ioff Supports Partial-Power-Down Mode Operation Latch-Up Perf...

N82HS321BF/NO9

Vendor:PHI

N82HS641A/BJA

Vendor:PHILIPSPackage Cooled:DIPD/C:91+

The HY62SF16201A is a high speed, low power and 2M bit full CMOS SRAM organized as 131,072 words by 16bit. The HY62SF16201A uses high performance full CMOS process technology and designed for high speed low power circuit technology. It is particularly well suited for used in high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum po...

N82HS641AF

Vendor:S/PHIPackage Cooled:CDIP24D/C:——

stream and 24 Mbps downstream. This device is ide- al for power and area sensitive Central Office equipment, providing highest performance and den- sity while meeting all telecom grade equipment re- quirements. The STLC61255 is designed for minimal host controller intervention during runtime operation. Combining this feature with additional management interfaces such as the serial host interface and ...

N82HS641AF

Vendor:S/PHIPackage Cooled:CDIP24D/C:——

stream and 24 Mbps downstream. This device is ide- al for power and area sensitive Central Office equipment, providing highest performance and den- sity while meeting all telecom grade equipment re- quirements. The STLC61255 is designed for minimal host controller intervention during runtime operation. Combining this feature with additional management interfaces such as the serial host interface and ...

N82HS641AF/NO8

Vendor:PHI

N82HS641BF

Vendor:大SPackage Cooled:DIP24陶瓷D/C:90+

96 Outputs Plasma Display Driver 90V Absolute Maximum Rating Reduced EMI (Electro Magnetic Interference) 3.3V / 5V Compatible Logic -40 / 30 mA Source / Sink Output Mos 6 Bit Data Bus (40 MHz) BCD Process Packaging Adapted to Customer Request (DICE, COB, COF, TAB).

N82HS641BF

Vendor:大SPackage Cooled:DIP24陶瓷D/C:90+

96 Outputs Plasma Display Driver 90V Absolute Maximum Rating Reduced EMI (Electro Magnetic Interference) 3.3V / 5V Compatible Logic -40 / 30 mA Source / Sink Output Mos 6 Bit Data Bus (40 MHz) BCD Process Packaging Adapted to Customer Request (DICE, COB, COF, TAB).

N82HS641BF/NO3

Vendor:PHI

N82HS641N

The DG411/883 series monolithic CMOS analog switches are drop-in replacements for the popular DG211 and DG212 series devices. They include four independent single pole throw (SPST) analog switches, and TTL and CMOS compat- ible digital inputs.

N82LS135N

Vendor:PHILIPSPackage Cooled:DIP/20

The MB90590/590G series with two FULL-CAN*1 interfaces and FLASH ROM is especially designed for automo- tive and industrial applications. Its main features are two on board CAN Interfaces, which conform to V2.0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full CAN approach. The instruction set of F2MC-16LX CPU core inherits an AT a...

N82LS16F

Vendor:PHIPackage Cooled:DIP=16

Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBest Programming support CAlteras Master Programming Unit (MPU) and programming hardware from third-party manufact...

N82LS16F

Vendor:PHIPackage Cooled:CDIP16

Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBest Programming support CAlteras Master Programming Unit (MPU) and programming hardware from third-party manufact...

N82LS16N

Vendor:PHILIPSPackage Cooled:DIP

N82LS16N

Vendor:PHILIPSPackage Cooled:DIP

N82S09/82S19/PLS105

N82S09/BXA

Vendor:SING/PHID/C:97+

ADC Noise Filtering The ADC is an integrating type with inherently good noise rejection. Micropower operation places con- straints on high-frequency noise rejection; therefore, careful PC board layout and proper external noise fil- tering are required for high-accuracy remote meas- urements in electrically noisy environments.

N82S09/BXA

Vendor:SING/PHID/C:97+

ADC Noise Filtering The ADC is an integrating type with inherently good noise rejection. Micropower operation places con- straints on high-frequency noise rejection; therefore, careful PC board layout and proper external noise fil- tering are required for high-accuracy remote meas- urements in electrically noisy environments.

N82S100/BXA

D/C:91

The second case to consider is static discharges to the exterior of the host equipment chassis after installation. To the extent that the optical interface is exposed to the outside of the host equipment chassis, it may be subject to system-level ESD requirements.

N82S100/BXA

D/C:91

The second case to consider is static discharges to the exterior of the host equipment chassis after installation. To the extent that the optical interface is exposed to the outside of the host equipment chassis, it may be subject to system-level ESD requirements.

N82S100F

Vendor:PHIPackage Cooled:DIPD/C:N/A

• HiPerFET TM technology C low RDSon C unclamped inductive switching (UIS) capability C dv/dt ruggedness C fast intrinsic reverse diode C low gate charge • thermistor for internal temperature measurement • package C low inductive current path C screw connection to high current main terminals C use of non interchangeable connectors for auxiliary terminals possible C ...

N82S100F883B

Vendor:SING/PHID/C:97+

N82S100F883B

Vendor:SING/PHID/C:97+

N82S100N

Vendor:PHILIPSPackage Cooled:DIP28

The purchase of this product conveys to the buyer the non-transferable right to use the purchased amount of the product and components of the product in research conducted by the buyer (whether the buyer is an academic or for-profit entity). The buyer cannot sell or otherwise transfer (a) this product (b) its components or (c) materials made using this product or its components to a third party or otherwise u...

N82S100N

Vendor:PHILIPS

The purchase of this product conveys to the buyer the non-transferable right to use the purchased amount of the product and components of the product in research conducted by the buyer (whether the buyer is an academic or for-profit entity). The buyer cannot sell or otherwise transfer (a) this product (b) its components or (c) materials made using this product or its components to a third party or otherwise u...

N82S101/BXA

Vendor:PHI/S

N82S101N

Vendor:SPackage Cooled:DIP

NOTES: 1. Dimensions are in inches. 2. Metric equivalents are given for general information only. 3. Symbol TL is measured from HD maximum. 4. Lead number 4 omitted on this variation. 5. CD shall not vary more than .010 inch (0.25 mm) in zone P. This zone is controlled for automatic handling. 6. Leads at gauge plane .054 inch (1.37 mm) + .001 (0.03 mm) - .000 inch (0.00 mm) below seating plane sha...

N82S103N

Vendor:PHIPackage Cooled:DIP-28D/C:8416

Two important wavelength ranges (windows 2 and 3) are in use for transmitting information over a fiber cable in telecommunication networks. Within an optical window, the signals benefit from a lower impact on quality (less dispersion) and less attenuation per unit of fiber length. The range between 1000nm and 1300nm, called the second optical window, is known for low dispersion-as low as 0dB. The range from...

N82S105/BXA

Vendor:SING/PHID/C:97+

N82S105AF

Vendor:大SPackage Cooled:DIP28陶瓷D/C:86+

The ICSI IC61S6432 is a high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, secondary cache for the Pentium™, 680X0™, and PowerPC™ microprocessors. It is organized as 65,536 words by 32 bits, fabricated with ICSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs i...

N82S105F

Vendor:大SPackage Cooled:DIP-28陶瓷D/C:81+

In questo capitolo saranno illustrate tutte le operazioni da effettuare per ottenere il corretto funzionamento della scheda. A questo scopo di seguito riportata la funzione dei jumpers, dei connettori e di tutti quei componenti che possono modificare il comportamento della scheda.

N82S105N

ISO256 is a precision three-port isolation operational amplifier incorporating an uncommitted operational amplifier for input conditioning and a novel duty cycle modulation-demodulation technique which has excel- lent accuracy. Internal input protection can withstand up to 30V input differential without damage. The signal is transmitted digitally across a differential capacitive barrier. With digital ...

N82S107F

Vendor:SPackage Cooled:DIPD/C:06+

Note 6: Output rise and fall times are measured between the 10% and 90% power supply levels. These specifications are based on characterization. Note 7: Guaranteed by 5V test. Note 8: The LTC6900C is guaranteed to meet specified performance from 0C to 70C. The LTC6900C is designed, characterized and expected to meet specified performance from C 40C to 85C but is not tested or QA sampled at these temperatur...

N82S107F

Vendor:SPackage Cooled:DIPD/C:06+

Note 6: Output rise and fall times are measured between the 10% and 90% power supply levels. These specifications are based on characterization. Note 7: Guaranteed by 5V test. Note 8: The LTC6900C is guaranteed to meet specified performance from 0C to 70C. The LTC6900C is designed, characterized and expected to meet specified performance from C 40C to 85C but is not tested or QA sampled at these temperatur...

N82S112N

Vendor:PHIPackage Cooled:DIP+24

† The D package is available taped and reeled. Add the suffix R to the device type when ordering (e.g., TLC7705QDR). ‡ The PW package is only available left-end taped and reeled (indicated by the LE suffix on the device type; e.g., TLC7705QPWLE).

N82S114F

N82S115/BJA

Vendor:SPackage Cooled:91+D/C:DIP

Demodulator Converts the PSK signal shaped by the carrier extraction circuit of the analog block into binary data. Digital PLL Compares the frequency of the oscillator circuit in the analog block with the signal shaped by the carrier extraction circuit and generates a clock with a fixed frequency for operation of the entire digital block. Using the clock the internal LSI operates in synchronize with the ca...

N82S115F

Vendor:大SPackage Cooled:DIP24陶瓷D/C:78+

Resolution Integral Nonlinearity (fin = 10kHz) Differential Nonlinearity (fin = 10kHz) Full Scale Absolute Accuracy Bipolar Zero Error (Tech Note 2) Unipolar Offset Error (Tech Note 2) Gain Error (Tech Note 2) No Missing Codes (fin = 10kHz)

N82S115N

Vendor:SPackage Cooled:sigD/C:06+

Simple primary side control solution to enable full-bridge DC-Bus Converters for 48V distributed systems with reduced component count and board space. Frequency and dead time set by two external components Maximum 500KHz per channel output with 50% duty cycle Adjustable dead time 50nsec ~ 200nsec Floating channel designed for bootstrap operation up to +100Vdc High and low side pulse width matching to +...

N82S123

Note 1) The specified condition Tj=25˚C means that the test should be carried out with the test time so short (within 10ms) that the drift in characteristic value due to the rise in chip junction temperature can be ignored. Note 2) When not specified, VI=9V, IO=100mA, CI=0.33µF, CO=0.1µF, Tj=0 to 125˚C

N82S123/BEA

Vendor:PHILIPSD/C:9813

N82S123AF

Vendor:PHILPackage Cooled:DIP-16D/C:90/97+

Notes: 1. Load and Line Regulation are specified at a constant junction temperature. Pulse testing with low duty cycle is used. Changes in output voltage due to heating effects must be taken into account separately. 2. If not tested, shall be guaranteed to the specified limits. 3. The • denotes the specifications which apply over the full operating temperature range.

N82S123F(50NS)

Vendor:S/PHIPackage Cooled:CDIP16D/C:——

N82S123F/AF

Vendor:陶DIP16Package Cooled:SD/C:02+

There are no user serviceable parts nor any maintenance required for the HFBR-5710L. All adjustments are made at the factory before shipment to our customers. Tampering with, modifying, misusing or improp- erly handling the HFBR-5710L will void the product warranty. It may also result in improper operation of the HFBR-5710L circuitry, and possible overstress of the laser source. Device deg...

N82S123F/NO3

Vendor:PHI

N82S123N

Vendor:PHILIPSPackage Cooled:DIP/16

The CY7B951 can be used in Local Area Network ATM appli- cations. The operating frequency of the CY7B951 is centered around the SONET/SDH STS-1 rate of 51.84 MHz and the SONET/SDH STS-3/STM-1 rate of 155.52 MHz. This device can also be used in data mover and Local Area Network (LAN) applications that operate at these frequencies.

N82S125AA

N82S126

Vendor:S/PHIPackage Cooled:CDIP16D/C:——

Bidirectional I/O line. Software instructions deter- mine the CMOS output, Schmitt trigger input with or without a pull-high resistor (determined by pull-high options: bit option). The PWM output function is pin-shared with PD0 (dependent on PWM options).