NCP1012ST65T3

Vendor:ONPackage Cooled:SOT223D/C:06+

The SRAM has an extremely low Soft Error Rate (SER) as specified in the table below. This hardness level is defined by the Adams 90% worst case cosmic ray environment. The low SER is achieved by the use of a unique 7-transistor memory cell and the oxide isolation of the SOI substrate.

NCP1012ST65T3G

Vendor:ONPackage Cooled:SOT223D/C:07+

The EMC1002 generates two separate interrupts with programmable thermal trip points. The THERM output operates as a thermostat with programmable threshold and hysteresis. The ALERT output can be configured as a maskable SMBus alert with programmable window comparator limits, or a second THERM output.

NCP1013AP065G

Vendor:ONPackage Cooled:DIP-7D/C:DIP-7

Atmel can accept Register Transfer level (RTL) designs for VHDL (MIL-STD-454, IEEE STD 1076) or Verilog-HDL format. Atmel fully supports Synopsys for VHDL simula- tion as well as synthesis. Design via VHDL or Verilog- HDL is the preferred method of performing a gate array design.

NCP1013AP100G

Vendor:ONPackage Cooled:2005D/C:DIP-7

The NCP1013AP100G solution saves valuable board space. The device is housed in the space-saving SO-8 package, whose low pin-count minimizes external components. Its 400kHz PWM operation allows a small inductor and small output capacitors to be used. The NCP1013AP100G can implement all- ceramic capacitor solutions.

NCP1013ST100T3

Vendor:OND/C:05+

6 bit VR10 compatible VID with 0.5% overall system accuracy 1 to X phases operation with matching phase ICs On-chip 700Ω VID Pull-up resistors with VID pull-up voltage input Programmable Dynamic VID Slew Rate No Discharge of output capacitors during Dynamic VID step-down (can be disabled) +/-300mV Differential Remote Sense Programmable 150kHz to 1MHz oscillator Programmable VID Offset and Load Line out...

NCP1013ST130T3

Vendor:ON

Current-Limited Wall Supplies Ideal for Low Dropout Charger Design for Single-Cell Li-Ion Packs With Coke or Graphite Anodes Integrated PowerFET for 500 mA Integrated Voltage Regulation With 0.5% Accuracy Battery Insertion and Removal Detection Charge Termination by Minimum Current and Time Pre-Charge Conditioning With Safety Timer Sleep Mode for Low-Power Consumption Charge Status Output for LED or Hos...

NCP1013ST65T3

Vendor:ON

Muting all channel drivers can be obtained using the REF (signal reference) pin. The simplified schematic diagram for reference all mute function is shown in Fig.1. When the input voltage of the signal reference pin (pin23) is below 1.0V, the comparator turns Q1 on and the bias currents of all output drivers are shut down.

NCP1013ST65T3

Vendor:ON

Muting all channel drivers can be obtained using the REF (signal reference) pin. The simplified schematic diagram for reference all mute function is shown in Fig.1. When the input voltage of the signal reference pin (pin23) is below 1.0V, the comparator turns Q1 on and the bias currents of all output drivers are shut down.

NCP1014AP06

Vendor:ONPackage Cooled:DIP-7D/C:04+

Input Low Voltage Input Current (with pull-up/pull-down) Input Current (no pull-up/pull-down) Input Capacitance2 DIGITAL OUTPUTS (BUSY, SDO) Output Low Voltage Output High Voltage (SDO) High Impedance Leakage Current High Impedance Output Capacitance2

NCP1014AP065

Vendor:ON

A logic 0 applied to this input forces the transcoder into a low power dissipation mode. A rising edge on this pin causes power to be restored and the optional transcoder RESET state (specified in the standards) to be forced. Valid data is available at the output pins four input enables after a rising edge on this pin. This pin has a CMOS compatible input.

NCP1014AP065

Vendor:ON

A logic 0 applied to this input forces the transcoder into a low power dissipation mode. A rising edge on this pin causes power to be restored and the optional transcoder RESET state (specified in the standards) to be forced. Valid data is available at the output pins four input enables after a rising edge on this pin. This pin has a CMOS compatible input.

NCP1014AP10

Vendor:ONPackage Cooled:DIP-7D/C:04+

The 60320 uses burst-mode charge transfer methods pioneered and patented by Quantum, including charge cancellation methods which allow for a wide range of key sizes and shapes to be mixed together in a single keypanel. These features permit the construction of entirely new classes of keypanels never before contemplated, such as touch-sliders, back-illuminated keys, and arbitrary shape keypanels, all a...

NCP1014AP100

Vendor:ON

NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O.

NCP1014AP100G

Vendor:ONPackage Cooled:PDIP-7D/C:0815+

The Hynix 2Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter- nally pipelined and 2-bit prefetched to achieve very high ...

NCP1014APL100R2G

Vendor:ONPackage Cooled:2005D/C:500

7.5 ATM Encapsulation and spanning-tree RFC 1483/2684 provides a simple robust method of connecting end stations over an ATM network. User data in the form of Ethernet packets are encapsulated into AAL-5 PDUs for transport over ATM. RFC 1483/2684 provides no AAA function (authentication, authorization & accounting).

NCP1014APO65G

Vendor:OND/C:08 +

NCP1014ST100T3

Vendor:ONPackage Cooled:SOT223D/C:06+

NCP1014ST100T3

Vendor:ONPackage Cooled:SOT223D/C:06+

NCP1014ST100T3G

Vendor:ONPackage Cooled:SOT-22D/C:08+

(Segment mode) ! Shift Clock frequency: 14 MHz (Max.) (VDD = 5V 10%) 8 MHz (Max.) (VDD = 2.5V - 4.5V) ! Adopts a data bus system ! 4-bit / 8-bit parallel input modes are selectable with a mode (MD) pin ! Automatic transfer function with an enable signal ! Automatic counting function when in chip select mode, which causes the internal clock to be stopped by automatically counting 160 bits of inpu...

NCP1014ST65T3G

Vendor:ON原装无铅D/C:08+09+

The DAA can be soldered directly to the host circuit card or installed in sockets. To avoid the problems of contamination, hand soldering is preferred to wave soldering. When hand cleaning use only deionized water; when wave soldering use washless flux.

NCP1015AP065G

LDQM and UDQM control the lower and upper bytes of the DQ buffers. In read mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the corre- sponding buffer byte is enabled, and when HIGH, dis- abled. The outputs go to the HIGH Impedance State when LDQM/UDQM is HIGH. This function corresponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer. When LD...

NCP1015AP100G

Vendor:ON

Turn on current (IFT), 5.0 mA typical Gate trigger current (IGT), 20 µA Surge anode current, 1.0 AMP Blocking voltage, 400 V Gate trigger voltage (VGT), 0.6 Volt Isolation Test Voltage, 5300 VRMS Solid State Reliability Standard DIP Package Lead-free component

NCP1027P065G

Vendor:On semiD/C:07+

Timer • Timer 0 : 16-bit timer/counter With 2-bit prescaler + 8-bit programmable prescaler Mode 0 : Two 8-bit timers with a programmable prescaler Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter Mode 2 : 16-bit timer with a programmable prescaler Mode 3 : 16-bit counter The resolution of timer is 1 tCYC. • Base timer Generate every 500ms overflow for a clock appli...

NCP1027P100G

Vendor:On semiD/C:07+

The MSK 4301 is a 3 phase MOSFET bridge plus drivers in a convenient isolated hermetic package. The hybrid is capable of 29 amps of output current and 75 volts of DC bus voltage. It has a full line of protection features, including undervoltage lockout protection of the bias voltage, cross conduction control and a user programmable dead-time control for shoot-through elimination. In addition, the bridge ma...

NCP1030DMR2

Vendor:OND/C:03

DESCRIPTION: The CENTRAL SEMICONDUCTOR CMPZDA2V4 Series silicon dual zener diode is a high quality voltage regulator, connected in a common anode configuration, for use in industrial, commercial, entertainment and computer applications.

NCP1030DMR2G

Vendor:ONPackage Cooled:MICRO8D/C:05+

Hynix HYMD116G725A(L)8M-K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to iden- tify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

NCP1031DR2G

Vendor:NXP

1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC . 4. IccSB1_MAX. is 5uA/30uA at Vcc=3.0V/5.0V and TA=70oC. 5. Icc_MAX. is 27mA(@3.0V)/65mA(@5.0V) under 55ns operation.

NCP1031DR2G

Vendor:NXP

1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC . 4. IccSB1_MAX. is 5uA/30uA at Vcc=3.0V/5.0V and TA=70oC. 5. Icc_MAX. is 27mA(@3.0V)/65mA(@5.0V) under 55ns operation.

NCP1050A

Vendor:ONPackage Cooled:DIP-7D/C:04+

O When 16/68# pin is at logic 1 for Intel bus interface, this ouput (OD) becomes channel A interrupt output. The output state is defined by the user and through the software setting of MCR[3]. INTA is set to the active mode when MCR[3] is set to a logic 1. INTA is set to the three state mode when MCR[3] is set to a logic 0 (default). See MCR[3]. When 16/68# pin is at logic 0 for Motorola bus interf...

NCP1050ST100T3

Vendor:ON

NCP1050ST136T3

Vendor:ON

Four address spaces, the Program Memory, Register File, Data Memory, and Expanded Register File (ERF) support a wide range of memory configurations. Through the ERF the designer has access to three additional control registers that provide extra peripheral devices, I/O ports, and register addresses.

NCP1050ST136T3G

NCP1051A

Vendor:ONPackage Cooled:DIP/7D/C:03+

NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

NCP1051B

Vendor:ONPackage Cooled:DIP-7D/C:04+

3.6 Link Test and Jabber Logic The link test circuit performs the necessary link test functions specified by IEEE 802.3. The link test function is enabled when LTE/LS is sampled high during reset period. If the link test function is enabled, the LTE/LS pin becomes an output that can drive the link LED display. To disable the link test function, LTE should be tied low. The link test function can be changed on...

NCP1051C

Vendor:ONPackage Cooled:DIP/7D/C:03+

The encoder has an enable function for use in multiplexer applications. Encoder and Decoder forced idle capabilities are provided forcing 10101010pattern in encode and a VDD/2 bias in decode. The companding circuit may be operated with an externally selectable 3- or 4-bit algorithm. The device may be placed in standby mode by selecting Powersave. A reference 1.024MHz oscillator uses an external clock or ...

NCP1051ST100T3

Vendor:ON

NCP1051ST136T3

Vendor:ONPackage Cooled:SOT-223D/C:04+

is the case then the N-Channel MOSFET is fully enhanced and the CTIM capacitor is discharged. Once CTIM charges to 1.87V, signaling that the time out period has expired an internal latch is set whereby the FET gate is quickly pulled to 0V turning off the N-Channel MOSFET switch, isolating the faulty load.

NCP1052A

Vendor:ONPackage Cooled:DIP-7D/C:04+

NCP1052A

Vendor:ONPackage Cooled:DIP-8D/C:04+

NCP1052P136

Vendor:ON

The microcontroller instruction set is based on the AT architecture of the F2MC* family with additional instructions for high-level languages, extended addressing modes, enhanced multiplication and division instructions, and a complete range of bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word (32-bit) data.

NCP1052ST100T3

Vendor:ONPackage Cooled:SOT-223D/C:03+

Note 5: A military RETS specification is available on request. At the time of printing, the military RETS specifications for the LM140AK-5.0/883, LM140AK-12/883, and LM140AK-15/883 complied with the min and max limits for the respective versions of the LM140A. At the time of printing, the military RETS specifications for the LM140K-5.0/883, LM140K-12/883, and LM140K-15/883 complied with the min and max limit...

NCP1052ST136T3

Vendor:N/APackage Cooled:N/AD/C:08+09+

NCP1052ST136T3G

Vendor:N/APackage Cooled:N/AD/C:08+09+

If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the FX2LP substitutes its INT2VEC byte. Therefore, if the high byte (page) of a jump-table address is preloaded at location 0x0044, the automatically-inserted INT2VEC byte at 0x0045 will direct the jump to the correct address out of the 27 addresses within the page.

NCP1053

Vendor:ONPackage Cooled:DIP7D/C:00+

Stable Oscillation Using External Resistor Lock Frequency Range: C 35 MHz to 75 MHz (VDD = 5 V 0.25 V, TA = C 20C to 85C) C 28 MHz to 50 MHz (VDD = 3 V 0.15 V, TA = C 20C to 85C) Operating Free-Air Temperature Range, TA = C 20C to 85C 8-Pin Thin Shrinked Small-Outline Package

NCP1053A

Vendor:ONPackage Cooled:DIP/7D/C:03+

All the Data ALU operations are performed in two clock cycles in pipeline fashion so that a new instruction can be initiated in every clock, yielding an effective execution rate of one instruction per clock cycle. The destination of every arithmetic operation can be used as a source operand for the immediately following arithmetic operation without a time penalty (i.e., without a pipeline stall).

NCP1053ACKTN

Vendor:DIPD/C:03+

NCP1053B

Vendor:ONPackage Cooled:DIP-7D/C:04+

The Victory66 SLC90E66 Enhanced PCI South Bridge with Ultra ATA/66MHz IDE Controller is a multi-function PCI device implementing a PCI-to-ISA bridge function, a PCI Ultra ATA/66 IDE controller function, a Universal Serial Bus host/hub function, and an Enhanced Power Management function. As a PCI-to-ISA bridge, the SLC90E66 integrates I/O functions found in a common ISA bridge chip, that includes two DMA contr...

NCP1053B

Vendor:ONPackage Cooled:DIP-7D/C:04+

The Victory66 SLC90E66 Enhanced PCI South Bridge with Ultra ATA/66MHz IDE Controller is a multi-function PCI device implementing a PCI-to-ISA bridge function, a PCI Ultra ATA/66 IDE controller function, a Universal Serial Bus host/hub function, and an Enhanced Power Management function. As a PCI-to-ISA bridge, the SLC90E66 integrates I/O functions found in a common ISA bridge chip, that includes two DMA contr...

NCP1053P100

Vendor:ON

The Fairchild Semiconductors RMLA3565C is a single bias wideband low noise MMIC amplifier designed for the 3.5C 6.5 GHz frequency range. The MMIC requires no external matching circuits or external gate bias supply. This device uses our advanced 0.25µm PHEMT process to provide low noise, high linearity, and low current.

NCP1053ST100T3

Vendor:ON

The Read operation of the EM39LV040 is controlled by CE# and OE#. Both have to be Low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read Cy...

NCP1053ST136T3

Vendor:ONPackage Cooled:SOT223D/C:07+

MAX 7000A devices contain from 32 to 512 macrocells that are combined into groups of 16 macrocells, called logic array blocks (LABs). Each macrocell has a programmable-AND/fixed-OR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. To build complex logic functions, each macrocell can be supplemented with both shareable expander product term...

NCP1054A

Vendor:ONPackage Cooled:DIP-7D/C:N/A

Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 7: The minimum on-time condition is specified for an inductor peak- to-peak ripple current 40% of IMAX (see Minimum On-Time Considerations in the Applicatio...

NCP1054ST100T3

Vendor:ON

The Si9711CY is a monolithic switch designed to meet the needs of the PC Card interface. The inputs are fully CMOS compatible and incorporate all the level shift and interface required to be driven by any CMOS driver. The external inputs can be driven to 3.3-V or 5-V by setting VL at the appropriate level. The switches are low RON and can carry the maximum currents found on the PC Card interface.

NCP1055B

Vendor:ONPackage Cooled:DIP7

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

NCP1055C

Vendor:OND/C:01+

The ICL8052 or ICL8068/lCL71C03 chip pairs with their multiplexed BCD output and digit drivers are ideally suited for the visual display DVM/DPM market. The outstanding 41/2 digit accuracy, 200.00mV to 2.0000V full scale capabil- ity, auto-zero and auto-polarity combine with true ratiometric operation, almost ideal differential linearity and time-proven dual slope conversion. Use of these chip pairs el...

NCP1055C

Vendor:OND/C:01+

The ICL8052 or ICL8068/lCL71C03 chip pairs with their multiplexed BCD output and digit drivers are ideally suited for the visual display DVM/DPM market. The outstanding 41/2 digit accuracy, 200.00mV to 2.0000V full scale capabil- ity, auto-zero and auto-polarity combine with true ratiometric operation, almost ideal differential linearity and time-proven dual slope conversion. Use of these chip pairs el...

NCP1055P100G

Cs: The input pin to the overcurrent comparator. Exceeding the overcurrent threshold value specified in Static Electrical Parameters Section will terminate output pulses. A new soft start cycle will commence after the expiration of the programmed delay time at DELAY pin.

NCP1055ST100T3

Vendor:ON

All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. The data was taken at CL = 15 pF, RL = 2 kΩ (see Figure 1). The data was taken at CL = 30 pF, RL = 500 Ω (see Figure 1).

NCP1055ST100T3G

Generates Three Voltages: 5.1V at 10mA C 5V, C10, or C15V at 500µA 10V or 15V at 500µA Better than 90% Efficiency Low Output Ripple: Less than 5mVP-P Complete 1mm Component Profile Solution Controlled Power-Up Sequence: AVDD/VGL/VGH All Outputs Disconnected and Actively Discharged in Shutdown Low Noise Fixed Frequency Operation Frequency Reduction Input for High Efficiency in Blank Mod...

NCP1055ST136T3

Vendor:ON

FullCAN interface with 15 message buffers complaint to CAN specification 2.0B active Versatile Timer Unit with four subsystems (VTU) Two analog comparators Integrated WATCHDOG logic I/O Features Up to 56 general-purpose I/O pins (shared with on-chip peripheral I/O pins) Programmable I/O pin characteristics: TRI-STATE out- put, push-pull output, weak pull-up input, high-imped- ance input Schmi...

NCP1086-A

Vendor:ONPackage Cooled:TO-220D/C:06+

256K x 36, 512K x 18 memory configurations Supports fast access times: C 7.5ns up to 117MHz clock frequency C 8.0ns up to 100MHz clock frequency C 8.5ns up to 87MHz clock frequency LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW byte writeGW),GW enable (BWE and byte writes (BWBWE),BWx)BWEBW 3.3V core power supply Power down controlled by ZZ input 3.3...

NCP1086D2T-033

Serial data at 2048 kbit/s is received at the eight ST-BUS inputs (STi0 to STi7), and serial data is transmitted at the eight ST-BUS outputs (STo0 to STo7). Each serial input accepts 32 channels of digital data, each channel containing an 8-bit word which may represent a PCM-encoded analog/voice sample as provided by a codec. This serial input word is converted into parallel data and stored in the ...

NCP1086D2T-33

Vendor:D2PAK-3Package Cooled:673D/C:05+

Controller (MAC) for Supporting Standard Rates up to 11 Mbps Supports Antenna Diversity Algorithm, Automatic Receive Gain Control, Transmit Gain Control, Transmit Filter for Japanese Regulatory and Differential or Single-Ended I- and Q-Baseband Signals Integrates 160 KBytes of SRAM Organized in Five Banks of 32 KBytes Each, Offering the Flexibility for individually Configuring Each of Them as Program or Dat...

NCP1086D2T-33R4

Vendor:ON

• Two global inputs and two global outputs for general purpose I/O • Power down mode • On chip crystal oscillator, 2C8 MHz • TTL input levels. Outputs switch between full VCC and VSS • High speed CMOS technology • 84 pin PLCC • 100 pin LQFP

NCP1086D2T-33R4G

Vendor:ONPackage Cooled:0632D/C:7500

The RMBA19500 is a highly linear Power Amplifier. The circuit uses our pHEMT process. It has been designed for use as a driver stage for PCS base stations, or as the output stage for Micro- and Pico-Cell base stations. The amplifier has been optimized for high linearity requirements for CDMA operation.

NCP1086D2T-ADJR4

Vendor:N/APackage Cooled:N/AD/C:08+09+

The LCX240 is an inverting octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver. The device is designed for low voltage (2.5V or 3.3V) VCC appli- cations with capability of interfacing to a 5V signal environ- ment. The LCX240 is fabricated with an advanced CMOS tech- nology to achieve high speed operation while maintaini...

NCP1086ST-33T3

Vendor:ON

11.1 United States export laws and regulations prohibit the exportation of certain products or technical data received from DVSI under this Agreement to certain countries except under a special validated license. As of November 30, 1999 the restricted countries are: Libya, Cuba, North Korea, Iraq, Serbia, Taliban in Afghanistan, Sudan, Burma, Yugoslavia and Iran. The END USER hereby gives its assurance t...

NCP1086ST-33T3G

Vendor:ONPackage Cooled:SOT223D/C:08+

sFEATURES qLow Offset VoltageVIO=4mV max qSingle Low Power SupplyVDD=1.0~5.5V qWide Output Swing RangeVOM=2.9V min @ VDD=3.0V qLow Operating Current(See Line-up) qLow Bias CurrentIIB=1pA typ qCompensation Capacitor Incorporated qPackage OutlineSC88A qC-MOS Technology

NCP1086ST-ADJT3

Vendor:ON

The M28R400C is a 4 Mbit (256Kbit x 16) non-vol- atile Flash memory that can be erased electrically at the block level and programmed in-system on a Word-by-Word basis. These operations can be performed using a single low voltage (1.65 to 2.2V) supply. VDDQ allows to drive the I/O pin down to 1.65V. An optional 12V VPP power supply is provided to speed up customer programming. The device features a...

NCP1086ST-ADJT3

Vendor:ON

The M28R400C is a 4 Mbit (256Kbit x 16) non-vol- atile Flash memory that can be erased electrically at the block level and programmed in-system on a Word-by-Word basis. These operations can be performed using a single low voltage (1.65 to 2.2V) supply. VDDQ allows to drive the I/O pin down to 1.65V. An optional 12V VPP power supply is provided to speed up customer programming. The device features a...

NCP1086ST-ADJT3/086-A

NCP1086ST-ADJT3G/086-A

NCP1086T-033G

Vendor:ON

All outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2.0 ms, one output loaded at a time. Notes:1. IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC 2. VH=(VT+)-(VT-)

NCP1117DT12RK

Vendor:ONPackage Cooled:SOT252D/C:08+

Single 1.2-V to 3.6-V Supply Operation High Throughput C 200/240/280KSPS for 12/10/8-Bit VDD 1.6 V C 100/120/140KSPS for 12/10/8-Bit VDD 1.2 V 1.5LSB INL, 12-Bit NMC (ADS7866) 71 dB SNR, C83 dB THD at fIN = 30 kHz (ADS7866) Synchronized Conversion with SCLK SPI Compatible Serial Interface No Pipeline Delays Low Power C 1.39 mW Typ at 200 KSPS, VDD = 3.6 V C 0.39 mW Typ at 200 KSPS, VDD = 1.6 V C 0.22...

NCP1117DT15RKG

Vendor:N/APackage Cooled:N/AD/C:08+09+

This data sheet provides an overview of the R4700s CPU features and architecture. A more detailed description of this processor is provided in the IDT79R4700 RISC Processor Hardware Users Manual, available from Integrated Device Technology (IDT). Information on development support, applications notes and complementary products is available on the IDT Web site www.idt.com or through your local IDT sal...

NCP1117DT18RKG

Vendor:ONPackage Cooled:TO-252-2D/C:08+

The MC623 consists of a positive temperature coefficient (PTC) temperature sensor and dual threshold detector. Temperature set point programming is easily accomplished with external programming resistors from the HIGH SET and LOW SET inputs to VCC. The HIGH LIMIT and LOW LIMIT outputs remain inactive (low) as long as the measured temperature is below setpoint values. As temperature increases, the LOW ...

NCP1117DT18T5

Vendor:ONPackage Cooled:252D/C:06+

The PIC12C67X series fits perfectly in applications ranging from personal care appliances and security systems to low-power remote transmitters/receivers. The EPROM technology makes customizing applica- tion programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and conve- nient, while the EEPROM data memory (PIC12CE67X only) technology allows for the changing of ...

NCP1117DT18T5G

Vendor:ONPackage Cooled:TO-252D/C:07+

The 74LVC(H)32244A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 and 5 V environment.

NCP1117DT18T5G

Vendor:ONPackage Cooled:TO-252D/C:07+

The 74LVC(H)32244A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 and 5 V environment.

NCP1117DT20RK

Vendor:ON

The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable...

NCP1117DT25G

The SN74CBT16210C is organized as two 10-bit bus switches with separate output-enable (1OE, 2OE) inputs. It can be used as two 10-bit bus switches or as one 20-bit bus switch. When OE is low, the associated 10-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 10-bit bus switch is OFF, and the high-impedance stat...

NCP1117DT25RK

Vendor:OND/C:05+

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use pro- vided in the labeling, can be reasonably expected to result in a significant injury to the user.

NCP1117DT25RK

Vendor:OND/C:05+

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use pro- vided in the labeling, can be reasonably expected to result in a significant injury to the user.

NCP1117DT25RKG

Vendor:ONPackage Cooled:TO-252-2D/C:08+

Limits appearing in bold type face apply over the entire junction temperature range of operation, −40˚C to 125˚C. Specifications appearing in normal type apply for TA = TJ = 25˚C. Unless otherwise specified VIN =12V for the 3.3V, 5V and Adjustable versions and VIN =24V for the 12V version.

NCP1117DT285RK

Vendor:ONPackage Cooled:SOT252D/C:08+

The SM561 is a very simple and versatile device to use. The frequency and spread% range is selected by programming S0 and S1 digital inputs. These inputs use three (3) logic states including High (H), Low (L), and Middle (M) to select one of the

NCP1117DT285RK

Vendor:OND/C:08+

The SM561 is a very simple and versatile device to use. The frequency and spread% range is selected by programming S0 and S1 digital inputs. These inputs use three (3) logic states including High (H), Low (L), and Middle (M) to select one of the

NCP1117DT285RKG

Vendor:ONPackage Cooled:TO-252-2D/C:08+

(Reset) - The RST pin functions as a microprocessor reset signal. This pin is driven low 1) when VCC is outside of nominal limits; 2) when the watchdog timer has timed out; 3) during the power up reset period; and 4) in response to a pushbutton reset. The RST pin also functions as a pushbutton reset input. When the RST pin is driven low, the signal is debounced and timed such that a RST signal of...

NCP1117DT33RK

Vendor:ONPackage Cooled:TO252D/C:04+

Semelab Plc reserves the right to change test conditions, parameter limits and package dimensions without notice. Information furnished by Semelab is believed to be both accurate and reliable at the time of going to press. However Semelab assumes no responsibility for any errors or omissions discovered in its use. Semelab encourages customers to verify that datasheets are current before placing orders.

NCP1117DT-33RK

Vendor:ONPackage Cooled:223D/C:08+

Signal input pin. A internal matching circuit, configured with resistors, enables 50 Ω connec- tion over a wide band. A multi-feedback circuit is de- signed to cancel the deviations of hFE and resistance. This pin must be coupled to sig- nal source with capacitor for DC cut.

NCP1117DT33RKG

Vendor:ONSD/C:08+

Note 1. Commercial Product : TA=0 to 70C, unless otherwise specified Industrial Product : TA=-40 to 85C, unless otherwise specified 2. Overshoot : V CC+3.0V in case of pulse width30ns 3. Undershoot : -3.0V in case of pulse width30ns 4. Overshoot and undershoot are sampled, not 100% tested

NCP1117DT50

Vendor:ONPackage Cooled:TO-252D/C:08+

Note 3: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical on resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage the source (zero output impedance).

NCP1117DT50G

Vendor:ON

The Analog Ground terminal, pin 1, is shown internally connected to the non-inverting input of the op amp. This terminal connects to other internal circuitry and should be connected to ground. Approximately 200µA flows out of this terminal.

NCP1117DT50RK

Vendor:N/APackage Cooled:TO-252D/C:08+09+

Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Ioff and Power-Up 3-State Support Hot Insertion Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 − 2000-V Human...

NCP1117DT50RKG

Vendor:ONPackage Cooled:TO-252-2D/C:08+

• BuiltCin interface for PC/XT™/AT® or compatible busses • Interface to serial EEPROM for Node ID and configura- tion storage allows construction of jumperless, electroni- callyCconfigurable adapters • Automatic polarity correction on twistedCpair 10BASECT receive twistedCpair cable

NCP1117DT50RKG

Vendor:ONPackage Cooled:TO-252-2D/C:08+

• BuiltCin interface for PC/XT™/AT® or compatible busses • Interface to serial EEPROM for Node ID and configura- tion storage allows construction of jumperless, electroni- callyCconfigurable adapters • Automatic polarity correction on twistedCpair 10BASECT receive twistedCpair cable

NCP1117DTARK

Vendor:ONPackage Cooled:SOT-223D/C:08+

or Powered Down Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 4 Ω Typical) Rail-to-Rail Switching on Data I/O Ports − 0- to 5-V Switching With 3.3-V VCC − 0- to 3.3-V Switching With 2.5-V VCC Bidirectional Data Flow, With Near-Zero Propagation Delay Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 3.5 pF Typical) Fast...

NCP1117DTARK

Vendor:ONPackage Cooled:OT252D/C:08+

or Powered Down Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 4 Ω Typical) Rail-to-Rail Switching on Data I/O Ports − 0- to 5-V Switching With 3.3-V VCC − 0- to 3.3-V Switching With 2.5-V VCC Bidirectional Data Flow, With Near-Zero Propagation Delay Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 3.5 pF Typical) Fast...

NCP1117DTARKG

Vendor:ONPackage Cooled:633D/C:3000

GATE (Pin 1): MOSFET Gate Drive Pin. This pin is tied to the gate(s) of the external N-channel MOSFET(s). The GATE pin drives high when UV is above the VUV(TH) threshold, OV is below the VOV(TH) threshold and VIN is greater than OUT by 15mV. When not driven high, GATE actively pulls to GND. GATE can sink or source up to 600mA.

NCP1117H-ADJ-BR

Vendor:ONPackage Cooled:TO223D/C:03+

*Specifications same as ISO120BG, ISO121BG. NOTE: (1) Input voltage range = 10V for VS1, VS2 = 4.5VDC to 18VDC. (2) Ripple frequency is at carrier frequency. (3) Overload recovery is approximately three times the settling time for other values of C2. (4) The SG-grade is specified C55C to +125C; performance of the SG in the C25C to +85C temperature range is the same as the BG-grade.

NCP1117ST12T3

Vendor:ONPackage Cooled:SOT-223D/C:04+

micropackage. The HCC/HCF4000B, HCC/HCF4001B, HCC/HCF 4002B and HCC/HCF4025B nor gate provide the system designer with direct implementation of the nor function and supplement the existing family of COS/MOS gates. All inputs and outputs are buf- fered.