N74F139D

Selects Positive or Negative Edge Control and High or Low output drive strength. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference clock, respectively. When at MID level, the output drive strength is increased and the outputs synchronize with the positive edge of the reference clock (see Table 6).

N74F139D-T1

N74F139N

Vendor:PHPackage Cooled:05+D/C:2000

Features 1) Built-in bias resistors enable the configuration of an inverter circuit without connecting external input resistors. 2) The bias resistors consist of thin-film resistors with complete isolation to allow positive biasing of the input, and parasitic effects are almost completely eliminated. 3) Only the on / off conditions need to be set for operation, making device design easy. 4) Highe...

N74F14

Vendor:PHIPackage Cooled:SOP

1. Laser trimming of both initial accuracy and temperature coefficient results in very low errors over temperature without the use of external components. The AD581L has a maximum deviation from 10.000 volts of 7.25 mV from 0C to +70C, while the AD581U guarantees 15 mV maximum total error without external trims from C55C to +125C.

N74F148D

Vendor:PHILIPSPackage Cooled:SOPD/C:1998

Drain-to-Source Breakdown Voltage 500 Gate Threshold Voltage …2.0 Gate-to-Source Leakage Forward Gate-to-Source Leakage Reverse Zero Gate Voltage Drain Current Static Drain-to-Source … On-State Resistance One Diode Forward Voltage …

N74F148D

Vendor:PHILIPSPackage Cooled:SOPD/C:1998

Drain-to-Source Breakdown Voltage 500 Gate Threshold Voltage …2.0 Gate-to-Source Leakage Forward Gate-to-Source Leakage Reverse Zero Gate Voltage Drain Current Static Drain-to-Source … On-State Resistance One Diode Forward Voltage …

N74F14DJPL

Vendor:PHIPackage Cooled:SOP5.2mm-14LD/C:1990

The TS3702 is a micropower CMOS dual voltage comparator with extremely low consumption of 9µA typ / comparator (20 times less than bipolar LM393). The push-pull CMOS output stage allows power and space saving by eliminating the external pull-up resistor required by usual open-collector output comparators. Thus response times remain similar to the LM393.

N74F14N

Vendor:PHILIPSPackage Cooled:DIP-14D/C:96

The RS-232 port in most portable systems transmits and receives for only a small percentage of the time that power is applied; for the rest of the time it may waste power needlessly. An ideal RS-232 transceiver, therefore, should shut itself down when not transmitting or receiving.

N74F14N

Vendor:PHILIPSPackage Cooled:DIP-14D/C:96

The RS-232 port in most portable systems transmits and receives for only a small percentage of the time that power is applied; for the rest of the time it may waste power needlessly. An ideal RS-232 transceiver, therefore, should shut itself down when not transmitting or receiving.

N74F151A

Vendor:PHIPackage Cooled:3.9mm

The BAfffLBSG (the fff indicates the output voltage value) is a low-saturation series regulator IC employing the super-mini mold package of the SMP5 (2916 package). Equipped with a power-saving function that reduces current consumption, it also offers outstanding ripple rejection and other characteristics, and is ideal for cellular telephones and other compact telephones.

N74F153N

Vendor:ＮＸＰ

Chip Center: X=0µm, Y=0µm Chip Size: X=7.54mm, Y=2.09mm Chip Thickness: 400µm30µm Bump Size: 78.16µm x 48.10µm Pad Pitch: 70µm(Min.) Bump Height: 15µm(Typ.) Bump Material: Au Voltage boosting polarity : Negative Voltage(VDD Common) Substrate:N

N74F153N

Vendor:ＮＸＰ

Chip Center: X=0µm, Y=0µm Chip Size: X=7.54mm, Y=2.09mm Chip Thickness: 400µm30µm Bump Size: 78.16µm x 48.10µm Pad Pitch: 70µm(Min.) Bump Height: 15µm(Typ.) Bump Material: Au Voltage boosting polarity : Negative Voltage(VDD Common) Substrate:N

N74F154D

Vendor:PHILPD/C:984

The Am186ES/ESLV and Am188ES/ESLV microcontrollers have been designed to meet the most c om mo n r eq ui r e me nt s of e mb ed de d pr o du c ts developed for the office automation, mass storage, and communications markets. Specific applications include disk drives, hand-held and desktop terminals, set-top controllers, fax machines, printers, photocopiers, feature phones, cellular phones, PBXs, mult...

N74F157A

Vendor:A1Package Cooled:SOPD/C:99

(3) Static Electricity Static electricity or surge voltage damages the LEDs. It is recommended that a wrist band or an anti-electrostatic glove be used when handling the LEDs. All devices, equipment and machinery must be properly grounded. It is recommended that measures be taken against surge voltage to the equipment that mounts the LEDs. When inspecting the final products in which LEDs were assembl...

N74F157AD-T

D/C:1704

Systems using more than one converter for power management functions often face EMC problems. The reflected ripple at the inputs from these independent converters, which operate at different frequencies and phases, can create a wide frequency range of harmonics. Obviously, it is difficult, if not impossible, to eliminate all of these from the emission spectrum. The alternatives are to incorporate a he...

N74F157AD-T

Package Cooled:99D/C:1704

Systems using more than one converter for power management functions often face EMC problems. The reflected ripple at the inputs from these independent converters, which operate at different frequencies and phases, can create a wide frequency range of harmonics. Obviously, it is difficult, if not impossible, to eliminate all of these from the emission spectrum. The alternatives are to incorporate a he...

N74F157AN

Vendor:DIPPackage Cooled:PHID/C:00+

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli- able. However, no responsibility is assumed by Intersil...

N74F157N

Vendor:ＮＸＰ

Case: SOD-523, Plastic Case material - UL Flammability Rating Classification 94V-0 Moisture sensitivity: Level 1 per J-STD-020A Terminals: Finish - Matte Tin (Note 1) Solderable per MIL-STD-202, Method 208 Polarity: Cathode Band Marking Code: LM Weight: 0.002 grams (approx.)

N74F158D

Vendor:PHID/C:90

N74F158D

Vendor:PHID/C:90

N74F166D

Vendor:ＮＸＰ

DESCRIPTION The M74HC4017 is an high speed CMOS DECADE COUNTER/DIVIDER fabricated with silicon gate C2MOS technology. The M74HC4017 is a 5-stage Johnson counter with 10 decoded outputs. Each of the decoded outputs is normally low and sequentially goes high on the low to high transition of the clock input. Each output stays high for one clock period of the 10 clock period cycle. The CARRY output go...

N74F166HOUSE

N74F166N

When the R and V inputs are equal in frequency and the phase of R leads that of V the D output will stay HIGH while the U output pulses from HIGH to LOW. The magnitude of the pulse will be proportional to the phase difference between the V and R inputs reaching a minimum 50% duty cycle under a 180 out of phase condition. The signal on U indicates to the VCO to increase in frequency to bring the loop ...

N74F173

Vendor:PHILIPSPackage Cooled:SOP-16D/C:99+

N74F174D

3 4 COLLISION TRANSLATOR The Ethernet transceiver detects collisions on the coax ca- ble and generates a 10 MHz signal on the transceiver cable The SNIs collision translator asserts the collision detect output (COL) to the DP8390 controller when a 10 MHz sig- nal is present at the collision inputs The controller uses this signal to back off transmission and recycle itself The colli- sion detect output ...

N74F174DT

Vendor:PHIPackage Cooled:SOPD/C:99+

n 2.5 million pixels/s conversion rate n Implements Correlated Double Sampling for minimum noise and offset error n Pixel-to-pixel gain correction for individual pixels maximizes dynamic range and resolution, even on weak pixels n Reference and signal sampling points digitally controlled in 25ns increments for maximum performance n Generates all necessary CCD clock signals n Compatible with a wid...

N74F174N

Vendor:ＮＸＰ

The AD9878 is a single-supply, cable modem/set-top box, mixed-signal front end. The device contains a transmit path interpolation filter, a complete quadrature digital upconverter, and a transmit DAC. The receive path contains dual 12-bit ADCs and a 10-bit ADC. All internally required clocks and an output system clock are generated by the phase-locked loop (PLL) from a single crystal oscillator or cloc...

N74F175A

Vendor:PHIPackage Cooled:SMD-16

The RAMified Timekeeper provides full functional capability when VCC is greater than 4.5 volts and write-protects the register contents at 4.25 volts typical. Data is maintained in the absence of VCC without any additional support circuitry. The DS1386 constantly monitors VCC. Should the supply voltage decay, the RAMified Timekeeper will automatically write-protect itself and all inputs to the registers become...

N74F175AD

Vendor:PHIPackage Cooled:SOP3.9mm-16LD/C:1997

REFOUT is a 3.3V CMOS level non-modulated inverted copy of the clock at XIN/CLKIN. As an inverted clock, the output clock at REFOUT is 180 out of phase with the input clock at XIN/CLKIN. Placing a high(1) logic state of REFOFF, pin 2, will disable the REFOUT clock. When REFOUT is disabled, REFOUT, pin 3 is at a low(0) logic state.

N74F175D

Vendor:大SPackage Cooled:SOPD/C:07+

The transmitter consists of an integrated VCO and tank circuit, a complete integer-N synthesizer, and a power amplifier. The divider, prescaler, and reference oscillator require only the addition of an external crystal and a loop filter to provide a complete PLL with a typical frequency resolution of better than 200 kHz.

N74F175N

Notes: 1 Monitoring time is the time from the last pulse (negative edge) of the timer clear clock pulse until reset pulse output. In other words, reset output is output if a clock pulse is not input during this time. 2 Reset time means reset pulse width. However, this does not apply to power ON reset. 3 Reset hold time is the time from when VCC exceeds detection voltage (VSH) during power ON reset until ...

N74F175N

Notes: 1 Monitoring time is the time from the last pulse (negative edge) of the timer clear clock pulse until reset pulse output. In other words, reset output is output if a clock pulse is not input during this time. 2 Reset time means reset pulse width. However, this does not apply to power ON reset. 3 Reset hold time is the time from when VCC exceeds detection voltage (VSH) during power ON reset until ...

N74F1808D

Vendor:PHIPackage Cooled:SOP-20D/C:07+

The EUA5212 is a stereo audio power amplifier. When driving 1 W into 8-Ω speakers, the EUA5212 has less than 0.8% THD+N across its specified frequency range. Included within this device is integrated depop circuitry that virtually eliminates transients that cause noise in the speakers. Amplifier gain is internally configured and controlled by way of two terminals (GAIN0 and GAIN1). BTL gain setti...

N74F182N

DMAC (DMA controller) • 8 channels • Transfer factor : Interrupt request of built-in resources • Transfer sequence : Step transfer/Block transfer/Burst transfer/Consecutive transfer • Transfer data length : Selectable among 8 bits, 16 bits, and 32 bits • Pausing is allowed by interrupt request

N74F191

Vendor:TDAPackage Cooled:96+97+D/C:SOP

The JTAG emulation port of this device also includes two additional pins, EMU0 and EMU1, for global control of multiple processors conforming to the TI emulation standard. These pins are open collector-type outputs which are wire ORed and tied high with a pullup. Non-TI emulation devices should not be connected to these pins.

N74F191D

Vendor:PHIPackage Cooled:SOP3.9mm-16LD/C:2000

suspend feature while erasing a sector when you want to read data from a sector in the other plane. After the erase suspend command is given, the device requires a maxi- mum time of 15 µs to suspend the erase operation. After the erase operation has been suspended, the plane which contains the suspended sector enters the erase-suspend- read mode. The system can then read data or program data to...

N74F191D

Vendor:PHIPackage Cooled:SOP3.9mm-16LD/C:2000

suspend feature while erasing a sector when you want to read data from a sector in the other plane. After the erase suspend command is given, the device requires a maxi- mum time of 15 µs to suspend the erase operation. After the erase operation has been suspended, the plane which contains the suspended sector enters the erase-suspend- read mode. The system can then read data or program data to...

N74F191D-T

Vendor:ＮＸＰ

No-miss operation regardless of back-grounds Area reflective type sensor does not detect objects beyond the set range. Resistant to lens surface soiling Area reflective type sensor detects the distance by the angle, not the intensity of received light. Even if the lens sur- face is soiled by dust or any powdery material, there is a little variation of sensing range.

N74F193D

Vendor:PHIPackage Cooled:SOP3.9mm-16LD/C:1995

Integrated 4-band Graphic Equaliser Adjustable output stage filter compensation for different speakers Volume control on each channel +24dB to -103.5dB in 0.5dB steps, with volume ramping and auto-mute functions Programmable Dynamic Peak Compressor avoids clipping even at high volume settings Internal PLL and optional crystal oscillator, supporting Audio and MPEG standards 2/3-Wire MPU Serial Control Inte...

N74F193D

Vendor:PHIPackage Cooled:SOP3.9mm-16LD/C:1995

Integrated 4-band Graphic Equaliser Adjustable output stage filter compensation for different speakers Volume control on each channel +24dB to -103.5dB in 0.5dB steps, with volume ramping and auto-mute functions Programmable Dynamic Peak Compressor avoids clipping even at high volume settings Internal PLL and optional crystal oscillator, supporting Audio and MPEG standards 2/3-Wire MPU Serial Control Inte...

N74F193D-T

Vendor:ＮＸＰ

• Auto-Track™ Sequencing • Output Over-Current Protection (Non-Latching, Auto-Reset) • IPC Lead Free 2 • Safety Agency Approvals: UL 1950, CSA 22.2 950, EN60950 VDE (Pending) • Point-of-Load Alliance (POLA) Compatible

N74F193N

Vendor:PHILIPSPackage Cooled:DIPD/C:2002

1000:1 Dimming Range: The DIG_DIM input accepts a TTL or CMOS logic signal that controls duty cycle of the output currents. Independent Channels: The six channels feature independent regulation with respect to output voltage, so one does not affect the others. Any one or more outputs can be left unloadedwithoutaffectingcurrent regulation of the other channels. Multiple channels can also be conn...

N74F194D

Vendor:PHIPackage Cooled:SMDD/C:2000

The ARF Series EMI filter has been designed to pro- vide full compliance with the input line reflected ripple current requirement specified by CE03 of MIL-STD- 461C over the full military temperature range while operating in conjunction with the corresponding ART and ARH series of DC/DC converters. These filters are offered as part of a family of high reliability conversion products providing single,...

N74F195N-D

Package Cooled:87D/C:780

Members of the Texas Instruments Widebus ™ Family 3-State True Outputs Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise EPIC ™ (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125C Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Package Using 25-mil Center...

N74F20

N74F20D

Vendor:PHIPackage Cooled:SOP3.9mmD/C:2003

NOTES 1Measured at IOUTA, driving a virtual ground. 2Nominal full-scale current, I OUTFS, is 32 the I REF current. 3Use an external buffer amplifier to drive any external load. 4Reference bandwidth is a function of external cap at COMP1 pin. 5For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance. 6Measured at fCLOCK = 50 MSPS and fOU...

N74F2245DB

Vendor:PHILIPSPackage Cooled:SSOPD/C:08+

• Automatic use of UIM Resources C SMARTswitch The Universal Interconnect Maticx (UIM) used in Xilinx EPLDs provides an additional level of logic at no additional delay. XEPLD automatically uses the inherent logic capability of the UIM when possible to reduce Macrocell requirements and increase speed.

N74F240

Vendor:SD/C:91

The M28R400C is a 4 Mbit (256Kbit x 16) non-vol- atile Flash memory that can be erased electrically at the block level and programmed in-system on a Word-by-Word basis. These operations can be performed using a single low voltage (1.65 to 2.2V) supply. VDDQ allows to drive the I/O pin down to 1.65V. An optional 12V VPP power supply is provided to speed up customer programming. The device features a...

N74F240D

Vendor:PHIPackage Cooled:SOP7.2mm-20LD/C:1999

After Preset Mode inputs have been changed to one of the modes, the next positive-going clock transition changes an internal flip-flop so that the countdown can begin at the second positive-going clock transition. Thus, after an MP (Master Preset) mode, there is always one extra count before the output goes high. Figure 1 illustrates a total count of 3 (8 mode). If the Master Preset mode i...

N74F240D/T3

Vendor:ＮＸＰ

N74F240N

Vendor:PHID/C:2001

The N74F240N is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 32 bits, fabricated with SAMSUNGs high performance CMOS technol- ogy. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the sam...

N74F241D

Vendor:PHIPackage Cooled:SOP7.2mm-20LD/C:2000

*Serial Port: 16C550 UART-compatible RS-232 x 1 serial ports with 16-byte FIFO *Game Port: Supports one Joystick game port *USB: Four USB ports, two internal and two external *Keyboard: PS/2 6-pin Mini DIN *Mouse: PS/2 6-pin Mini DIN *BIOS: AMI PnP Flash BIOS *CMOS: Battery backup *Power Connector: One 20-pin ATX power connector *Temperature: 0~+60oC (operating) *Hardware Monitor: VIA VT82C686B *Dimens...

N74F243N

Vendor:PHIPackage Cooled:DIP-14D/C:9435

Program Memory Interface C Contains Pro- gram Counter (PC) and related logic. It per- forms the instructions code fetching. Program Memory can be also written. This feature al- lows usage of a small boot loader loading new program into RAM, EPROM or FLASH EEPROM storage via UART, SPI, I2C or DoCD™ module. Program fetch cycle length can be programmed by user. This feature is called Program Memory Wait...

N74F244D/T3

Vendor:ＮＸＰ

N74F244D623

Vendor:PHILIPSPackage Cooled:SMDD/C:08+

Internal Organization When ORG is connected to VDD or ORG is floated, the (´16) memory organi- zation is selected. When ORG is tied to VSS, the (´8) memory organization is selected. There is an internal pull-up resistor on the ORG pin. (HT93LC66-A)

N74F244DB

This hardware specification contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC885/MPC880 (refer to Table 1 for the list of devices). The MPC885 is the superset device of the MPC885/MPC880 family. The CPU on the MPC885/MPC880 is a 32-bit PowerPC™ core that incorporates memory management units (MMUs) and instruction and ...

N74F244DB

This hardware specification contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC885/MPC880 (refer to Table 1 for the list of devices). The MPC885 is the superset device of the MPC885/MPC880 family. The CPU on the MPC885/MPC880 is a 32-bit PowerPC™ core that incorporates memory management units (MMUs) and instruction and ...

N74F244N

Vendor:PHILIPSPackage Cooled:DIP-20D/C:97

NC = No Connect, RFU = Reserved for Future Use 1. RESET (Pin 18) is connected to both OE of PLL and Reset of register. 2. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs) 3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are for optional function to check address and command parity. 4. CKE1,S1 Pin is used for double side Registered DIMM.

N74F245

D/C:02

For the supply-voltage blocking capacitor C3 a value of 68 nF/X7R is recommended (see Figure 6 on page 6 and Figure 7 on page 7). C1 and C2 are used to match the loop antenna to the power amplifier where C1 typically is 8.2 pF/NP0 and C2 is 6 pF/NP0 (10 pF + 15 pF in series); for C2 two capacitors in series should be used to achieve a better tolerance value and to have the possibility to realize the ZLoa...

N74F245

D/C:02

For the supply-voltage blocking capacitor C3 a value of 68 nF/X7R is recommended (see Figure 6 on page 6 and Figure 7 on page 7). C1 and C2 are used to match the loop antenna to the power amplifier where C1 typically is 8.2 pF/NP0 and C2 is 6 pF/NP0 (10 pF + 15 pF in series); for C2 two capacitors in series should be used to achieve a better tolerance value and to have the possibility to realize the ZLoa...

N74F245DB

Vendor:PHIPackage Cooled:SSOPD/C:07+

The MCP1701 is capable of delivering 250 mA with an input-to-output voltage differential (dropout voltage) of 650 mV. The low dropout voltage extends the battery operating lifetime. It also permits high currents in small packages when operated with minimum VIN C VOUT differentials.

N74F245N

Vendor:PHIPackage Cooled:DIP-20D/C:2000

Parallel Mode Operation For latched parallel interfacing the LE line should be held low while changing attenuation state control logic P0.5 thru P16. To load data pulse LE from low to high and to low again. See Figure 1 and Table 1 on the next page for the parallel mode timing diagram and specifications. For direct parallel mode operation the LE line should be held high and the attenuation state is directly l...

N74F245N

Vendor:PHIPackage Cooled:DIP-20D/C:2000

Parallel Mode Operation For latched parallel interfacing the LE line should be held low while changing attenuation state control logic P0.5 thru P16. To load data pulse LE from low to high and to low again. See Figure 1 and Table 1 on the next page for the parallel mode timing diagram and specifications. For direct parallel mode operation the LE line should be held high and the attenuation state is directly l...

N74F253D

Vendor:PHPackage Cooled:SOPD/C:0519+

• Automatic use of UIM Resources C SMARTswitch The Universal Interconnect Maticx (UIM) used in Xilinx EPLDs provides an additional level of logic at no additional delay. XEPLD automatically uses the inherent logic capability of the UIM when possible to reduce Macrocell requirements and increase speed.

N74F258A

Vendor:PHIPackage Cooled:3.9mm

• 256 Resistor Taps • 2-Wire Serial Interface for write, read, and transfer operations of the potentiometer • Wiper Resistance, 100Ω typical @ 5V • 16 Nonvolatile Data Registers for Each Potentiometer • Nonvolatile Storage of Multiple Wiper Positions • Power On Recall. Loads Saved Wiper Position on Power Up. • Standby Current < 5µA Max • VC...

N74F258A

Vendor:PHIPackage Cooled:3.9mm

• 256 Resistor Taps • 2-Wire Serial Interface for write, read, and transfer operations of the potentiometer • Wiper Resistance, 100Ω typical @ 5V • 16 Nonvolatile Data Registers for Each Potentiometer • Nonvolatile Storage of Multiple Wiper Positions • Power On Recall. Loads Saved Wiper Position on Power Up. • Standby Current < 5µA Max • VC...

N74F269D602

In the normal mode, these devices are 18-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the b...

N74F27D

Vendor:PHILIPSPackage Cooled:SOPD/C:07+

FEATURES Schottky Barrier Chip Guard Ring Die Construction for Transient Protection Low Power Loss, High Efficiency High Surge Capability High Current Capability and Low Forward Voltage Drop For Use in Low Voltage, High Frequency Inverters, Free Wheeling, and Polarity Protection Applications

N74F280BD

Vendor:PHIPackage Cooled:95+D/C:2362

The W83877TF provides two high-speed serial communication ports (UARTs), one of which supports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability, and a processor interrupt system. One of the UARTs support infrared (IR) IrDA1.0. Both UARTs provide legacy speed with baud rate up to 115.2K and provide advanced sp...

N74F280BD

Vendor:PHIPackage Cooled:95+D/C:2362

The W83877TF provides two high-speed serial communication ports (UARTs), one of which supports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability, and a processor interrupt system. One of the UARTs support infrared (IR) IrDA1.0. Both UARTs provide legacy speed with baud rate up to 115.2K and provide advanced sp...

N74F299N

Vendor:PHPackage Cooled:539D/C:2150

Meets or Exceeds the Requirements of ANSI TIA/EIA-232-C Wide Range of Supply Voltage VCC = 4.5 V to 15 V Low Power . . . 117 mW (VCC = 9 V) Receiver Output TTL Compatible Response Control Provides: C Input Threshold Shifting C Input Noise Filtering

N74F30244D

Vendor:PHIPackage Cooled:02+D/C:864

N74F3037D512

N74F3037D-T

Vendor:PHIPackage Cooled:7.2mm

TAOperating free-air temperature−55125−4085C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

N74F3037N.602

N74F30D

Vendor:N/APackage Cooled:2500D/C:0027+

Dual pins: OUTPUTA, OUTPUTB, PVDDA1 and PVDDB1 must have both pins connected externally to the same point on the circuit board, respectively. Both PVSS pins must also be connected together externally. These multiple pins are for the high current DMOS output devices. Failure to connect all the multiple pins to the same respective node will result in excessive current flow in the internal bond wires and can ...

N74F30D

Vendor:N/AD/C:0027+

Dual pins: OUTPUTA, OUTPUTB, PVDDA1 and PVDDB1 must have both pins connected externally to the same point on the circuit board, respectively. Both PVSS pins must also be connected together externally. These multiple pins are for the high current DMOS output devices. Failure to connect all the multiple pins to the same respective node will result in excessive current flow in the internal bond wires and can ...

N74F30D-T

Vendor:PHIPackage Cooled:SOP3.9mm-14LD/C:1996

1.High isolation voltage between input and output (Viso=5000 Vrms). 2.Compact dual-in-line package KB817:1-channel type 3.Recognized by UL and CUL, file NO.E225308. 4.Approved by VDE 0884 Teil2(NO:40006364) (Creepage distance between input and output:7mm or more). 5.Rohs compliant.

N74F32DT

Vendor:availPackage Cooled:PHID/C:99/00+

When the output load exceeds the current-limit threshold or a short is present, the TPS203x limits the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OC) logic output low. When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermal protection circuit shuts off the sw...

N74F32DT SO-14

N74F32N

24-Bit Resolution Analog Performance: C Dynamic Range: 105 dB Typical C SNR: 105 dB Typical C THD+N: 0.002% Typical C Full-Scale Output: 3.9 Vp-p Typical 4/8 Oversampling Interpolation Filter: C Stop-Band Attenuation: C50 dB C Pass-Band Ripple: 0.04 dB Sampling Frequency: 5 kHz to 200 kHz System Clock: 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768 fS, or 1152 fS With Autodetect Zero Flags for Selectable C...

N74F32N

Package Cooled:PHILIPS

24-Bit Resolution Analog Performance: C Dynamic Range: 105 dB Typical C SNR: 105 dB Typical C THD+N: 0.002% Typical C Full-Scale Output: 3.9 Vp-p Typical 4/8 Oversampling Interpolation Filter: C Stop-Band Attenuation: C50 dB C Pass-Band Ripple: 0.04 dB Sampling Frequency: 5 kHz to 200 kHz System Clock: 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768 fS, or 1152 fS With Autodetect Zero Flags for Selectable C...

N74F365N

Vendor:ＮＸＰ

N74F367D

Vendor:SigPackage Cooled:92D/C:92

Notes: 1. Steady State Voltage Regulation includes Initial Voltage Setpoint, DC load regulation, outut ripple/noise and temperature drift. 2. These specifications assume a minimum of 20, 1µF ceramic capacitors are placed directly next to the CPU in order to provide adequate high-speed decoupling. For motherboard applications, the PCB layout must exhibit no more than 0.5m parasiticΩ resistance a...

N74F367N

(6) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage, and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failu...

N74F367N602

The CY2313ANZ is a 3.3V buffer designed to distribute high-speed clocks in desktop PC applications. The part has 13 outputs, 12 of which can be used to drive up to three SDRAM DIMMs, and the remaining can be used for external feedback to a PLL. The device operates at 3.3V and outputs can run up to 100 MHz, thus making it compatible with Pentium® II pro- cessors. The CY2313ANZ can be used in conjunc...

N74F373D.623

As seen in the block diagram, these encoders contain a single Light Emitting Diode (LED) as its light source. The light is collimated into a parallel beam by means of a single polycarbonate lens located directly over the LED. Opposite the emitter is the integrated detector circuit. This IC consists of multiple sets of photodetectors and the signal processing circuitry necessary to produce t...

N74F373N

Self Test allows to test the mechanical and electrical part of the sensor. By applying a digital signal to the ST input pin an internal reference is switched to a certain area of the sensor and creates a defined deflec- tion of the moveable structure. The sensor will generate a defined signal and the interface chip will perform the signal conditioning. If the output signal changes with the specified amplit...

N74F374

Vendor:PHIPackage Cooled:DIP-20D/C:1993

An internal oscillator fixes the switching frequency at 500KHz to minimize the size of external components. Having a minimum input voltage of 4.4V only, it is particularly suitable for 5V bus, available in all com- puter related applications. Pulse by pulse current limit with the internal frequen- cy modulation offers an effective constant current short circuit protection.

N74F374D

Vendor:PHIPackage Cooled:SOPD/C:2002

DESIGN CHANGES: ProTek reserves the right to discontinue product lines without notice, and that the final judgement concerning selection and specifications is the buyers and that in furnishing engineering and technical assistance, ProTek assumes no responsibility with respect to the selection or specifications of such products.

N74F374DB

Vendor:PHILIPSPackage Cooled:SSOPD/C:07+

C&D Technologies (NCL) Limited reserve the right to alter or improve the specification, internal design or manufacturing process at any time, without notice. Please check with your supplier or visit our web site to ensure that you have the current and complete specification for your product before use.

N74F377

Package Cooled:90D/C:DIP

N74F377N

Vendor:PHILPackage Cooled:DIPD/C:08+

NOTES: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

N74F377N

Vendor:PHILPackage Cooled:DIPD/C:08+

NOTES: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

N74F37D-T N74F37D-T N74F37DT

N74F37N.602 N74F37N.602 N74F37N602

N74F38 N74F38 N74F38

N74F381N

Vendor:PHIPackage Cooled:DIP-20D/C:9514

c) Before using the PCB at full power or at- tempting a short circuit test, make sure that a proper high voltage electroytic capacitor is connected between DC BUS and GND as shown in Figure 4. The leads to this capacitor should be as short as possible to minimize any stray inductance.

N74F382N N74F382N N74F382N

N74F382N-SIG-DN N74F382N-SIG-DN N74F382NSIGDN