Index "O"Vendor:ADPackage Cooled:SMD D/C:97+
A reduction in video noise is achieved by correlating the picture contents of two successive fields, the non-correlated components (noise) being attenuated by the digital filter. To achieve this, the instantaneous digital picture signal on the outputs of the demultiplexer DEMUXS and the picture signal delayed by a field interval on the outputs of the back-channel demultiplexer DEMUXR are fed to the IIP a...
Vendor:AD
Data transmission for the DPSK mode requires that data ultimately be transmitted in a synchronous fashion. The 73K322L includes ASYNC/SYNC and SYNC/ASYNC converters which delete or insert stop bits in order to transmit data at a regular rate. In Asynchronous mode the serial data comes from the TXD pin into the ASYNC/SYNC converter. The ASYNC/SYNC converter accepts the data provided on the TXD pin which norm...
Vendor:PMID/C:00+
Vendor:23D/C:N/A
!Features 1) Built-in bias resistors enable the configuration of an inverter circuit without connecting external input resistors (see equivalent circuit). 2) The bias resistors consist of thin-film resistors with complete isolation to allow negative biasing of the input. They also have the advantage of almost completely eliminating parasitic effects. 3) Only the on/off conditions need to be set fo...
Vendor:ADIPackage Cooled:N/AD/C:04+
The VSP2272 device is a complete mixed-signal processing IC for digital cameras providing signal conditioning and analog-to-digital conversion for the output of a charge-coupled device (CCD) array. The primary CCD channel provides correlated double sampling (CDS) to extract the video information from the pixels, C6-dB to 42-dB gain range with digital control for varying illumination conditions, and b...
Vendor:ADID/C:04+
The VSP2272 device is a complete mixed-signal processing IC for digital cameras providing signal conditioning and analog-to-digital conversion for the output of a charge-coupled device (CCD) array. The primary CCD channel provides correlated double sampling (CDS) to extract the video information from the pixels, C6-dB to 42-dB gain range with digital control for varying illumination conditions, and b...
Vendor:ANALOGDEVICESD/C:08+
The S1117 series of positive adjustable and fixed regulators are designed to provide 1A with high efficiency. All internal circuitry is designed to operate down to 1.3V input to output differential. On-chip trimming adjusts reference voltage to 2%.
Package Cooled:DIPD/C:99+
Vendor:ADID/C:05+
Surface mount equivalent to 1N4728 to 1N4764A Ideal for high-density and low-profile mounting Zener voltage available 3.3V to 200V Standard voltage tolerances are plus/minus 5% with A suffix and 10 % with no suffix identification Tight tolerances available in plus or minus 2% or 1% with C or D suffix respectively Options for screening in accordance with MIL-PRF- 19500 for JAN, JANTX, JANTXV, and JANS ar...
Vendor:ADIPackage Cooled:DIPD/C:05+
The oscillator is tuned internally, requiring only an external fixed LC tank and is optimised for high linearity over the normal deviation range. Typical frequency versus video drive voltage response for the oscillator is shown in Fig. 8. This response was measured with a modulated carrier. The compensated oscillator temperature stability is typically 0.05MHz/C. The gain of the oscillator is nominall...
Vendor:ADID/C:05+
The oscillator is tuned internally, requiring only an external fixed LC tank and is optimised for high linearity over the normal deviation range. Typical frequency versus video drive voltage response for the oscillator is shown in Fig. 8. This response was measured with a modulated carrier. The compensated oscillator temperature stability is typically 0.05MHz/C. The gain of the oscillator is nominall...
Vendor:CDIPPackage Cooled:1048D/C:AD
Flexible Logic Resources - Up to 93,184 internal registers / latches with Clock Enable - Up to 93,184 look-up tables (LUTs) or cascadable 16-bit shift registers - Wide multiplexers and wide-input function support - Horizontal cascade chain and Sum-of-Products support - Internal 3-state bussing
Vendor:CDIPPackage Cooled:1365D/C:AD
Notes: (1) See SOA curves or consult factory for appropriate derating. (2) The set-point voltage tolerance is affected by the tolerance and stability ofRSET. The stated limit is unconditionally met if RSET has a tolerance of 1 % with 100 ppm/C or better temperature stability. (3) The Inhibit control (pin 3) has an internal pull-up to Vin, and if left open-circuit the module will operate when input pow...
Vendor:CDIPPackage Cooled:1365D/C:AD
Notes: (1) See SOA curves or consult factory for appropriate derating. (2) The set-point voltage tolerance is affected by the tolerance and stability ofRSET. The stated limit is unconditionally met if RSET has a tolerance of 1 % with 100 ppm/C or better temperature stability. (3) The Inhibit control (pin 3) has an internal pull-up to Vin, and if left open-circuit the module will operate when input pow...
Vendor:SOPD/C:99+
The Hyundai HYM71V32S755AT4 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 256Mbytes memory. The Hyundai HYM71V32S755AT4 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.
Vendor:SOPD/C:99+
The Hyundai HYM71V32S755AT4 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 256Mbytes memory. The Hyundai HYM71V32S755AT4 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.
Vendor:AD
to that code position, and there is no need to replicate this information in the sub-repertoire definition. At present, a request to ISO/IEC JTC 1/SC 2 (which will be assigned to ISO/IEC SC 2/WG 2) to issue a collection identifier and enter that into the Annex A of the standard is all that is needed to identify such a sub-repertoire.
Vendor:ADIPackage Cooled:DIPD/C:08+
262,144-word by 8-bit CMOS static RAM. The IS61LV2568 is fabricated using ISSI's high-performance CMOS tech- nology. This highly reliable process coupled with innova- tive circuit design techniques, yields higher performance and low power consumption devices.
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.03 / Aug.01Hynix Semiconductor
Vendor:ADID/C:08+
Negative supply pin. Active high output enable. When logic HIGH, the outputs are enabled and active. When logic LOW, the outputs are disabled and are in a high impedance state. LVCMOS/LVTTL interface levels. Differential clock outputs. LVPECL interface levels.
Vendor:ADID/C:05+
4.3 Screening (JANTX and JANTXV levels only). Screening shall be in accordance with table IV of MIL-PRF-19500 and as specified herein. The following measurements shall be made in accordance with table I herein. Devices that exceed the limits of table I herein shall not be acceptable.
Vendor:ADID/C:05+
There is little to be gained from choosing resistor R2 values below 400Ω and, in fact, it would only result in increased power dissipation and signal distortion. Above 400Ω, the bandwidth response will develop some peaking (for a gain of two), but substantially higher resistor R2 values may be used for higher voltage gains, such as up to 2kΩ at a gain of eight before peaking will deve...
Vendor:ADID/C:05+
There is little to be gained from choosing resistor R2 values below 400Ω and, in fact, it would only result in increased power dissipation and signal distortion. Above 400Ω, the bandwidth response will develop some peaking (for a gain of two), but substantially higher resistor R2 values may be used for higher voltage gains, such as up to 2kΩ at a gain of eight before peaking will deve...
Vendor:AD
Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor package must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to
Vendor:ADPackage Cooled:DIP条仔
1 Gbit/sec, 100 MBytes/sec, each direction w/full duplex support Up to 1024 bytes Arbitrated Loop, Public & Private, and N_Port Fabric attachment Class 3 and Class 2 (via software) FCP C On-chip automation for complete SCSI I/O Completely hardware-based for high availability Loop map, loop-directed reset, loop broadcast, loop port bypass Four via on-chip buffers 10-bit Interface Link status i...
D/C:08+
Integrated tracking capacitor Senses motion of ring magnet or ferrous targets Wide operating temperature range Operation with frequency of sensed transitions from 20 Hz to 30 kHz EMI/ESD-resistant Large effective air gaps 4.0 to 26.5 V operating range Output compatible with both TTL and CMOS logic families Reverse battery protection Resistant to mechanical and thermal stress
Package Cooled:ADID/C:08+
Integrated tracking capacitor Senses motion of ring magnet or ferrous targets Wide operating temperature range Operation with frequency of sensed transitions from 20 Hz to 30 kHz EMI/ESD-resistant Large effective air gaps 4.0 to 26.5 V operating range Output compatible with both TTL and CMOS logic families Reverse battery protection Resistant to mechanical and thermal stress
Vendor:N/APackage Cooled:N/AD/C:08+09+
and 4 to 40 V Low current consumption of less than 0.8 mA Integrated output stage for up to 60 mA output current Short-circuit and overload protection of output stages and external components Temperature response of the IC compensates that of the coil High noise immunity High switching frequencies up to 5 kHz Useful extra functions Suitable for two-wire AC proximity switches Temperature range C 40 to 11...
Vendor:ADD/C:99+
The Intel 87C51 80C51BH 80C31BH is a single-chip control-oriented microcontroller which is fabricated on Intels reliable CHMOS III-E technology Being a member of the MCS 51 controller family the 87C51 80C51BH 80C31BH uses the same powerful instruction set has the same architecture and is pin-for- pin compatible with the existing MCS 51 controller family of products
Vendor:ADID/C:08+
Vendor:ADID/C:08+
Vendor:ADID/C:08+
Vendor:CDIPPackage Cooled:1048D/C:AD
the rise section of the signal be expressed accurately with respect to the original sound. However, there is inevitable mismatching between the speakers and amplifiers in current audio systems. Solid- state power amplifiers use negative feedback techniques and operate off a fixed voltage supply, but as speakers are a current element, mismatching in the system inevit- ably occurs. In addition, the spe...
Vendor:CDIPPackage Cooled:1048D/C:AD
the rise section of the signal be expressed accurately with respect to the original sound. However, there is inevitable mismatching between the speakers and amplifiers in current audio systems. Solid- state power amplifiers use negative feedback techniques and operate off a fixed voltage supply, but as speakers are a current element, mismatching in the system inevit- ably occurs. In addition, the spe...
Vendor:CDIPPackage Cooled:DIPD/C:AD
I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it is an input con- trol signal used by the CPU to load information into the 82C37A. In the Active cycle, it is an output control signal used by the 82C37A to load data to the peripheral during a DMA Read transfer.
Vendor:HARRISPackage Cooled:LCCD/C:92+
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Elec- trical Characteristics state DC and AC electrical specifications under particu- lar test conditions which guarantee specific performance limits. This assumes that the device is within...
Vendor:ADPackage Cooled:DIP-14D/C:439
Full I2C multiple Master/Slave Interface supporting ACCESS BUS Rich Instruction Set with 14 Addressing Modes Division-by-zero trap generation VersatileDevelopment Tools, including Assembler, Linker, C-Compiler, Archiver, Source Level Debugger, Hardware Emulators and Real Time Operating System
Vendor:ADPackage Cooled:DIP-14D/C:439
Full I2C multiple Master/Slave Interface supporting ACCESS BUS Rich Instruction Set with 14 Addressing Modes Division-by-zero trap generation VersatileDevelopment Tools, including Assembler, Linker, C-Compiler, Archiver, Source Level Debugger, Hardware Emulators and Real Time Operating System
Vendor:ADIPackage Cooled:DIPD/C:07+
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
Vendor:PMIPackage Cooled:CDIP14D/C:8839
3. Measured by the voltage drop between A and B pins at the indicated current through the switch. On Resistance is determined by the lower of the voltages on the two (A or B Ports). 4. Parameter is characterized but not tested in production. 5. DRON = RON max − RON min measured at identical VCC, temperature and voltage levels. 6. Flatness is defined as the difference between the maximum and minimum...
Vendor:ADID/C:06+
An Intel 8254 timer-counter (or functionally equivalent device) generates the software clock. This timer-counter generates an interrupt every 54.936 milliseconds, or about 18.2 times per second. The PC BIOS (basic input output system) contains a software routine that counts the interrupt requests and generates a time-of-day clock that can be read or set by other software programs. For example, the operating...
Vendor:ADID/C:06+
Vendor:ADIPackage Cooled:DIPD/C:08+
4 channel 10-bit resolution A/D conversion time : 15.2 µs (MB89965, MB89P965A, MB89F969A) 13.2 µs (MB89PV960) Continuous activation is available using the output from the 8/16-bit timer/counter or timebase timer. Reference voltage input (AVR)
Vendor:DIP14Package Cooled:315D/C:AD
The IP4001S has a thermal protection against the abnormal operation. When the junction temperature rises above 175OC, and channel drivers are muted. This makes the junction temperature be continuously decreased. When the junction temperature falls below 150OC, all channel operature again.
Vendor:DIP14Package Cooled:315D/C:AD
The IP4001S has a thermal protection against the abnormal operation. When the junction temperature rises above 175OC, and channel drivers are muted. This makes the junction temperature be continuously decreased. When the junction temperature falls below 150OC, all channel operature again.
Vendor:DIP14Package Cooled:DIPD/C:AD
As the SI pulse is clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a charge- coupled output amplifier that generates a voltage on the analog output AO. Two dummy pixel values are shifted out first, then the 128 actual pixel bits, followed by two additional dummy pixel bits, for a total of 132 data bits. Although there are only 132 pixels, 133 clo...
Vendor:DIP14Package Cooled:328D/C:AD
As the SI pulse is clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a charge- coupled output amplifier that generates a voltage on the analog output AO. Two dummy pixel values are shifted out first, then the 128 actual pixel bits, followed by two additional dummy pixel bits, for a total of 132 data bits. Although there are only 132 pixels, 133 clo...
Vendor:ADID/C:05+
Internally generated bias voltage of approximately VDD /2, except when the device is in Powersave mode when VBIAS will discharge to VSS. Should be decoupled to VSS by a capacitor mounted close to the device pins. The inverted output of the Tx Output Buffer.
Vendor:ADID/C:05+
Internally generated bias voltage of approximately VDD /2, except when the device is in Powersave mode when VBIAS will discharge to VSS. Should be decoupled to VSS by a capacitor mounted close to the device pins. The inverted output of the Tx Output Buffer.
The transmission of ADSL/HDSL signals requires very low distortion amplification, so this amplifier was designed with this as a primary goal. The actual signal distortion levels depend upon input and output signal amplitude, as well as the output load impedance. (See distortion data inside.)
Vendor:AD
The ILD205T/ 206T/ 207T/ 211T/ 213T/ 217T are optically coupled pairs with a Gallium Arsenide infra- red LED and a silicon NPN phototransistor. Signal information, including a DC level, can be transmitted by the device while maintaining a high degree of elec- trical isolation between input and output. The ILD205T/ 206T/ 207T/ 211T/ 213T/ 217T come in a standard SOIC-8A small outline package for surfa...
Vendor:PMIPackage Cooled:DIP/14
The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177C189C. ...
Vendor:N/APackage Cooled:adD/C:08+09+
(Note 9) (Continued) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 kSPS to 500 kSPS, CL = 35 pF unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C.
An enhanced, multiple cell security scheme is provided that prevents reading of the JEDEC programming file when secured. After the device has been secured using this mechanism, the only way to clear the security is to execute a bulk-erase instruction.
Vendor:ADD/C:2008
− 170 Mbps (1.2 V 3 (VCCA or VCCB) 3 3.3 V) − 320 Mbps (1.8 V 3 (VCCA or VCCB) 3 3.3 V) Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 − 8000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101)
Vendor:ADIPackage Cooled:SOP-16D/C:500
Vendor:ADID/C:08+
Xilinx introduces the XC1800 series of in-system program- mable configuration PROMs. Initial devices in this 3.3V family are a 4 megabit, a 2 megabit, a 1 megabit, a 512 Kbit, a 256 Kbit, and a 128 Kbit PROM that provide an easy-to-use, cost-effective method for re-programming and storing large Xilinx FPGA or CPLD configuration bit- streams.
Vendor:ADIPackage Cooled:DIPD/C:0910
Vendor:ADID/C:0910
Vendor:OPPackage Cooled:DIP
• Small, space-saving fuses provide a high degree of current limitation on short-circuits for excellent component protection. • Commonly applied in electric heat circuits, load center, disconnect switches, and meters. • The small size of the T-Tron fuses permits installation in panelboards and control centers for system upgrading when existing circuit breakers cannot safely interrupt ...