OPA37BJ/883

Vendor:BBD/C:08+

FEATURES 16 16 High Speed Nonblocking Switch Array Serial or Parallel Programming of Switch Array Serial Data Out Allows Daisy Chaining Control of Multiple 16 16s to Create Larger Switch Arrays Output Disable Allows Connection of Multiple Devices without Loading the Output Bus Complete Solution Buffered Inputs 16 Output Amplifiers Operates on 5 V or 12 V Supplies Low Supply Current of 54 mA E...

OPA37BJ/883

Vendor:BBD/C:08+

FEATURES 16 16 High Speed Nonblocking Switch Array Serial or Parallel Programming of Switch Array Serial Data Out Allows Daisy Chaining Control of Multiple 16 16s to Create Larger Switch Arrays Output Disable Allows Connection of Multiple Devices without Loading the Output Bus Complete Solution Buffered Inputs 16 Output Amplifiers Operates on 5 V or 12 V Supplies Low Supply Current of 54 mA E...

OPA37BM

Vendor:BBD/C:07+

(1) Lead Forming When forming leads, the leads should be bent at a point at least 3mm from the base of the epoxy bulb. Do not use the base of the leadframe as a fulcrum during lead forming. Lead forming should be done before soldering. Do not apply any bending stress to the base of the lead. The stress to the base may damage the BG-LEDs characteristics or it may break the BG-LEDs. When mounting the...

OPA37CM

Vendor:BBPackage Cooled:CAN

The UC3854A/B products are pin compatible enhanced versions of the UC3854. Like the UC3854, these products provide all of the functions necessary for active power factor corrected preregulators. The controller achieves near unity power factor by shaping the AC input line current waveform to correspond to the AC input line voltage. To do this the UC3854A/B uses average current mode control. Average ...

OPA37EJ

Vendor:BBPackage Cooled:CAN8

• Bidirectional data strobe(DQS) • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • Programmable Read latency 2, 2.5 (clock) • Programmable Burst length (2, 4, 8) • Programmable Burst type (sequential & interleave) • Edge aligned data output, center aligned data input • Auto & Self refresh, 7.8us refresh inter...

OPA37EZ

Vendor:1Package Cooled:CDIP8D/C:N/A

RC: RC is the oscillator timing pin. For fixed frequency operation, set timing capacitor charging current by con- necting a resistor from REF to RC. Set frequency by con- necting a timing capacitor from RC to GND. For best performance, keep the timing capacitor lead to GND as short and direct as possible. If possible, use separate ground traces for the timing capacitor and all other func- tions.

OPA37EZ/FZ

Vendor:BB

The four documents listed in Table 1 are required for a complete description and proper design with the DSP56F801. Documentation is available from local Motorola distributors, Motorola semiconductor sales offices, Motorola Literature Distribution Centers, or online at www.motorola.com/semiconductors/dsp.

OPA37G

Vendor:BBPackage Cooled:STKD/C:2005+

OPA37GP

Vendor:BBPackage Cooled:DIP8

The crystal-based architecture of the MAX7044 elimi- nates many of the common problems with SAW-based transmitters by providing greater modulation depth, faster frequency settling, higher tolerance of the trans- mit frequency, and reduced temperature dependence. The MAX7044 also features a low supply voltage of +2.1V to +3.6V. These improvements enable better overall receiver performance when using the MAX70...

OPA37GPG4

Vendor:TIPackage Cooled:DIP8D/C:05+

Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider when S_LOAD tran- sitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input ...

OPA37GU/2K5

Vendor:4162

Measuring Diode Parameters The measurement of the five elements which make up the equivalent circuit for a packaged Schottky diode (see Figure 10) is a complex task. Various techniques are used for each element. The task begins with the elements of the diode chip itself.

OPA37GU/2K5G4

Vendor:TID/C:05+

Absolute Maximum Ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Exposure of the device to the absolute maximum ratings for extended period may degrade the device and effect its reliability.

OPA37GUE4

Vendor:3691

OPA37GZ

Vendor:availPackage Cooled:BBD/C:04+

HY57V56820T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

OPA37J

Vendor:BBPackage Cooled:CAN8

1-5ms Power Good (PG) control signal Regulated 1.2V output 150mA output current Low quiescent operating current (90µA typical) "Zero" disable mode current Foldback current limiting protection Thermal shutdown protection Stable with low-ESR capacitors SOT23-5 package "MIC5258" pinout Lead-free version available

OPA37LM

Vendor:BBPackage Cooled:CAN

Low Supply Current: 1.5µA Max Rail-to-Rail Input and Output Low Offset Voltage: 375µV Max Wide Supply Range: 2.2V to 36V Single Supply Input Range: C 0.3V to 36V Low Input Bias Current: 250pA Low Input Offset Current: 20pA High AVOL: 100V/mV Minimum Driving 100kΩ Load Output Sources and Sinks 500µA Load Current Reverse Battery Protected to 18V

OPA37U

Vendor:BBD/C:05+

Gain Drift is a measure of the change in the full scale range output over temperature expressed in parts per million per C (ppm/C). Gain drift is established by: 1) testing the end point differences for each DAC80 model at 0C, +25C, and +70C; 2) calculating the gain error with respect to the 25C value, and; 3) dividing by the temperature change. This figure is expressed in ppm/C and is given in the ele...

OPA37UA

Vendor:BBPackage Cooled:SOP8D/C:05+

OPA380A

Vendor:BBPackage Cooled:SOP8D/C:06+

The Edge646 supports an on-board window comparator. CVB and CVA are high impedance analog inputs which establish the threshold voltages. COMPA and COMPB are the digital outputs which reflect the real time status of VINP Table 2 summarizes the relationship between the. threshold levels, VINP and the output signals.,

OPA380A

Vendor:BBPackage Cooled:SOPD/C:06+

The Edge646 supports an on-board window comparator. CVB and CVA are high impedance analog inputs which establish the threshold voltages. COMPA and COMPB are the digital outputs which reflect the real time status of VINP Table 2 summarizes the relationship between the. threshold levels, VINP and the output signals.,

OPA380AID

Direct interface to high voltage display Serial data input No external resistors required Wide display power supply operation LSTTL compatible inputs Software compatible with NS display driver family Compatible with alphanumeric or dot matrix displays Display blanking control input Simple to cascade

OPA380AID

Direct interface to high voltage display Serial data input No external resistors required Wide display power supply operation LSTTL compatible inputs Software compatible with NS display driver family Compatible with alphanumeric or dot matrix displays Display blanking control input Simple to cascade

OPA380AIDGKRG4

Vendor:TI/BBPackage Cooled:MSOP8D/C:0740+

The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be individually configured as an input, output or for bi-directional operation. The output enable for each macrocell can be selected from the true or compliment of the two output enable pins, a subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done by the fitter software when the I/O...

OPA380AIDGKT

The LS395 contains four D-type edge-triggered flip-flops and auxiliary gating to select a D input either from a Parallel (Pn) input or from the preceding stage When the Select input is HIGH the Pn inputs are enabled A LOW signal in the S input enables the serial inputs for shift-right opera- tions as indicated in the Truth Table State changes are initiated by HIGH-to-LOW transitions on the Clock Pulse (C...

OPA380AIDGKT

Package Cooled:MSOP-8

The LS395 contains four D-type edge-triggered flip-flops and auxiliary gating to select a D input either from a Parallel (Pn) input or from the preceding stage When the Select input is HIGH the Pn inputs are enabled A LOW signal in the S input enables the serial inputs for shift-right opera- tions as indicated in the Truth Table State changes are initiated by HIGH-to-LOW transitions on the Clock Pulse (C...

OPA380AIDR

Vendor:BB/TIPackage Cooled:SOP8D/C:04+

The Freescale manuals are available on the Freescale Semiconductors Web site at http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web site, or printed versions may be ordered. The ARM Ltd. documentation is available from http://www.arm.com.

OPA381AIDGKR

Vendor:TID/C:08+

The transmitter portion of the chip receives TTL compatible signals and transmits a corresponding bipolar data stream down the line (See Figure 5). TPOS and TNEG are TTL compatible signals that dictate the polarity of the pulse to be generated and transmitted on the output bipolar data stream. Both TPOS and TNEG inputs are sampled by the rising edge of the transmit clock, TCLK. The TX DATA(+) and TX ...

OPA381AIDRBR

Vendor:TID/C:08+

Adjustable flashing speed Adjustable detection voltage supports all settings Adjustable hysteresis voltage enables response to large ripple settings High precision voltage detection (MM1253) enables support of sets using nickel cadmium and other batteries 5. The LED can be lit up by the voltage from one battery (type of special built-in step-up circuit : rank B)

OPA3832ID

The PCA9544A is a quad bidirectional translating switch controlled via the I2C bus. The SCL/SDA upstream pair fans out to four downstream pairs, or channels. One SCL/SDA pair can be selected at a time, and this is determined by the contents of the programmable control register. Four interrupt inputs (INT3CINT0), one for each of the downstream pairs, are provided. One interrupt output (INT) acts as an AND ...

OPA3832IPWG4

OPA3862E

Vendor:MAXPackage Cooled:SSOP16D/C:06+

OPA3875IDBQG4

OPA404

Vendor:30Package Cooled:SOP/DIP

NOTES: 1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions. 2. 1082mV LVEPECL (2.5V) and 1880mV LVPECL (3.3V) crossing point levels are specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Thi...

OPA404AP

Vendor:BB/TIPackage Cooled:07+

OPA404AU

Vendor:BBPackage Cooled:06+D/C:800

• Array Format: 1,280H x 1,024 V (1,310,720 pixels) • Pixel Size and Type: 12.0µm x 12.0µm TrueSNAP (shuttered-node active pixel) • Sensor Imaging Area: H: 15.36mm, V: 12.29mm, Diagonal: 19.67mm • Frame Rate: 0C500+ fps @ (1,280 x 1,024), >10,000 fps with partial scan, [e.g. 0C4000 fps @ (1,280 x 128)] • Output Data Rate: 660 Mbs (master clock 66 MHz, ~...

OPA404JG

Vendor:DIPPackage Cooled:121

OPA404JU

Vendor:BBPackage Cooled:SOP

OPA404KP

Vendor:100Package Cooled:BB/TID/C:N/A

• Three 3V66 clocks (66.6 MHz, 3.3V) ICH, HUBLINK, and AGP memory • One selectable frequency for VCH video channel clock (48-MHz non-SSCG, 66.6-MHz CPU-SSCG, 3.3V) • Power management using power-down, CPU stop, and PCI stop pins • Three function select pins (include test-mode select) • Cypress Spread Spectrum for best electromagnetic interference (EMI) reduction • S...

OPA404KPG4

Vendor:BB/TIPackage Cooled:DIP14D/C:05+

FEATURES ! Drives wide range of n-channel MOSFETs in 3-phase bridges ! PFM boost converter for use with low-voltage battery supplies ! Internal LDO regulator for gate-driver supply ! Bootstrap circuits for high-side gate drivers ! Current monitor output ! Adjustable battery overvoltage detection. ! Diagnostic outputs

OPA404KU/1K

Vendor:BBD/C:2008+

In the external oscillator mode the external source is connected to pin EXTDR and pin RC is short-circuited to pin SGND to disable the internal oscillator. If the internal divider is disabled (pin DD = VDD) the duty factor of the bridge output signal is determined by the external oscillator signal and the bridge frequency equals the external oscillator frequency.

OPA404KUG4

Vendor:TIPackage Cooled:SOP16D/C:05+

8-Bit Resolution 25MHz Conversion Rate 60MHz 3dB Analog Input Bandwidth Single +5V Supply Operation Low Power Consumption (Typically 670mW) +3V to +5V Analog Input Range Selectable Data Format TTL Compatible Direct Replacement for TDC 1058 or CXA 1096P Low Cost No Missing Codes - Guaranteed

OPA404TG

Vendor:100Package Cooled:N/AD/C:N/A

OPA404UA

Vendor:BBPackage Cooled:SOP16D/C:N/A

OPA410CA

Vendor:2Package Cooled:OKID/C:N/A

Figure 1 shows a typical battery pack application of the bq2014 using the LED display capability as a charge- state indicator. The bq2014 is configured to display ca- pacity in a relative display mode. The relative display mode uses the last measured discharge capacity of the battery as the battery full reference. The LED seg- ments output a percentage of the available charge based on NAC and LMD. A push-but...

OPA4130P

Vendor:BBPackage Cooled:2005D/C:500

OPA4130UA/2K5

Vendor:BB/TIPackage Cooled:SOP14D/C:04+

Clock: CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing).

OPA4130UA/2K5E4

Vendor:BB/TIPackage Cooled:SOP14D/C:06+

Aperture Delay (ta). The average (or mean value) of the delay between the hold command (input clock switched from track to hold state) and the instant at which the analog input is sampled. The time is positive if the clock path delay is longer than the signal path delay. It is negative if the signal path delay is longer than the clock path delay.

OPA4130UA/2K5E4

Vendor:BB/TIPackage Cooled:SOP14D/C:06+

Aperture Delay (ta). The average (or mean value) of the delay between the hold command (input clock switched from track to hold state) and the instant at which the analog input is sampled. The time is positive if the clock path delay is longer than the signal path delay. It is negative if the signal path delay is longer than the clock path delay.

OPA4131NA/2K5E4

Vendor:BB/TIPackage Cooled:9360D/C:06+

SQD200A is a Darlington power transistor module which a high speed, high power Darlington transistor. The transistor has a reverse paralled fast recovery diode. The mounting base of the module is electrically isolated from semiconductor elements for simple heatsink construction,

OPA4131NAG4

Vendor:TIPackage Cooled:SOP14D/C:06+

Analog Interface The IRMCK203 has a built-in interface to the ADS7818 (BurrBrown) serial A/D converter (12 bit). Dc bus voltage feedback, external speed reference and Leg Shunt current can be obtained via ADS7818 in conjunction with MUX circuitry. An analog feedback application example is given in Section 2.4.2.

OPA4131NJ

Vendor:TIPackage Cooled:SOP14D/C:08+

The Hynix HYM72V32M636T6M Series are 32Mx64bits Synchronous DRAM Modules. The modules are composed of eight 16Mx16bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 144pin glass-epoxy printed circuit board. Two 0.33uF and one 0.1uF decoupling capacitors per each SDRAM are mounted on the PCB.

OPA4131NJ/2K5E4

Vendor:BB/TIPackage Cooled:SOP14D/C:06+

ARCHITECTURAL ADVANTAGES Simultaneous Read/Write operations - Data can be continuously read from one bank while executing erase/program functions in other bank - Zero latency between read and write operations Multiple bank architectures - Three devices available with different bank sizes (refer to Table 2) Package options - 48-ball TFBGA - 48-pin TSOP Top or bottom boot block Manufactur...

OPA4131NJG4

Vendor:TIPackage Cooled:SOP14D/C:06+

In most applications, the transient suppressor device is placed in parallel with the equipment or component to be protected. In this situation, there is a time delay associated with the capacitance of the device and an overshoot condition associated with the inductance of the device and the inductance of the connection method. The capacitive effect is of minor importance in the parallel protection sc...

OPA4131P

Vendor:30Package Cooled:TI

OPA4131PAG4

Vendor:in stockPackage Cooled:TID/C:06+

Receive byte clock. RBC0 and RBC1 are 62.5-MHz recovered clocks used for synchronizing the 10-bit output data on RD0 C RD9. The 10-bit output data words are valid on the rising edges of RBC0 and RBC1. These clocks are adjusted to half-word boundaries in conjunction with synchronous detect. The clocks are always expanded during data realignment and never slivered or truncated. RBC0 registers bytes 1 and 3...

OPA4131PJ

Vendor:BB/TIPackage Cooled:DIP14D/C:05+

The TLE 4476 is a monolithic integrated voltage regulator providing two output voltages, Q1 is a 3.3 V output for loads up to 350 mA and Q2 is a 5 V output providing 430 mA. The device is available in the P-TO252-5-1 (D-PAK) package. Output 2 can be switched ON/OFF via the Enable input EN.

OPA4131PJG4

Vendor:in stockPackage Cooled:TID/C:06+

AH,BH,CH - Are the highside logic level digital inputs. These three inputs control the three highside bridge transistors. Un- less the deadtime is disabled by connecting SWR to ground, the lowside input of each phase will override the corresponding highside input. If SWR is the lowside input of each phase will override the corresponding highside input. In this condition, tied to ground, deadtime is disa...

OPA4131UA

Vendor:BPackage Cooled:SOP16D/C:N/A

International Rectifier's FRED.. series are the state of the art Ultra fast recovery rectifiers specifically designed with optimized performance of forward voltage drop and ultra fast recovery time. The planar structure and the platinum doped life time control, guarantee the best overall performance, ruggedness and reliability characteristics. These devices are intended for use in the output rectification sta...

OPA4131UA/1K

Vendor:BB,TID/C:04+

a VCA gain of 8 dB and gives C9.8 dBu (250 mV) before limiting. Both have a noise gate threshold of C64 dBu (500 µV), below which downward expansion reduces the gain with a ratio of approximately 1:3. That is, a C3 dB reduction of output signal occurs with a C1 dB reduction of input signal. For applications requiring adjustable noise gate threshold, VCA gain up to 18 dB, and adjustable rotation po...

OPA4131UA/1KG4

Vendor:TIPackage Cooled:SOP16D/C:06+

FOR SAFETY USING Great detail and careful attention are given to the production activity of Hics, such as the development, the quality of production, and in its reliability. However the reliability of Hics depends not only on their own factors but also in their condition of usage. When handling Hics, please note the following cautions.

OPA4131UA/1KG4

Vendor:TIPackage Cooled:SOP16D/C:06+

FOR SAFETY USING Great detail and careful attention are given to the production activity of Hics, such as the development, the quality of production, and in its reliability. However the reliability of Hics depends not only on their own factors but also in their condition of usage. When handling Hics, please note the following cautions.

OPA4132AR

Vendor:ADPackage Cooled:SOPD/C:00+

OPA4132U

Vendor:SOP14Package Cooled:35050D/C:BB/TI

s Complies with Universal Serial Bus Specification Rev. 2.0 and most Device Class specifications s Supports data transfer at full-speed (12 Mbit/s) s High performance USB peripheral controller with integrated Serial Interface Engine (SIE), FIFO memory, transceiver and 3.3 V voltage regulator s High speed (11.1 Mbyte/s or 90 ns read/write cycle) parallel interface s Fully autonomous and mul...

OPA4132U/2K5E4

Vendor:BB/TIPackage Cooled:SOP14D/C:06+

such that M = 343 and A /64 = 075. Now, M is programmed to the integer part = 343 and A is programmed to the fractional part364 i.e., A = 075364 = 48. NB The minimum ratio N that can be used is P 22P (=4032 in our example) for all contiguous channels to be available. To check: N = 343364148 = 22000, which is the required division ratio and is greater than 4032 ( = P 22P ). When re-programming, the cou...

OPA4132UA BB 07+

OPA4132UA/2K5E4

Vendor:BBPackage Cooled:06+D/C:2352

DESCRIPTION The 74LVX3245 is a dual supply low voltage CMOS OCTAL BUS TRANSCEIVER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. Designed for use as an interface between a 5V bus and a 3.3V bus in a mixed 5V/3.3V supply systems, it achieves high speed operation while maintaining the CMOS low power dissipation.

OPA4134U

Vendor:SOP14Package Cooled:11580D/C:BB

The NetLink™ OPA4134U(M) is a fully integrated 10/100/1000OPA4134UASE- T Gigabit Ethernet media access control and physical layer transceiver (PHY) solution for client networking applications. The NetLink OPA4134U(M) combines a triple-speed, IEEE 802.3-compliant media access controller (MAC), a PCI v2.2 bus interface, an on-chip buffer memory, and an integrated PHY in a single device. The NetLink O...

OPA4134U

Vendor:SOP14Package Cooled:48050D/C:BB

The NetLink™ OPA4134U(M) is a fully integrated 10/100/1000OPA4134UASE- T Gigabit Ethernet media access control and physical layer transceiver (PHY) solution for client networking applications. The NetLink OPA4134U(M) combines a triple-speed, IEEE 802.3-compliant media access controller (MAC), a PCI v2.2 bus interface, an on-chip buffer memory, and an integrated PHY in a single device. The NetLink O...

OPA4134UA/2K5

Vendor:BB/TIPackage Cooled:SOP14D/C:04+

The embedded authentication protocol allows the memory and the host to authenticate each other. When this device is used with a host that incorporates a microcontroller (e.g., AT89C51, AT89C2051, AT90S1200), the system provides an anti-wiretapping configuration. The device and the host exchange challenges issued from a random generator and verify their values through a specific cryptographic function inclu...

OPA4134UA/2K5E4

Vendor:BB/TIPackage Cooled:SOP-14D/C:06+

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation sleep mode. Two clock cycles are required to enter into or exit from this sleep mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the sleep...

OPA4137P

Vendor:BB/TIPackage Cooled:DIP-14D/C:04+

generate TCLK (Transmit Clock), the internal clock used to transmit read data. The CFM and CFMN pins (Clock-From- Master) generate RCLK (Receive Clock), the internal clock signal used to receive write data and to receive the ROW and COL pins.

OPA4137PA

Vendor:608Package Cooled:BB/TID/C:N/A

10 ms. typical 5 ms. typical 100 MΩ, at 500 VDC, 50%RH 500 Vrms,1 min. 10 g,11ms. DA 1.5 mm, 10 - 55 Hz 1 M height drop on concrete Standard: 0.6W; Big Gap: 0.8W -30ºC to 85ºC operating; -40ºC to 100ºC storage 6 g, approx.

OPA4137PAG4

Vendor:BB/TIPackage Cooled:07+

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

OPA4137U

Vendor:BBPackage Cooled:SOPD/C:N/A

The PI6C104 is a high-speed low-noise clock generator designed to work with the PI6C18X family of clock buffer to meet all clock needs for Desktop Intel Architecture platforms. CPU and chipset clock frequencies from 66.6 MHz to 112 MHz are supported.

OPA4137U/2K5

Vendor:BB/TIPackage Cooled:SOP14D/C:04+

A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement of entering the three-byte program sequence is offered to further improve programming time. After entering the six-byte code, only single pulses on the write control lines are required for writing into the device. This mode (Single Pulse Word Program) is exited by powering down the device, or by pulsing the RESET pin l...

OPA4137UA/2K5

Vendor:BB/TIPackage Cooled:SOP14D/C:04+

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men...

OPA4137UA/2K5

Vendor:BB/TIPackage Cooled:SOP14D/C:04+

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men...

OPA4137UA/2K5E4

Vendor:BB,TID/C:06+

The devices also have 96 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, output or bi-directional I/O pin with 3-state control, and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching

OPA4137UE4

Vendor:TIPackage Cooled:SOP14D/C:05+

SECTOR LOCKDOWN DETECTION: A software method is available to determine if program- ming of a sector is locked down. When the device is in the software product identification mode (see Software Product Identification Entry/Exit sections on page 22), a read from address location 00002H within a sector will show if programming the sector is locked down. If the data on I/O0 is low, the sector can be programmed...

OPA413PA

Vendor:BBPackage Cooled:DIP14

OPA4140UA

Vendor:IN STOCKPackage Cooled:00+D/C:BB

The OPA4140UA is manufactured with Winbond high performance CMOS WinFlash technology. Thes Serial Flash is organized as 16 sectors of 4096 Bytes for the OPA4140UA. The memory is accessed for Read or Erase/Program by the SPI bus compatible serial protocol. The bus signals are: serial data input (SI), serial data output (SO), serial clock (SCK), write protect (#WP), chip enable (#CE), and hardware reset (#RES...

OPA4227PA

Vendor:260Package Cooled:BB/TID/C:N/A

Note 7: Because the Bus LVDS serial data stream is not decoded, the maximum frequency of the CHTST output driver could be exceeded if the data stream were switched to CHTST. The maximum frequency of the BUS LVDS input should not exceed the parallel clock rate.

OPA4227PAG4

To allow for dc coupling to ADCs, its unique output common-mode control circuit maintains the output common-mode voltage within 3 mV offset (typ) from the set voltage, when set within 0.5 V of mid-supply, with less than 4 mV differential offset voltage. The common-mode set point is set to mid-supply by internal circuitry, which may be over-driven from an external source.

OPA4227U

Vendor:SOP14Package Cooled:4630D/C:BB/TI

programming the ADC into the desired mode. The THS1009 consists of two analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured to single-ended or differential inputs. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the applica...

OPA4227U

Vendor:SOP14Package Cooled:4630D/C:BB/TI

programming the ADC into the desired mode. The THS1009 consists of two analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured to single-ended or differential inputs. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the applica...

OPA4227U/2K5

Vendor:BB/TIPackage Cooled:7630D/C:SOP14

OPA4227UA (PBF)

OPA4227UA/2K5

Vendor:BB/TIPackage Cooled:3720D/C:04+

To achieve fast and accurate switch performance, each device comprises four n-channel JFET transistors and a TTL compatible bipolar driver. In the on state, each switch conducts current equally well in either direction. In the off condition, the switches will block up to 20 V peak-to-peak, with feedthrough of less than C60 dB at 10 MHz.

OPA4227UA/2K5G4

Vendor:BB/TIPackage Cooled:SOP14D/C:06+

COMP and FB are the available external pins of the PWM converter error amplifier. The FB pin is the inverting input of the error amplifier. Similarly, the COMP pin is the error amplifier output. These pins are used to compensate the voltage-mode control feedback loop of the synchronous PWM converter.

OPA4227UA/2K5G4

Vendor:BB/TIPackage Cooled:SOP14D/C:06+

COMP and FB are the available external pins of the PWM converter error amplifier. The FB pin is the inverting input of the error amplifier. Similarly, the COMP pin is the error amplifier output. These pins are used to compensate the voltage-mode control feedback loop of the synchronous PWM converter.

OPA4228AP

Vendor:DIP14Package Cooled:1080D/C:BB

Description The OPA4228APR is an IC designed to drive the color LCD panels LCX032 and LCX033. This IC greatly reduces the number of peripheral circuits and parts by incorporating a RGB driver and timing generator for video signals onto a single chip. This chip has a built-in serial interface circuit and electronic attenuators which allow various settings to be performed by microcomputer control, etc.

OPA4228P

Vendor:BB/TIPackage Cooled:2836D/C:DIP/14

OPA4228PA

Vendor:BBD/C:DIP

The serial audio port consists of a shift clock (SCLK pin), a left/right frame synchronization clock (LRCLK pin), and a data input (SDIN pin). The serial audio port supports standard serial PCM formats (Fs = 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, or 192 kHz) stereo. See the serial interface formats section.

OPA4228U

Vendor:BBPackage Cooled:SOP-14D/C:08+PB

OPA4228UA/2K5

Vendor:BB/TIPackage Cooled:SOP14D/C:04+

The OPA4228UA/2K5/36BT may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, meaning that in addition to the rising edge triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register d...

OPA4228UAE4

Vendor:TIPackage Cooled:SOP14D/C:05+

The IF section uses a true-synchronous vision IF demodulator (PLL) with an intercarrier SAW filter in front of it. The analog AFC voltage is fed to the 5-level A/D converter in the PLL tuning IC, so that the AFC status can be read via the I2C-bus.

OPA4234P

Vendor:BB/TIPackage Cooled:DIP14D/C:05+

The Hitachi HM62V16256CBP Series is 4-Mbit static RAM organized 262,144-word 16-bit. HM62V16256CBP Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is packaged in 48 bumps chip size package with 0.75 mm b...

OPA4234P

Vendor:BB/TIPackage Cooled:DIP14D/C:05+

The Hitachi HM62V16256CBP Series is 4-Mbit static RAM organized 262,144-word 16-bit. HM62V16256CBP Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is packaged in 48 bumps chip size package with 0.75 mm b...

OPA4234PA

♦ Low Power: 511mW (fCLK = 100MHz) ♦ User Programmable Selectable 2x, 4x, or 8x Interpolating Filters <0.01dB Passband Ripple >99dB Stopband Rejection Selectable Real or Complex Modulator Operation Selectable Modulator LO Frequency: OFF, fIM / 2, or fIM / 4 Selectable Output Filter: Lowpass or Highpass Channel Gain and Offset Adjustment ♦ EV Kit Available (Order the MAX5895E...

OPA4234U/2K5

- Logic controlled 1-CH DC motor driver - 4-CH BTL(Balanced Transformerless) drivers - Built-in TSD (Thermal shutdown) circuit - Built-in 5V regulator with an internal NPN TR - Built-in mute circuit - Built-in tray motor speed control circuit - Wide operating supply voltage range: 6.5V~13.2V