OPA703NA/3KG4

Vendor:1200

The OPA703NA/3KG4 employs short, ultra-low duty cycle bursts of charge-transfer cycles to acquire its signal. Burst mode permits power consumption in the low microamp range, dramatically reduces RF emissions, lowers susceptibility to EMI, and yet permits excellent response time. Internally the signals are digitally processed to reject impulse noise, using a 'consensus' filter which requires four consec...

OPA703PA

Vendor:BBPackage Cooled:DIP-8D/C:05+

On-chip control functions make the ISD1000A Series very easy to use in a wide array of applica- tions. Each device offers a variety of operating modes and interface options. The devices may be used in applications that require little more than a few switches and a battery. The devices may also be integrated into electronic systems where digital addresses can be provided for more sophisti- cated message addr...

OPA703PAG4

Hynix HYMD132645B(L)8-M/K/H/L series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 32Mx64 high-speed memory arrays. Hynix HYMD132645B(L)8-M/K/ H/L series consists of sixteen 16Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD132645B(L)8-M/K/H/L series provide a high performance 8-byte interface in 5.25&q...

OPA703UA/2K5

Vendor:BB/TIPackage Cooled:SOP8D/C:04+

• Precision voltage monitor for 3V, 3.3V or 5V power supplies • /RESET remains valid with VCC as low as 1.4V • <15µA supply current • 20ms, 40ms, or 1100ms minimum reset pulse widths available • Manual reset input • 4-pin SOT-143 package

OPA703UA/2K5E4

Vendor:BB/TIPackage Cooled:SOP8D/C:05+

The product spectrum is designed for supply voltages of 2.5 V, 3 V, 3.3 V, and 5 V. The circuits are available in a 5-pin SOT23-5 package. The TPS382x-xxQ-Q1 devices are characterized for operation over a temperature range of C40C to 125C, and are qualified in accordance with AEC-Q100 stress test qualification for integrated circuits.

OPA703UAG4

Small Size Surface Mount DPAK Package Passivated Die for Reliability and Uniformity Blocking Voltage to 800 V On−State Current Rating of 4.0 A RMS at 108C High Immunity to dv/dt − 500 V/ms at 125C High Immunity to di/dt − 6.0 A/ms at 125C Epoxy Meets UL 94, V−0 @ 0.125 in ESD Ratings: Human Body Model, 3B u 8000 V Machine Model, C u 400 V

OPA704NA/250

Vendor:TI/BBPackage Cooled:05+D/C:0

Digital Control A digital-to-analog converter (DAC) allows selection of the following modes: OFF, 7mA, 14mA, 20mA, per diode. By turning the IN B pin ON and OFF, the current can be modulated between 7 to 20mA to achieve any IAverage value (PWM). In PWM mode, the modulating frequency has to be set sufficiently high in order to avoid a flickering effect (100Hz to 1kHz).

OPA704NA/3K

Vendor:TIPackage Cooled:SOT23-5D/C:05+

Single power supply. Crystal/Ring oscillator option. 3-340 seconds voice capacity. Power down mode for saving power consumption. Reset pin available. Single ROM for voice program. Maximum 32 K program addressing size available. Readable ROM data. One 6 bit timer overflow control is provided. Two stack for subroutine call. 5 bits ASPCM synthesis. 38K Hz modulation for IR transmission. 15 steps volume c...

OPA704NA/3KCT-ND

Vendor:=D/C:-

RJA is the sum of the junction-to-case and case-to-ambient resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design while RCA is determined by the user's board design.

OPA704NA/3KG4

Vendor:TIPackage Cooled:SOT23-5D/C:06+

Calibration Cycle Initiate. A minimum 80 input clock cycles logic low followed by a minimum of 80 input clock cycles high on this pin initiates the self calibration sequence. See Section 2.4.2 for an overview of self-calibration and Section 2.4.2.2 for a description of on-command calibration.

OPA704UA

Vendor:BB/TIPackage Cooled:SOP8D/C:04+

Pericom Semiconductors PI5C16212 is a 24-bit bus exchange switches designed with a low On-Resistance allowing inputs to be connected directly to outputs. This device operates as a 24-bit bus switch or a 12-bit exchanger that provides data exchanging between the four signal ports via the data select pins (S0-S2).

OPA704UA/2K5

Vendor:BB/TIPackage Cooled:SOP8D/C:04+

Secondary Reference (Input). This is one of two (PRI & SEC) input reference sources (falling edge) used for synchronization. One of four possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be used. The selection of the input reference is based upon the MS, and RSEL, control inputs.This pin is internally pulled up to VDD.

OPA704UA/2K5

Vendor:BB/TIPackage Cooled:SOP8D/C:04+

Secondary Reference (Input). This is one of two (PRI & SEC) input reference sources (falling edge) used for synchronization. One of four possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be used. The selection of the input reference is based upon the MS, and RSEL, control inputs.This pin is internally pulled up to VDD.

OPA705

Vendor:BBD/C:07+

OPA705NA/250

Vendor:TI/BBPackage Cooled:05+D/C:0

- Updated SPI electrical characteristics. - Updated Derivative Differences table. - Added ordering number example. - Added Detailed Register Map. - Changed Internal Pull Resistor column of signal table. - Added pull device description for MODC pin. - Corrected XCLKS figure titles. Moved table to section Modes of Operation. - Removed 1/2 from BDM in Figure Clock Connections. - Completely rewo...

OPA705NA/3K

Package Cooled:N/AD/C:04+

The two flip-flops have common clock (CK), clock enable (EC) and set/reset (SR) inputs. Internally both flip-flops are also controlled by a global initialization signal (GSR) which is described in detail in Global Signals: GSR and GTS, page 20.

OPA705UA/2K5

Vendor:BB/TIPackage Cooled:1000D/C:DIP8

Data Outputs: A 4-bit parallel data word, forming a HEX character representing the decoded tone frequency. This word is output after a successful decode. Table 1 details the Hex character output codes for the relevant decoded tone frequencies. Upon power-up this output is set to EH, but no Data Change pulse generated. These are tri-state outputs.

OPA705UA/2K5G4

Vendor:TIPackage Cooled:SOP8D/C:05+

OPA705UAG4

Hynix HYMD264646A(L)8J-J series is designed for high speed of up to 166MHz and offers fully synchronous opera- tions referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelin...

OPA725AID

Audio PLL and system PLL Read-Solomon encoder and decoder SPDIF interface Low cost low power EPICS7B DSP core with hardware debugger and JTAG interface Integrated memories: x 24/6 kWords program ROM/RAM (bit width: 32 bits) x 12 kWords X data RAM (bit width: 24 bits) x 12/2 kWords Y data ROM/RAM (bit width: 12 bits). Interrupt controller DMA controller Oscillator and time base unit with programma...

OPA725AIDBVT

Package Cooled:N/AD/C:06+

The ASH transceivers unique feature set is made possible by its system architecture. The heart of the transceiver is the amplifier- sequenced receiver section, which provides more than 100 dB of stable RF and detector gain without any special shielding or de- coupling provisions. Stability is achieved by distributing the total RF gain over time. This is in contrast to a superheterodyne receiver, which achiev...

OPA725AIDBVT

Package Cooled:N/AD/C:06+

The ASH transceivers unique feature set is made possible by its system architecture. The heart of the transceiver is the amplifier- sequenced receiver section, which provides more than 100 dB of stable RF and detector gain without any special shielding or de- coupling provisions. Stability is achieved by distributing the total RF gain over time. This is in contrast to a superheterodyne receiver, which achiev...

OPA725AIDG4

3.3V LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A, FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD# (active LOW) assertion, this pin becomes a real-time input for asserting power-down (active HIGH).

OPA725ID

Vendor:BB/TIPackage Cooled:SOP8D/C:04+

OPERATION In order to prevent data corruption and inadvertent write operations during power-up, a Power On Reset (POR) circuit resets all internal programming cicuitry. Access to the memory in write mode is allowed after a power-up as specified in Table 7. Read The M28LV16 is accessed like a static RAM. When E and G are low with W high, the data addressed is presented on the I/O pins. The I/O pins ...

OPA726AID

Vendor:BB/TIPackage Cooled:SOP8D/C:04+

Broadcom®, the pulse logo, and Connecting everything®, and QAMLink® are trademarks of Broadcom Corporation and/or its subsidiaries in the United States and certain other countries. All other trademarks mentioned are the property of their respective owners.

OPA726AID

Vendor:BB/TIPackage Cooled:SOP8D/C:04+

Broadcom®, the pulse logo, and Connecting everything®, and QAMLink® are trademarks of Broadcom Corporation and/or its subsidiaries in the United States and certain other countries. All other trademarks mentioned are the property of their respective owners.

OPA726AIDG4

OPA726AIDGKR

Vendor:TIPackage Cooled:04+D/C:0

10BASE-T/100BASE-TX IEEE-802.3 compliant TX and RX functions requiring a dual 1:1 isolation transformer interface to the line Integrated MII, 10BASE-T/100BASE-TX ENDEC, 100BASE-TX scrambler/descrambler, and full- featured auto-negotiation function Full duplex operation capable PCS Bypass supports 5-bit symbol interface Dual speed clock recovery Automatic polarity correction during auto- negotiation and 10...

OPA726AIDGKT

The contents of the offset registers can be read to the data outputs when WEN2/LD is LOW and both REN1 and REN2 are LOW. LOW-to-HIGH transitions of RCLK read register contents to the data outputs. Writes and reads should not be performed simultaneously on the offset registers.

OPA726AIDGKTG4

Four independent 128-bit wide internal data buses, each con- necting to the six 2M bit memory banks, enable quad-word data, instruction, and I/O accesses and provide 28G bytes per second of internal memory bandwidth. Operating at 500 MHz, the ADSP-TS202S processors core has a 2.0 ns instruction cycle time. Using its Single-Instruction, Multiple-Data (SIMD) fea- tures, the ADSP-TS202S processor can perf...

OPA727ADIG(AUE)

OPA727AIDGKR

Package Cooled:MSSOP

These LCA functions are established by a configuration program which is loaded into an internal, distributed array of configuration memory cells. The configuration program is loaded into the LCA device at power-up and may be reloaded on command. The Logic Cell Array includes logic and control signals to implement automatic or passive

OPA727AIDGKT

If ((7/8 bit = 0) And (DIV bit = 0)) PWM base period CLOCK period x 128 else If ((7/8 bit = 0) And (DIV bit = 1)) PWM base period = CLOCK period x 256 else If ((7/8 bit = 1) And (DIV bit = 0)) PWM base period = CLOCK period x 256 else If ((7/8 bit = 1) And (DIV bit = 1)) PWM base period = CLOCK period x 512

OPA727AIDGKTG4

Operates from Single +5V Power Supply Meets All RS-232D and ITU V.28 Specifications Operates with 0.1µF to 10µF Capacitors High Data Rate C 120Kbps Under Load Low Power Shutdown 1µA (Typical) 3-State TTL/CMOS Receiver Outputs Low Power CMOS C 3mA Operation Improved ESD Specifications: 15kV Human Body Model 15kV IEC1000-4-2 Air Discharge 8kV IEC1000-4-2 Contact Discharge

OPA728AIDGKR

Vendor:TID/C:08+

Single Supply for Read and Write: 2.7V to 3.6 (BV), 3.0 to 3.6V (LV) Fast Read Access Time - 70 ns Internal Program Control and Timer Sector Architecture C One 16K Byte Boot Block with Programming Lockout C Two 8K Byte Parameter Blocks C Two Main Memory Blocks (32K, 64K) Bytes Fast Erase Cycle Time - 10 seconds Byte By Byte Programming - 30 µs/Byte Typical Hardware Data Protection DATA Polling ...

OPA728AIDGKRG4

n −40˚C to +85˚C operation n Complete CODEC and filtering system (COMBO) including: Transmit high-pass and low-pass filtering Receive low-pass filter with sin x/x correction Active RC noise filters µ-law or A-law compatible COder and DECoder Internal precision voltage reference Serial I/O interface Internal auto-zero circuitry n µ-law, 16-pin TP3054 n A-law...

OPA728AIDGKT

Package Cooled:MSOP-8

The FDC37M70x supports the ISA Plug-and- Play Standard (Version 1.0a) and provides the recommended functionality to support Windows '95.The I/O Address, DMA Channel and hardware IRQ of each logical device in the FDC37M70x may be reprogrammed through the internal configuration registers. There are 480 I/O address location options, a Serialized IRQ interface, and three DMA channels.

OPA728AIDRBR

Vendor:TIPackage Cooled:SON-8D/C:06+

The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or ommisions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the users own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits...

OPA734

Vendor:BBD/C:07+

OPA734A

Vendor:BBPackage Cooled:SOP8D/C:06+

• Highest sustained bandwidth per DRAM device C 1.6 GB/s sustained data transfer rate C Separate control and data buses for maximized efficiency C Separate row and column control buses for easy scheduling and highest performance C 32 banks: four transactions can take place simultaneously at full bandwidth data rates

OPA734AID

Vendor:BBPackage Cooled:SOPD/C:06+

Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage. Products are not designed, authorized, or warranted to be suitable for use in life support devices or systems or other critical applications. Inclusion of Performance Motion Devices, Inc. products in such applications is understood to be fully at the customers ...

OPA734AIDBVR

Vendor:TID/C:08+

If a 1Cwire device is present on the I/O line it pulls I/O low after time T (15 µs T 60 µs) from the previous rising edge. The 1Cwire device(s) holds the I/O line low for 4T and then releases it, allowing the I/O line to return high. This is the presence detect pulse. The I/O line must remain high (in its idle state) for at least 3T before the 1Cwire device(s) is ready for further communi...

OPA734AIDBVT

Package Cooled:N/AD/C:99+

The IDT70V06 is a high-speed 16K x 8 Dual-Port Static RAM. The IDT70V06 is designed to be used as a stand-alone 128K-bit Dual-Port Static RAM or as a combination MASTER/SLAVE Dual-Port Static RAM for 16-bit-or-more word systems. Using the IDT MASTER/ SLAVE Dual-Port Static RAM approach in 16-bit or wider memory system applications results in full-speed, error-free operation without the need for additional d...

OPA734AIDBVT

Package Cooled:N/AD/C:99+

The IDT70V06 is a high-speed 16K x 8 Dual-Port Static RAM. The IDT70V06 is designed to be used as a stand-alone 128K-bit Dual-Port Static RAM or as a combination MASTER/SLAVE Dual-Port Static RAM for 16-bit-or-more word systems. Using the IDT MASTER/ SLAVE Dual-Port Static RAM approach in 16-bit or wider memory system applications results in full-speed, error-free operation without the need for additional d...

OPA734AIDBVTG4

Capacitance of Schottky diode quads is measured using an HP4271 LCR meter. This instrument effectively isolates individual diode branches from the others, allowing accurate capacitance measurement of each branch or each diode. The conditions are: 20 mV R.M.S. voltage at 1 MHz. HP defines this measurement as CM, and it is equivalent to the capacitance of the diode by itself. The equivalent diagonal an...

OPA734AIDR

Vendor:BB/TIPackage Cooled:SOP8D/C:04+

The ISL6527 provides simple, single feedback loop, voltage- mode control with fast transient response. The output voltage can be regulated to as low as the provided external reference. A fixed frequency oscillator reduces design complexity, while balancing typical application cost and efficiency.

OPA734IDR

Vendor:BB/TIPackage Cooled:SOP8D/C:04+

A voltage programmable mute threshold (MCLADJ) is included to allow muting of the OPA734IDR output when a selected cable length is reached. This feature allows the OPA734IDR to distinguish between low amplitude HD SDI signals and noise at the input of the device. The CD/Mute pin provides an indication of the OPA734IDR mute status in addition to functioning as a mute control input. The output of the OPA734IDR...

OPA735

Vendor:BBD/C:07+

OPA735A

Vendor:BBPackage Cooled:SOP8D/C:06+

The MC10/100EP139 is a low skew 2/4, 4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single−ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using th...

OPA735AID

Vendor:BBPackage Cooled:SOPD/C:05+

The AUTO PRECHARGE function ensures that the precharge is initiated at the earliest valid stage within a burst. This function allows for individual-bank precharge without requiring an explicit command. A10 to enables the AUTO PRECHARGE function in conjunction with a spe- cific READ or WRITE command. For each individual READ or WRITE command, auto precharge is either

OPA735AIDBVR

Vendor:TID/C:08+

Description Agilent Technologiess ATF- 501P8 is a single-voltage high linearity, low noise E-pHEMT housed in an 8-lead JEDEC- standard leadless plastic chip carrier (LPCC[3]) package. The device is ideal as a medium- power amplifier. Its operating frequency range is from 400 MHz to 3.9 GHz.

OPA735AIDBVT

Vendor:TIPackage Cooled:08+D/C:10

Introduction Hewlett-Packards family of HSMS-285A zero bias Schottky diodes have been developed specifically for low cost, high volume detector applications where bias current is not available. The HSMS-286A family of DC Schottky diodes have been developed for low cost, high volume detector applications where stability over temperature is an important design consideration.

OPA735AIDBVT

Vendor:TIPackage Cooled:08+D/C:10

Introduction Hewlett-Packards family of HSMS-285A zero bias Schottky diodes have been developed specifically for low cost, high volume detector applications where bias current is not available. The HSMS-286A family of DC Schottky diodes have been developed for low cost, high volume detector applications where stability over temperature is an important design consideration.

OPA735AIDBVTG4

True 64-bit microprocessor C 64-bit integer operations C 64-bit floating-point operations C 64-bit registers C 64-bit virtual address space xHigh-performance microprocessor C 260 Dhrystone MIPS at 200MHz C 100 peak MFLOP/s at 200MHz C Two-way set associative caches C Simple 5-stage pipeline xHigh level of integration C 64-bit, 200 MHz integer CPU C 64-bit floating-point unit C 16KB instru...

OPA735AIDG4

The RTC Registers are double-buffered into an internal and external set. The user has direct access to the external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow the user to access static data. Assuming the internal oscillator is turned on, the internal set of registers are continuously updated; this occurs regardless of external registers settings to gu...

OPA735AIDR

Vendor:BB/TIPackage Cooled:SOP8D/C:04+

The QS4A210 is a high-performance CMOS two-channel SP4T multi- plexer/demultiplexer with individual enables. The low On-resistance of the QS4A210 allows inputs to be connected to outputs with low insertion loss and high bandwidth. TTL-compatible control circuitry with Break-Before-Make feature prevents contention. The QS4A210 with 700MHz bandwidth makes it ideal for high-perfor- mance video signal swit...

OPA735AIDR

Vendor:BB/TIPackage Cooled:SOP8D/C:04+

The QS4A210 is a high-performance CMOS two-channel SP4T multi- plexer/demultiplexer with individual enables. The low On-resistance of the QS4A210 allows inputs to be connected to outputs with low insertion loss and high bandwidth. TTL-compatible control circuitry with Break-Before-Make feature prevents contention. The QS4A210 with 700MHz bandwidth makes it ideal for high-perfor- mance video signal swit...

OPA735AIDRG4

Reception output H voltageVroH Reception output L voltageVroL Transmission waveform LOSS 1Vtloss1 Transmission waveform LOSS 2Vtloss2 General logic unit characteristics H level input voltageViH L level input voltageViL H level input currentIiH L level input currentIiL

OPA735IDR

Vendor:BB/TIPackage Cooled:SOP8D/C:04+

OPA740U

Vendor:N/APackage Cooled:SOP8D/C:08+09+

Thermal Sensitive Layer Over a 0.35 µm CMOS Array Image Zone: 0.4 x 11.6 mm Image Array: 8 232 = 1856 Pixels Pixel Pitch: 50 50 µm = 500 dpi Resolution On-chip 8-bit Analog to Digital Converter Serial Peripheral Interface (SPI) - 2 Modes: C Fast Mode at 16 Mbps Max for Imaging C Slow Mode at 200 kbps Max for Navigation and Control Die Size: 1.5 15 mm Operating Voltage: 2.3 to 3.6V I/O V...

OPA743NA/250

Vendor:in stockD/C:06+

The Advanced Interrupt Controller (AIC) controls the internal sources from the internal peripherals and the four external interrupt lines (including the FIQ) to provide an inter- rupt and/or fast interrupt request to the ARM7TDMI. It integrates an 8-level priority controller, and, using the Auto-vectoring feature, reduces the interrupt latency time.

OPA743NA/250G4

The external port supports asynchronous, synchronous, and synchronous burst accesses. ZBT synchronous burst SRAM can be interfaced gluelessly. Addressing of external memory devices is facilitated by on-chip decoding of high-order address lines to generate memory bank select signals. Separate control lines are also generated for simpli- fied addressing of page-mode DRAM. The OPA743NA/250G4 provides pro...

OPA743NA/3KG4

Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have been removed. Note 2: Offset nulled. Note 3: Shutdown supply currents are typically 0.5µA, maximum specification is limited by automated test equipment. Note 4: Defined as the change in positive full scale caused by a 5% variation in the nominal supply. Note 5: To e...

OPA743PA

Vendor:BBPackage Cooled:06+D/C:800

The UC3823A and UC3823B and the UC3825A and UC3825B family of PWM controllers are improved versions of the standard UC3823 and UC3825 family. Performance enhancements have been made to several of the circuit blocks. Error amplifier gain bandwidth product is 12 MHz, while input offset voltage is 2 mV. Current limit threshold is assured to a tolerance of 5%. Oscillator discharge current is specified at...

OPA743PAG4

Vendor:TIPackage Cooled:DIPD/C:08+

The OPA743PAG4 is optimized for use as the primary-side companion controller for a cascaded converter that has secondary-side control. The device incorporates dead-time programming. The synchronization output also provides dead-time information. The retry and soft-start duration scales with the oscillator clock frequency for high performance fault recovery.

OPA743UA

Vendor:TIPackage Cooled:SOP8D/C:09+

• High-speed access time: 35, 45, 55, 70 ns • Low active power: 450 mW (typical) • Low standby power: 500 µW (typical) CMOS standby • Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single 5V (10%) power supply

OPA747A

Vendor:ADPackage Cooled:SOP

When calculating synchronous frequencies, use tS1 if all inputs are on the input pins. tS2 should be used if data is applied at an I/O pin. If tS2 is greater than tCO1, 1/tS2 becomes the limiting frequency in the data-path mode unless 1/(tWH + tWL) is less than 1/tS2.

OPA7521

OPA777U

Vendor:BB/TIPackage Cooled:SOP8D/C:04+

The LTC®4055 is a USB power manager and Li-Ion battery charger designed to work in portable battery-powered applications. The part manages and limits the total current used by the USB peripheral for operation and battery charging. Depending on the state of the current select pin (HPWR), total input current can be limited to either 100mA or 500mA. The voltage drop from the USB supply or battery to the USB...

OPA77AJ

Vendor:BBD/C:04+

HERMETIC 100mil CERAMIC FLANGE PACKAGE +28.0dBm TYPICAL OUTPUT POWER HIGH BVgd FOR 10V BIAS 9.0dB TYPICAL POWER GAIN AT 8GHz 0.3 X 1200 MICRON RECESSED MUSHROOM GATE Si3N4 PASSIVATION ADVANCED EPITAXIAL DOPING PROFILE PROVIDES HIGH POWER EFFICIENCY, LINEARITY AND RELIABILITY

OPA77AJ/883

Vendor:BBD/C:04+

A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement for Port B. The level of SIZE must be static throughout device operation.

OPA77AJ/883

Vendor:BBPackage Cooled:CAN8D/C:04+

A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement for Port B. The level of SIZE must be static throughout device operation.

OPA77BJ

Vendor:BBPackage Cooled:CAN8D/C:04+

applied to the RESET pin while PWM inputs In1,...IN6 are held high (off condition). The FAULT condition can also be set by the controller through an active high signal on the STOP pin. After power-up, the RESET pin must be pulled low before any input signals are activated. The protection circuitry will set a FAULT for short-circuit, earth-fault, over-temperature, or over-voltage conditions as specified...

OPA77BJ/883

Vendor:BBPackage Cooled:CAN8D/C:04+

The Problem A momentary short can increase power dissipation in a MOSFET voltage regulator pass device to a catastrophic level. In the circuit of Figure 1, power dissipation in Q1 is approximately VDS IOUT, or (5V C 3.3V) 10A = 17W. If the output of the power supply is shorted it becomes

OPA77BJ/883

Vendor:BBPackage Cooled:CAN8D/C:04+

The Problem A momentary short can increase power dissipation in a MOSFET voltage regulator pass device to a catastrophic level. In the circuit of Figure 1, power dissipation in Q1 is approximately VDS IOUT, or (5V C 3.3V) 10A = 17W. If the output of the power supply is shorted it becomes

OPA77CJ

Vendor:BBPackage Cooled:CAN8D/C:04+

with serial programming. The flags are updated according to the timing mode and default offsets selected. The Partial Reset (PRS) also sets the read and write pointers to the first location of the memory. However, the timing mode, partial flag program- ming method, and default or programmed offset settings existing before Partial Reset remain unchanged. The flags are updated according to the timing mode and...

OPA77CJ/883

Vendor:BBPackage Cooled:CAN8D/C:04+

1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachis permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this doc...

OPA77CJ/883

Vendor:BBPackage Cooled:CAN8D/C:04+

1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachis permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this doc...

OPA77CZ/883

Vendor:BBPackage Cooled:CDIP8D/C:04+

4. DC/DC, PECL for Signal Detect PECL compatible. Load is 50 Ω into VCC C2 V for data, 500 Ω to VEE for Signal Detect. Measured under DC conditions. For dynamic mea- surements a tolerance of 50 mV should be added. VCC=3.3 V/5 V. TAMB=25C.

OPA77EP

Package Cooled:N/AD/C:04+

• high frequency rectifiers, output rectifiers of switched mode power supplies • single phase mains rectifiers with minimized electromagnetic emissions • power factor correction in conjunction with boost chopper (FID.../FMD... type)

OPA77EZ

Vendor:BBPackage Cooled:CDIP8D/C:04+

Pulse triggering occurs at a particular voltage level and is not related directly to the transition time of the input pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.

OPA77FJ

Vendor:BBPackage Cooled:CAN8D/C:04+

• 2A/3.3V, 5V, 5.1V, 9V, 12V output low dropout voltage regulator • TO-220 full-mold package (4pin) • Overcurrent protection, thermal shutdown • Overvoltage protection, short circuit protection • With output disable function

OPA77FJ

Vendor:BBPackage Cooled:CAN8D/C:04+

• 2A/3.3V, 5V, 5.1V, 9V, 12V output low dropout voltage regulator • TO-220 full-mold package (4pin) • Overcurrent protection, thermal shutdown • Overvoltage protection, short circuit protection • With output disable function

OPA77FZ

Vendor:BBPackage Cooled:CDIP8D/C:94+

C 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) C 512K-Bit Dual-Access Internal Data (64K Bytes) 32-Bit External Memory Interface (EMIF) C Glueless Interface to Synchronous Memories: SDRAM and SBSRAM C Glueless Interface to Asynchronous Memories: SRAM and EPROM Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel 16-Bit Host-Port Interface (HPI) C Acc...

OPA77FZ

Vendor:BBPackage Cooled:CDIP8D/C:94+

C 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) C 512K-Bit Dual-Access Internal Data (64K Bytes) 32-Bit External Memory Interface (EMIF) C Glueless Interface to Synchronous Memories: SDRAM and SBSRAM C Glueless Interface to Asynchronous Memories: SRAM and EPROM Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel 16-Bit Host-Port Interface (HPI) C Acc...

OPA77FZ/EZ

Vendor:BBPackage Cooled:04D/C:8

For cost-effective system solution, the SD1010A implements many system support features such as OSD mixer, error status indicators, 2-wire serial interface for both EEPROM and host CPU interface, and low-cost IC package. Another important contributing factor is that the SD1010A does not require external frame buffer memory for the automatic image scaling and synchronization.

OPA77GJ

Vendor:BBPackage Cooled:CAN8D/C:04+

I2C Address Select (Internal pull-up) This pin is the I2C Address Select, which corresponds to bits 1 and 0 of the I2C device address (see the I2C Port Operation section for details), creating an address selection as follows: ADDRI2C Address Selected 11110101 = 75H = 117 01110110 = 76H = 118

OPA77GJ

Vendor:BBPackage Cooled:CAN8D/C:04+

I2C Address Select (Internal pull-up) This pin is the I2C Address Select, which corresponds to bits 1 and 0 of the I2C device address (see the I2C Port Operation section for details), creating an address selection as follows: ADDRI2C Address Selected 11110101 = 75H = 117 01110110 = 76H = 118

OPA77GZ

Vendor:BBPackage Cooled:CDIP8D/C:04+

The TMS29F800T/B is an 1 048 576 by 8-bit / 524 288 by 16-bit (8 388 608-bit), 5-V single-supply, programmable read-only memory device that can be electrically erased and reprogrammed. This device is organized as 1 048 576 by 8 bits or 524 288 by 16 bits, divided into 19 sectors:

OPA7816U

Vendor:BBPackage Cooled:SOP8D/C:04+

Hynix HYMD232726A(L)8J-J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 32Mx72 high-speed memory arrays. Hynix HYMD232726A(L)8J-J series consists of nine 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD232726A(L)8J-J series provide a high performance 8-byte interface in 5.25" width form fac...

OPA7816U

Vendor:BBPackage Cooled:SOP8D/C:04+

Hynix HYMD232726A(L)8J-J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 32Mx72 high-speed memory arrays. Hynix HYMD232726A(L)8J-J series consists of nine 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD232726A(L)8J-J series provide a high performance 8-byte interface in 5.25" width form fac...

OPA8043U

Vendor:availPackage Cooled:BBD/C:04+

The OPA8043U monitors all the output voltages. The PWM controllers adjustable overcurrent function monitors the output current by using the voltage drop across the upper MOSFETs rDS(ON). The linear regulator outputs are monitored via the FB pins for undervoltage events.

OPA8043U

Vendor:availPackage Cooled:BBD/C:04+

The OPA8043U monitors all the output voltages. The PWM controllers adjustable overcurrent function monitors the output current by using the voltage drop across the upper MOSFETs rDS(ON). The linear regulator outputs are monitored via the FB pins for undervoltage events.

OPA820

Vendor:BBPackage Cooled:SOP-8D/C:05+

The OPA820USB is an 8 port USB hub with 1 upstream port and 7 downstream ports. It uses an 8-bit RISC-like uC to encode/decode the host commands. The OPA820USB is designed mainly for stand-alone hub and can also be integrated in PC mo therboard or any other devices to support USB hub function. The OPA820USB can switch between self- power and bus-power automatically without re-plug in. The OPA820USB can be ...

OPA820

Vendor:BBPackage Cooled:SOP-8D/C:05+

The OPA820USB is an 8 port USB hub with 1 upstream port and 7 downstream ports. It uses an 8-bit RISC-like uC to encode/decode the host commands. The OPA820USB is designed mainly for stand-alone hub and can also be integrated in PC mo therboard or any other devices to support USB hub function. The OPA820USB can switch between self- power and bus-power automatically without re-plug in. The OPA820USB can be ...

OPA820ID

Vendor:TIPackage Cooled:SOP8D/C:08+

The Super-220 is a package that has been designed to have the same mechanical outline and pinout as the industry standard TO-220 but can house a considerably larger silicon die. It has increased current handling capability over both the TO-220 and the much larger TO-247 package. This makes it ideal to reduce component count in multiparalled TO-220 applications, reduce system power dissipation, upgrade ex...

OPA820IDG4

Vendor:in stockPackage Cooled:TID/C:06+

NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 4. VCC = 3.0V, VEE = 0V, all other pins floating. 5. All loading with 50 ohms to VCC C2.0 volts. 6. Input and output parameters vary 1:1 with...

OPA822AN

OPA827AID

Vendor:TIPackage Cooled:SO-8D/C:08

In addition, this family is immune to the effects of parasitic capacitance and can drive large capacitive loads. This provides Printed Circuit Board (PCB) layout design flexibility by enabling the device to be remotely located from the microcontroller. Adding some capacitance at the output also helps the output transient response by reducing overshoots or undershoots. However, capacitive load is not ...

OPA827AIDGKR