Index "O"Vendor:PHILIPSPackage Cooled:NULLD/C:NULL
Vendor:PHILIPSPackage Cooled:NULLD/C:;00+
Vendor:STPackage Cooled:PQFP-100D/C:2
A: The value of R JA is measured with the device mounted on 1in 2 FR-4 board with 2oz. Copper, in a still air environment with T A=25C. The value in any a given application depends on the user's specific board design. The current rating is based on the t 10s thermal resistance rating. B: Repetitive rating, pulse width limited by junction temperature. C. The R JA is the sum of the thermal impedence from junc...
Vendor:STPackage Cooled:PQFP-100D/C:2
A: The value of R JA is measured with the device mounted on 1in 2 FR-4 board with 2oz. Copper, in a still air environment with T A=25C. The value in any a given application depends on the user's specific board design. The current rating is based on the t 10s thermal resistance rating. B: Repetitive rating, pulse width limited by junction temperature. C. The R JA is the sum of the thermal impedence from junc...
Vendor:PLCCD/C:00+
ISOPLUS247 package with DCB Base - Electrical isolation towards the heatsink - Low coupling capacitance to the heatsink for reduced EMI - High power dissipation - High temperature cycling capability of chip on DCB - JEDEC TO247AD compatible - Easy clip assembly
Vendor:PHILIPSD/C:05+
All the LNAs have switchable gain. The gain mode is selectable using the GAINSEL signal (pin 7). Low gain mode is selected by driving the GAINSEL signal to a logic 1; high gain mode is selected by driving the signal to a logic 0. Depending on the need of the handset design on the gain distribution, the gain step between the high gain and low gain modes can be set to either a 12 dB step or a 20 dB step. ...
Unless otherwise specified, the typical specification value applies over Vcc=5V, Vc=12V, VccLDO=5V and TA=25C. the Min and Max limits apply to the temperature range from 0 to 70C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
These P-Channel enhancement mode power field effect transistors are produced using Fairchilds proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for low voltage applications such as automot...
The SPI protocol is controlled by op-codes. These op-codes specify the commands to the device. After /CS is activated the first byte transferred from the bus master is the op-code. Following the op-code, any addresses and data are then transferred. Note that the WREN and WRDI op-codes are commands with no subsequent data transfer.
Package Cooled:DIP
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. N...
Serial data at 2048 kbit/s is received at the eight ST-BUS inputs (STi0 to STi7), and serial data is transmitted at the eight ST-BUS outputs (STo0 to STo7). Each serial input accepts 32 channels of digital data, each channel containing an 8-bit word which may represent a PCM-encoded analog/voice sample as provided by a codec. This serial input word is converted into parallel data and stored in the ...
Vendor:PHIPackage Cooled:SOP28D/C:04+
Vendor:N/APackage Cooled:DIP
Vendor:PHIPackage Cooled:DIPD/C:08+
3Msps Sampling ADC with Two Simultaneous Differential Inputs 1.5Msps Throughput per Channel Low Power Dissipation: 14mW (Typ) 3V Single Supply Operation 2.5V Internal Bandgap Reference with External Overdrive 3-Wire Serial Interface Sleep (10µW) Shutdown Mode Nap (3mW) Shutdown Mode 80dB Common Mode Rejection at 100kHz 0V to 2.5V Unipolar Input Range Tiny 10-Lead MS Package
Vendor:PHIPackage Cooled:1984
Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt ƒ Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case ) Mounting Torque, 6-32 or M3 screw
Signal Processors (DSPs) − TMS320C62x − 5-, 4-, 3.33-ns Instruction Cycle Time − 200-, 250-, 300-MHz Clock Rate − Eight 32-Bit Instructions/Cycle − 1600, 2000, 2400 MIPS C6202 and C6203B GLS Ball Grid Array (BGA) Packages are Pin-Compatible With the C6204 GLW BGA Package† C6202B and C6203B GNZ and GNY Packages are Pin-Compatible VelociTI Advanced Very-Lo...
DIGITAL OUTPUTS(6) Logic Family Logic Coding Low Output Voltage (IOL = 50µA to 0.5mA) High Output Voltage (IOH = 50µA to 0.5mA) Low Output Voltage (IOL = 50µA to 1.6mA) High Output Voltage (IOH = 50µA to 1.6mA) 3-State Enable Time 3-State Disable Time Output Capacitance
Vendor:PHID/C:05+
Functioning Temperature (TF) The temperature at which a thermal cutoff changes its state of conductivity to open a circuit with detection current of 10mA or less as the only load. The temperature tolerance for the UL and CSA standard is +0C / -10C.
Vendor:PHID/C:05+
Functioning Temperature (TF) The temperature at which a thermal cutoff changes its state of conductivity to open a circuit with detection current of 10mA or less as the only load. The temperature tolerance for the UL and CSA standard is +0C / -10C.
Vendor:PHILIPSPackage Cooled:SOP28
The NetPHY™ 4LP device is available in the Commer- cial (0C to 70C) or Industrial (-40C to +85C) tem- perature ranges. The Industrial temperature range is well suited to environment such as enclosures with re- stricted air flow or outdoor equipment.
Vendor:OMNIRELD/C:01年02年
Note 9: Junction to ambient thermal resistance for the 7 lead TO-263 mounted horizontally against a PC board copper area of 1.0064 square inches (7.4 times the area of the TO-263 package) of 1 oz. (0.0014 in. thick) copper. Additional copper area will reduce thermal resistance further. See the thermal model in Switchers Made Simple ® software.
Vendor:____Package Cooled:TO220-3D/C:96+
Vendor:QFP-100Package Cooled:QFPD/C:04+
Supply current and output power are a function of the voltage input on the PC (power control) pin. All specifications in the Electrical Charac- teristics table applies for condition VPC = 350mV. Increasing the voltage on the PC pin will increase transmit power and also increase MARK supply current. Refer to the graphs "Output Power Versus PC Pin Voltage" and "Mark Current Versus PC Pin Voltag...
Notes a: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at con- ditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat- ing conditions for extended periods may affect reliability.
Notes a: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at con- ditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat- ing conditions for extended periods may affect reliability.
Vendor:PHIPackage Cooled:SOP-8
It features a preamplifier module with adjustable gain and a unique power amplifier module that can be operated either as a high power, high efficiency class B amplifier, with very low quiescent current consumption, or as a medium power "vari-bias" class A amplifier.
Vendor:PHIPackage Cooled:SOP8
The LAN91C100FD is based on the LAN91C100 FEAST, functional revision G modified to add full duplex capability. Also added is a software-controlled option to allow collisions to discard receive packets. Previously, the LAN91C100 supported a Diagnostic Full Duplex mode. Under this mode the transmit packet is looped internally and received by the MAC. This mode was enabled using the FDUPLX bit in the TCR. In ord...
Vendor:N/MPackage Cooled:SOP-16D/C:0617+
Vendor:HEFPackage Cooled:DIP/18
Hynix HYMD232G726A(L)8-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
Package Cooled:SOP
1) CPD is defined as the value of the ICs internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per circuit)
Vendor:UNIVERSALPackage Cooled:N/AD/C:04+
Register File based 8/16 bit Core Architecture with RUN, WFI, SLOW and HALT modes 0C to +70C operating temperature range Up to 24 MHz. operation @ 5V10% Min. instruction cycle time: 165ns at 24 MHz. 48, 56, 64, 84 or 96 Kbytes ROM 256 bytes RAM of Register file (accumulators or index registers) 256 to 512 bytes of on-chip static RAM 2 or 8 Kbytes of TDSRAM (Teletext and Display Storage RAM) 28 f...
Vendor:phPackage Cooled:phD/C:dc93
AMDs Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
Vendor:MATPackage Cooled:DIPD/C:2002
Peak voltage across the varistor with a specified peak impulse current of 8 20s waveform. Maximum 50〜60Hz power which may be loaded for 1,000 hrs at 85 2 with VCmA/ VCmA Q 10%. The max. current within the varistor voltage change of less than 10% when one impulse current (8 20s) applied. The max. current with a varistor voltage change of less than 10% when two times impulse current (8 20s) are ap...
The feature set of the 80C186EB meets the needs of low power space critical applications Low-Power applications benefit from the static design of the CPU core and the integrated peripherals as well as low voltage operation Minimum current consump- tion is achieved by providing a Powerdown mode that halts operation of the device and freezes the clock circuits Peripheral design enhancements en- sure t...
Vendor:phPackage Cooled:phD/C:dc95
LCD Segment output terminal / LCD Common output terminal SEG40 in 1/3Duty use, COM4 in 1/4Duty use. LCD Segment output terminals / key scanning output terminals Select Segment output terminal or key scanning output terminal by the instruction. (No need for anti-reverse current diode in key scan) Key scanning output terminals. (No need for anti-reverse current diode in key scan)
XC3100 Family The XC3100 is a performance-optimized relative of the basic XC3000 family. While both families are bitstream and footprint compatible, the XC3100 family extends toggle rates to 270 MHz and in-system performance to 80 MHz. The XC3100 family also offers one additional array size, the XC3195. The XC3100 is best suited for designs that require the highest clock speed or the shortest net dela...
Package Cooled:05+
The AT40KAL, AT6000 and FPSLIC families are capable of implementing Cache Logic (dynamic full/partial logic reconfiguration, without loss of data, on-the-fly) for building adaptive logic and systems. As new logic functions are required, they can be loaded into the logic cache without losing the data already there or disrupting the operation of the rest of the chip; replacing or complementing the active log...
Vendor:PHILIPSPackage Cooled:SOPD/C:99
The ATA controller inside ADM uses DMA allowing instant data transfer from buffer to memory. This implementation eliminates microcontroller overhead associated with tradi- tional, firmware based, memory control, increasing data transfer rate.
Vendor:NULLPackage Cooled:NULLD/C:06+;08+
For the Read and all four Write commands, the data stored within the corresponding page of the EEPROM to the accessed page is repeatedly transmitted back to the reader by the chip after the command has completed. This permits a verify function for the commands. For the Write Lock and Write Configuration commands, the entire con- tents of page 8 are transmitted. Between each 32 bits transmitted, there...
Vendor:PHILIPSD/C:97
Measurements are done with the 13 MHz oscillator in slave mode. Measurements are done with a 32.768 kHz crystal connected to generate the Bluetooth low power clock. Measurements are done with a 13 MHz crystal connected and the Bluetooth low power clock derived from the 13 MHz.
Vendor:BGAPackage Cooled:PHID/C:98+
BSerial interface (CLK, STB, DIN, DOUT) BKey scanning (6 4 matrices) BProgramming display modes (11-digit & 11-segment to 6-digit & 16-segment) BProgramming dimming step BHigh-voltage output (VDD-35V max). B2 channels LED ports. B2-pin General-purpose input port BBuilt-in oscillator BNo external resistor necessary for driver outputs (provides PMOS open-drain and pull-low resistor
During initial turn-on the ISL6118 prevents nuisance faults from being reported to the system controller by blanking the fault signal for 12ms. This blanking eliminates the need for external RC filters necessary for other vendors products.
These devices are organized as four 4-bit low-impedanceswitcheswithseparate output-enable (OE) inputs. When OE is low, the switch is on, and data can flow from port A to port B, or vice versa. When OE is high, the switch is open, and the high-impedance state exists between the two ports.
Vendor:SSOP-40Package Cooled:PHILIPSD/C:04+
The transmitter is an inverting level translator that con- verts CMOS-logic levels to EIA/TIA-232 compatible lev- els. It guarantees data rates up to 460kbps with worst-case loads of 3kΩ in parallel with 1000pF. When SHDN is driven low, the transmitter is disabled and put into tri-state. The transmitter input does not have an internal pullup resistor.
Vendor:SSOP-40Package Cooled:PHILIPSD/C:04+
The transmitter is an inverting level translator that con- verts CMOS-logic levels to EIA/TIA-232 compatible lev- els. It guarantees data rates up to 460kbps with worst-case loads of 3kΩ in parallel with 1000pF. When SHDN is driven low, the transmitter is disabled and put into tri-state. The transmitter input does not have an internal pullup resistor.
1. Typical sensitivity data is based on a 10-3 bit error rate (BER), using DC-balanced data. There are two test methods commonly used to measure OOK/ASK receiver sensitivity, the 100% AM test method and the Pulse test method. Sensitivity data is given for both test meth- ods. See Appendix 3.8 in the ASH Transceiver Designers Guide for the details of each test method, and for sensitivity curves for a 2.2 to 3...
Vendor:PHIPackage Cooled:PLCCD/C:04+
1. One million cycle repeatability data is based upon 396 observations with an average repeatability 0.033 dB and a range of 0.093 dB. 2. Repeatability of attenuation values were obtained from tests conducted in a 20 dB attenuator network with a 0 dBm input signal. 3. Relay operates at frequencies higher than 3 GHz with reduced RF performance characteristics. 4. Curves were developed from tests perform...
Vendor:PHILIPSPackage Cooled:DIPD/C:06+
1.1 EMI REDUCTION The COP8SAx family of devices incorporates circuitry that guards against electromagnetic interference an increasing problem in todays microcontroller board designs. Nationals patented EMI reduction technology offers low EMI clock cir- cuitry, gradual turn-on output drivers (GTOs) and internal ICC smoothing filters, to help circumvent many of the EMI issues influencing embedded contr...
Vendor:PHILIPSPackage Cooled:DIP/PLCC
The negative output voltage of the Power Trends PT6900 Series ISRs may be adjusted higher or lower than the factory trimmed pre-set voltage with the addition of a single external resistor. Table 1 gives the allowable adjustment range for each model in the series as Va (min) and Va (max).
Vendor:PHILIPSPackage Cooled:DIP/PLCC
The negative output voltage of the Power Trends PT6900 Series ISRs may be adjusted higher or lower than the factory trimmed pre-set voltage with the addition of a single external resistor. Table 1 gives the allowable adjustment range for each model in the series as Va (min) and Va (max).
Vendor:PHILPSPackage Cooled:PLCC44D/C:07/08+
Vendor:PHILIPSPackage Cooled:PLCC44D/C:06+
Vendor:PHILIPSPackage Cooled:PDIP40D/C:06+
Vendor:PHIPackage Cooled:04+D/C:QFP-M44P
†Notice: Stresses above those listed under Maximum Rat- ings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Expo- sure to maximum rating conditions for extended periods may affect device reliability.
D/C:08+
Vendor:PHIPackage Cooled:PDIP28D/C:9810
The Hynix HY57V281620E(L)T(P) series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V281620E(L)T(P) series is organized as 4banks of 2,097,152 x 16.
Vendor:PHID/C:05+
System level features - SelectRAM+™ hierarchical memory: 16 bits/LUT distributed RAM Configurable 4K-bit true dual-port block RAM Fast interfaces to external RAM - Fully 3.3V PCI compliant to 64 bits at 66 MHz and CardBus compliant - Low-power segmented routing architecture - Full readback ability for verification/observability - Dedicated carry logic for high-speed arithmetic - Efficie...
Vendor:PHIPackage Cooled:SSOP-20PD/C:05+
The MC100ES6139 is a low skew 2/4, 4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB ou...
Vendor:PHILIPSD/C:05+
OUTA, OUTB, OUTC, OUTD: The 4 outputs are 100mA complementary MOS drivers, and are optimized to drive FET driver circuits. OUTA and OUTB are fully complementary, (assuming no programmed delay). They operate near 50% duty cycle and one-half the oscillating frequency. OUTA and OUTB are intended to drive one half-bridge circuit in an external power stage. OUTC and OUTD will drive the other half-bridge an...
Vendor:PHID/C:06+
The TLE214x and TLE214xA devices are high-performance, internally compensated operational amplifiers built using Texas Instruments complementary bipolar Excalibur process. The TLE214xA is a tighter offset voltage grade of the TLE214x. Both are pin-compatible upgrades to standard industry products.
The voltage and current amplifiers have a 3MHz gain bandwidth product to satisfy high performance system requirements. The internal current sense amplifier per- mits the use of a low value current sense resistor, mini- mizing power loss. The oscillator frequency is fixed internally at 100kHz, 200kHz, or 400kHz, depending upon the option selected. The foldback circuit reduces the converter short circu...
The voltage and current amplifiers have a 3MHz gain bandwidth product to satisfy high performance system requirements. The internal current sense amplifier per- mits the use of a low value current sense resistor, mini- mizing power loss. The oscillator frequency is fixed internally at 100kHz, 200kHz, or 400kHz, depending upon the option selected. The foldback circuit reduces the converter short circu...
Vendor:PHILIPSPackage Cooled:QFP0505-32D/C:02+
The OM5170 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the OM5170 will respond with a final acknowledge.
Vendor:PHIPackage Cooled:QFP
Package Cooled:QFPD/C:2000
1) CPD is defined as the value of the ICs internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = C PD x VCC x fIN + ICC/8 (per circuit)
Vendor:PHILIPSPackage Cooled:QFP0707-48D/C:97+
PIN DESCRIPTION This pin controls the gate of an external MOSFET for the AGP linear regulator. Leaving this pin open provides fixed output voltages of the 1.5V and 1.8V for the #3 and #4 linear regulators. When this pin is grounded the reference to the linear regulators are set to 1.26V and therefore the output of the regulators can be programmed to any volt- ages above the 1.26V using: VOUT = 1.26 3 (1 +...
Vendor:PHILIPSPackage Cooled:QFP0707-48D/C:97+
PIN DESCRIPTION This pin controls the gate of an external MOSFET for the AGP linear regulator. Leaving this pin open provides fixed output voltages of the 1.5V and 1.8V for the #3 and #4 linear regulators. When this pin is grounded the reference to the linear regulators are set to 1.26V and therefore the output of the regulators can be programmed to any volt- ages above the 1.26V using: VOUT = 1.26 3 (1 +...
Vendor:PHIPackage Cooled:SSOP-20D/C:N/A
The S3067 transceiver implements SONET/SDH and WDM serialization/deserialization, and transmis- sion functions. The block diagram in Figure 4 shows the basic operation of the chip. This chip can be used to implement the front end of WDM equipment, which consists primarily of the serial transmit inter- face and the serial receive interface. The chip handles all the functions of these two elements, in-...
• Efficiencies up to 88 % • 50 W/in³ Power Density • Output Over-Current Protection (Non-Latching, Auto-Reset) • Safety Agency Approvals (Pending): UL/cUL60950, EN60950, VDE • Point-of-Load Alliance (POLA) Compatible
Vendor:PHILIPSPackage Cooled:01+D/C:2380
This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of circuits described. No patent licences are implied Hyundai Semiconductor Rev.00 / Sep.97
Vendor:PHIPackage Cooled:QFP-48D/C:0129+
A single sampling sequence is taken during every inter- rupt routine. The accumulated energy to that point, adjusted by Cg, is compared with the values for D x C, as well as a fraction of the D xC equivalent to 1/3200 kWh. Prior to calibration, the application uses a value of 200 for both C and Cg. After calibration, Cg may change to compensate for gain inaccuracies; C remains at 200. An increment o...
Vendor:PHIPackage Cooled:QFP-48D/C:0129+
A single sampling sequence is taken during every inter- rupt routine. The accumulated energy to that point, adjusted by Cg, is compared with the values for D x C, as well as a fraction of the D xC equivalent to 1/3200 kWh. Prior to calibration, the application uses a value of 200 for both C and Cg. After calibration, Cg may change to compensate for gain inaccuracies; C remains at 200. An increment o...
Vendor:PHILIPSPackage Cooled:BGAD/C:06+
Notes: 1. CX1 must be placed within 0.7 cm of the HSDL-2300 to obtain optimum noise immunity. 2. In environments with noisy power supplies, supply rejection can be enhanced by including CX2 as shown in Application Circuit Diagram, Figure 1. 3. For interface between 5 V endec and HSDL-2300, level shifters or external protection circuits are recommended at all input pins; MD0, MD1, TXD, and FIR_SEL.
Vendor:PHILIPSPackage Cooled:BGAD/C:06+
Notes: 1. CX1 must be placed within 0.7 cm of the HSDL-2300 to obtain optimum noise immunity. 2. In environments with noisy power supplies, supply rejection can be enhanced by including CX2 as shown in Application Circuit Diagram, Figure 1. 3. For interface between 5 V endec and HSDL-2300, level shifters or external protection circuits are recommended at all input pins; MD0, MD1, TXD, and FIR_SEL.
Vendor:PHILIPSPackage Cooled:QFP100D/C:06+
The OM5183H IC combines a Dual synchronous Buck controller and a linear regulator controller, providing a cost-effective, high performance and flexible solution for multi-output applications. The Dual synchronous con- troller can be configured as 2-independent or 2-phase controller. In 2-phase configuration, the OM5183H provides a programmable current sharing which is ideal when the output power exceeds any ...
Forward-Current Transfer Ratio IC = 1.0 Adc, VCE = 4.0 Vdc IC = 20 Adc, VCE = 4.0 Vdc IC = 50 Adc, VCE = 4.0 Vdc Collector-Emitter Saturation Voltage IC = 20 Adc, IB = 2.0 Adc IC = 50 Adc, IB = 10 Adc Base-Emitter Saturation Voltage IC = 20 Adc, IB = 2.0 Adc
Vendor:PHILIPSPackage Cooled:QFP64D/C:01+
The UC3874 family of synchronous step-down (Buck) regulators provides high efficiency power conversion from an input voltage range of 4.5 to 36 volts. The UC3874 is tailored for battery powered applications such as laptop computers, consumer products, communications systems, and aerospace which demand high performance and long battery life. The synchronous regulator replaces the catch diode in the standa...