PCA84C122BT/215

Vendor:PHILIPSPackage Cooled:SMDD/C:08+

These N-Channel power MOSFETs are manufactured using the innovative UltraFET™ process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in...

PCA84C122BT245

† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.

PCA84C122BT9

PCA84C222AP/014

Vendor:PHIPackage Cooled:PDIP-24PD/C:6+

The PCA84C222AP/014 series is a family of voltage referenced shunt regulators. The main application of these products is in voltage regulators that provide a variable output voltage. The PCA84C222AP/014 series products are provided in a wide range of packages; TO-92 insertion mounting packages and MPAK-5 (5 pin), MPAK (3 pin), UPAK surface mounting packages are available. The on-chip high-precision reference...

PCA84C222AT

Package Cooled:06+D/C:800

• 2.1 MHz Clock Rate • Low power CMOS Active current less than 3.0 mA (5.5V) Standby current less than 10 µA (5.5V) • Low-voltage Operation IS25C64-3 & IS25C32-3 (Vcc = 2.5V to 5.5V) IS25C64-2 & IS25C32-2 (Vcc = 1.8V to 5.5V) • Block Write Protection Protect 1/4, 1/2, or Entire Array • 32 byte page write mode • Serial Peripheral Interface...

PCA84C222AT042

PCA84C222BT

Vendor:PHILPackage Cooled:00+D/C:95/96+

The TLV2262 and TLV2264 are dual and quad low voltage operational amplifiers from Texas Instru- ments. Both devices exhibit rail-to-rail output performance for increased dynamic range in single or split supply applications. The TLV226x family offers a compromise between the micro- power TLV225x and the ac performance of the TLC227x. It has low supply current for battery- powered applications, while...

PCA84C222BT/054

Vendor:PHLILPSPackage Cooled:SO20D/C:00+

NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage rating...

PCA84C422BT/905

Port 2: Is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 2 pins that are being pulled low externally will be a source of current (IIL, see section "Electrical Characteristic") because of the internal pull-ups. Port 2 emits the high-order address byt...

PCA84C440P/128

Vendor:PHILIPSPackage Cooled:DIPD/C:1994

Figure 4 illustrates the differential or gauge configuration in the unibody chip carrier (Case 344). A silicone gel isolates the die surface and wire bonds from the environment, while allowing the pressure signal to be transmitted to the silicon diaphragm. The MPX53/MPXV53GC series pressure sensor operating

PCA84C440P/401

All part numbers end with a place code, designating the silicon-die revision. Reference information available on request. Example: HYS 64D32020GDL-8-A, indicating Rev.A die are used for DDR-SDRAM components. The Compliance Code which is printed on the module labels describes the speed sort class (f.e. PC2100), the latencies (f.e. 20330 means CAS latency = 2, trcd latency = 3 and trp latency = 3) and the ...

PCA84C444P/504

Vendor:PHILPackage Cooled:DIP-42D/C:94+

Inputs Are TTL-Voltage Compatible Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data True Data Paths High-Current 3-State Outputs Can Drive up to 15 LSTTL Loads Package Options Include Plastic Small-Outline (DW) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs

PCA84C444P/504

Vendor:PHILD/C:94+

Inputs Are TTL-Voltage Compatible Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data True Data Paths High-Current 3-State Outputs Can Drive up to 15 LSTTL Loads Package Options Include Plastic Small-Outline (DW) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs

PCA84C640-016

Vendor:PHILIPSPackage Cooled:DIP

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1 AVDD = DRVDD = 3.3 V, IO = 3.5 mA, RL = 100 Ω. (1) All LVDS and CMOS specifications are characterized, but not tested at production.

PCA84C640-016

Vendor:PHILIPSPackage Cooled:DIP

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1 AVDD = DRVDD = 3.3 V, IO = 3.5 mA, RL = 100 Ω. (1) All LVDS and CMOS specifications are characterized, but not tested at production.

PCA84C640-019

Vendor:PHILIPSPackage Cooled:DIP

Addresses and data needed for the programming and erase operations are internally latched during write cycles, and the host system can detect completion of a program or erase operation by reading the DQ[7] (Data# Polling) and DQ[6] (toggle) status bits. Reading data from the device is similar to reading from SRAM or EPROM de- vices. Hardware data protection measures include a low VCC detector that ...

PCA84C640-019

Vendor:PHILIPSPackage Cooled:DIP

Addresses and data needed for the programming and erase operations are internally latched during write cycles, and the host system can detect completion of a program or erase operation by reading the DQ[7] (Data# Polling) and DQ[6] (toggle) status bits. Reading data from the device is similar to reading from SRAM or EPROM de- vices. Hardware data protection measures include a low VCC detector that ...

PCA84C640-030

may be accessed by hardware or software operation. The hardware operation mode can be used by an external pro- grammer to identify the correct programming algorithm for the Atmel product. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49BV/LV001(N)(T) features DATA polling ...

PCA84C640-049

Vendor:PHILIPS

At the low state of the clock a RESET signal is generated which clears all the shift registers for the next set of data. The shift registers are static mas- ter-slave configurations. There is no clear for the master portion of the first shift register, thus allow- ing continuous operation. There must be a complete set of 36 clocks or the shift registers will not clear. When power is first applied t...

PCA84C640P

Package Cooled:DIP

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 854058AGwww.icst.com/products/hiperclocks.htmlREV. A APRIL 8, 2004

PCA84C640P

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 854058AGwww.icst.com/products/hiperclocks.htmlREV. A APRIL 8, 2004

PCA84C640P/016

Vendor:PHILPackage Cooled:DIP-42D/C:03+

PCA84C640P/037

Vendor:PHIPackage Cooled:N/AD/C:9+

The upper ESD diodes for the R, G and B channels are connected to a separate supply rail (VRGB) to facilitate interfacing to graphics controller ICs with low voltage supplies. The remaining channels are connected to the main 5V rail (VCC). The lower diodes for the R, G and B channels are also connected to a dedicated ground pin (GNDA) to minimize crosstalk due to common ground impedance.

PCA84C640P-030

Vendor:PHILIPSPackage Cooled:DIPD/C:97+

Make connection to B side with pink wire for Light ON Make connection to v side with pink wire for Dark ON Note: When switching a power source, make ground connection to the frame ground termi- nal or to the ground terminal. This will assure more stable operation.

PCA84C640P-030

Vendor:PHILIPSPackage Cooled:DIPD/C:97+

Make connection to B side with pink wire for Light ON Make connection to v side with pink wire for Dark ON Note: When switching a power source, make ground connection to the frame ground termi- nal or to the ground terminal. This will assure more stable operation.

PCA84C641

The SPT1175 operates from a single +5.0 V power supply and has an internal voltage reference which eliminates the need for external reference circuitry. All digital inputs are CMOS compatible and the tri-state outputs are TTL-compat- ible. The SPT1175 is ideal for most video and image pro- cessing applications that require low power dissipation and low cost. The SPT1175 is available in 24-lead plastic ...

PCA84C641-076

PCA84C641P/030

Vendor:PHIPackage Cooled:DIP-42D/C:94+

PCA84C641P/06

PCA84C641P/068

Vendor:PHILPackage Cooled:DIP-42D/C:03+

Reading from the device is accomplished by taking Chip En- able (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table at the back of this data sheet for...

PCA84C822AT

Vendor:PHIPackage Cooled:STKD/C:2005+

A data cache is also used on the host bus to deliver the 32 /16 bits burst read on the host data port up to 4 data transfers in a single cycle. Two hand shake signals to communicate to the host bus interface during the data port transfer are simple and fast for the system integra- tor. An intelligent built-in SRAM bus arbiter will manage all SRAM access requests from the host bus access, the transmit ...

PCA84C822AT/010

Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

PCA84C822AT/026

The K1S1616B1A is fabricated by SAMSUNGs advanced CMOS technology using one transistor memory cell. The device supports Industrial temperature range and 48 ball Chip Scale Package for user flexibility of system design. The device also supports dual chip selection for user interface.

PCA84C822AT/031

Vendor:PHILIPSPackage Cooled:SOPD/C:1997

s 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package. s 16 kB on-chip Static RAM. s 128/256 kB on-chip Flash Program Memory. 128-bit wide interface/accelerator enables high speed 60 MHz operation. s In-System Programming (ISP) and In-Application Programming (IAP) via on-chip boot-loader software. Flash programming takes 1 ms per 512 byte line. Single sector or full chip erase takes 400 ms. ...

PCA84C822AT/105

The Secured Silicon Sector is an extra 256 byte sec- tor capable of being permanently locked by AMD or customers. The Secured Silicon Customer Indicator Bit (DQ6) is permanently set to 1 if the part has been customer locked, permanently set to 0 if the part has been factory locked, and is 0 if customer lockable. This way, customer lockable parts can never be used to re- place a factory locked part.

PCA84C822AT-010

Vendor:PHILIPSPackage Cooled:SOPD/C:2008+

The IS41C4400x and IS41LV4400x are CMOS DRAMs optimized for high-speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 11 or 12 address bits. These are entered 11 bits (A0-A10) at a time for the 2K refresh device or 12 bits (A0-A11) at a time for the 4K refresh device. The row address is latched by the Row Address Strobe (RAS). The column add...

PCA84C822AT-010

Vendor:PHILIPSD/C:2008+

The IS41C4400x and IS41LV4400x are CMOS DRAMs optimized for high-speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 11 or 12 address bits. These are entered 11 bits (A0-A10) at a time for the 2K refresh device or 12 bits (A0-A11) at a time for the 4K refresh device. The row address is latched by the Row Address Strobe (RAS). The column add...

PCA84C822AT1010

Vendor:N/APackage Cooled:PHID/C:06+

Data sheet information is generally presented in the following sequence: • Device description • Absolute maximum ratings • Thermal data - thermal resistances • Characteristics, switching characteristics • Electrical characteristics • Dimensions (mechanical data) Additional information on device performance is pro- vided where necessary.

PCA84C840P/008

PCA84C840P/054

Vendor:PHILIPSPackage Cooled:9449D/C:DIP-42

Note 2: CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at no output loading and operating at 50% duty cycle. (See Figure 2 .) CPD is related to ICCD dynamic operating current by the expression: ICCD = (CPD) (VCC) (fIN) + (ICC static)

PCA84C841/177

Vendor:PHIPackage Cooled:DIP-42

The 72-Mbit Direct Rambus DRAMs (RDRAM®) are extremely high-speed CMOS DRAMs organized as 4M words by 18 bits. The use of Rambus Signaling Level (RSL) technology permits 600MHz to 800MHz transfer rates while using conventional system and board design technologies. Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two bytes (10ns per sixteen bytes).

PCA84C841-177

Vendor:PHILIPSPackage Cooled:DIP42

Figure 3 shows the proper connection of the VRE304 series voltage references with the optional trim resistor for initial error and the optional capacitor for noise reduction. The VRE304 reference has the ground terminal brought out on two pins (pin 4 and pin 7) which are connected together internally. This allows the user to achieve greater accuracy when using a socket. Voltage references have a volt...

PCA84C841P

Vendor:300

The Si9160 Controller for RF Power Amplifier Boost Converter is a fixed-frequency, pulse-width-modulated power conversion controller designed for use with the Si6801 application specific MOSFET. The Si9160 and the Si6801 are optimized for high efficiency switched-mode power conversion at 1 MHz and over. The device has an enable pin which can be used to put the converter in a low-current mode compatible...

PCA84C841P/076

Vendor:PHILIPSPackage Cooled:DIP42D/C:94+

The PCA84C841P/076 is the third generation of Gigabit Ethernet transceivers from Texas Instruments combining high port density and ultralow power in a small form-factor footprint. The PCA84C841P/076 provides for high-speed full-duplex point-to-point data transmissions based on the IEEE 802.3z 1000-Mbps Ethernet specification. The PCA84C841P/076 supports data rates from 1.0 Gbps through 1.3 Gbps.

PCA84C841P/086

Vendor:飞利蒲Package Cooled:N/AD/C:9+

Port 0: Port 0 is an 8-bit open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high- impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pullups when emitting 1s.

PCA84C841P/259

Vendor:飞利蒲Package Cooled:N/AD/C:9+

This low-cost accessory board provides an easy way of powering all DMS- 30PC-X-RL (red low-power models only), as well as all DMS-30LCD and DMS- 40LCD (non-backlit, +5V-powered models only) panel meters from 100-264Vac (50/60Hz). The on-board AC/DC converter provides an isolated +5Vdc to power the meters electronics, while providing 1500Vac isolation between the AC supply and the input signal being measu...

PCA84C844-256

Vendor:PHILIPSPackage Cooled:DIP42

Power MOSis a new generation of high voltage N-Channel enhancement mode power MOSFETs. This new technology minimizes the JFET effect, increases packing density and reduces the on-resistance. Power MOS V® also achieves faster switching speeds through optimized gate layout.

PCA84C844-256

Vendor:PHILIPSPackage Cooled:DIP42

Power MOSis a new generation of high voltage N-Channel enhancement mode power MOSFETs. This new technology minimizes the JFET effect, increases packing density and reduces the on-resistance. Power MOS V® also achieves faster switching speeds through optimized gate layout.

PCA84C844-504

PCA84C844P

Vendor:N/AD/C:0

3. Zener voltage is measured with the device junction in thermal equilibrium with an ambient temperature of 25C. 4. Zener Impedance Derivation ZZT and ZZK are measured by dividing the AC voltage drop across the device by the AC current applied. The specified limits are for IZ(ac) = 0.1 IZ(dc) with the ac frequency = 60 Hz.

PCA84C844P/107V1.5

Vendor:PHILIPSPackage Cooled:DIPD/C:1994

In most applications the input coupling capacitors are 0.1µF. The Y and C inputs typically sink 1µA of current during active video, which normally tilts a horizontal line by 2mV at the Y out- put. During sync, the clamp restores this leakage current by sourcing an average of 20µA over the clamp interval. Any change in the coupling capacitor values will affect the amount of tilt per lin...

PCA84C844P/172

Vendor:PHILIPSPackage Cooled:DIPD/C:1995

Each transmit channel accepts parallel characters in an Input Register, encodes each character for transport, and converts it to serial data. Each receive channel accepts serial data and converts it to parallel data, decodes the data into characters, and presents these characters to an output register. Figure 1 illustrates typical connections between independent host sys- tems and corresponding CYP15G0...

PCA84C844P/208

Vendor:300

Ground pin. This pin provides a ground for the controller circuitry and the internal power switch. This pin is internally connected to the metal pad of the package to provide an addition- al ground connection as well as an effective means of dissipating heat.

PCA84C844P/221

Vendor:TAIWAN

The first character of the part number suffix determines the device operating temperature range. Suffix EC is for the automotive and industrial temperature range of -40C to +85C. Suffix LC is for the automotive and military temperature range of -40C to +150C. Three package styles provide a magnetically optimized package for most applications. Suffix CLT is a miniature SOT-89/TO-243AA transistor package for ...

PCA84C844P/256

Vendor:300

Active-Low, Manual Reset Input. When MR is asserted low, RESET is asserted low, the internal watchdog timer is reset to zero, and WDPO is reset to high impedance (open drain). After the rising edge of MR, RESET is asserted for at least 100ms. Leave MR unconnected or connect to VCC if unused.

PCA84C844P/258

Vendor:PHIPackage Cooled:DIP-42D/C:98+

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 210 mV at an output current of 2 A for the TPS75x33Q) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 75 µA over the full range of output current, 1 ...

PCA84C844P/258

Vendor:PHIPackage Cooled:DIP-42D/C:98+

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 210 mV at an output current of 2 A for the TPS75x33Q) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 75 µA over the full range of output current, 1 ...

PCA84C844P/270S1

Vendor:PHILIPSPackage Cooled:DIPD/C:00+

(3) Static Electricity Static electricity or surge voltage damages the LEDs. It is recommended that a wrist band or an anti-electrostatic glove be used when handling the LEDs. All devices, equipment and machinery must be properly grounded. It is recommended that measures be taken against surge voltage to the equipment that mounts the LEDs. When inspecting the final products in which LEDs were assembl...

PCA84C846P/025

Vendor:PHIPackage Cooled:DIP

The bq4847 can generate other in- terrupts based on a clock alarm con- dition or a periodic setting. The alarm interrupt can be set to occur from once per second to once per month. The alarm can be made ac- tive in the battery-backup mode to serve as a system wake-up call. For interrupts at a rate beyond once per second, the periodic interrupt can be programmed with periods of 30.5µs to 500ms.

PCA84C846P/025

Vendor:PHIPackage Cooled:DIP

The bq4847 can generate other in- terrupts based on a clock alarm con- dition or a periodic setting. The alarm interrupt can be set to occur from once per second to once per month. The alarm can be made ac- tive in the battery-backup mode to serve as a system wake-up call. For interrupts at a rate beyond once per second, the periodic interrupt can be programmed with periods of 30.5µs to 500ms.

PCA84C882-025

PCA8510

Vendor:PHILIPS

These N-Channel power MOSFETs are manufactured using the innovative UltraFET® process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in a...

PCA8510P003

Vendor:phPackage Cooled:phD/C:dc92

The MAX 7000 family of high-density, high-performance PLDs is based on Alteras second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in...

PCA8510T

Vendor:PHIPLSD/C:05+

CMOS Technology Low Power Consumption 4-Bit or 8-Bit MPU Interface High Speed MPU Interface: 2MHz (VDD =5V) 80 x 8-Bit Display RAM (80 characters max.) Auto Reset Function 5 x 8 and 5 x 10 Dot Matrix Built-in Oscillator with External Resistors Programmable Duty Cycle: - 1/8 Duty: (1 Display Line, 5 x 8 Dots with Cursor) - 1/11 Duty: (1 Display Line, 5 x 10 Dots with Cursor) - 1/16 Duty: (2 Display Lines,...

PCA8510T/006

Vendor:PHILIPS

PCA8515

Package Cooled:06+D/C:800

SWITCHING PARAMETERS Qg(4.5V) Total Gate Charge QgsGate Source Charge QgdGate Drain Charge tD(on)Turn-On DelayTime trTurn-On Rise Time tD(off)Turn-Off DelayTime tfTurn-Off Fall Time trrBody Diode Reverse Recovery Time QrrBody Diode Reverse Recovery Charge

PCA8515

Package Cooled:SOPD/C:800

SWITCHING PARAMETERS Qg(4.5V) Total Gate Charge QgsGate Source Charge QgdGate Drain Charge tD(on)Turn-On DelayTime trTurn-On Rise Time tD(off)Turn-Off DelayTime tfTurn-Off Fall Time trrBody Diode Reverse Recovery Time QrrBody Diode Reverse Recovery Charge

PCA8515-009

Vendor:PHILIPSPackage Cooled:SOPD/C:05+

The PCA8515-009 incorporates internal matching on each RF, IF, and LO port to enhance ease of use and to reduce the number of external components required. The IF and LO ports can be driven differential or single ended. Each broadband port has been designed to minimize perfor- mance degradation while operating into highly reactive components such as PCA8515-009AW filters.

PCA8515T

Vendor:PHID/C:05+

Third Order Intermodulation Distortion (VDD = 28 Vdc, Pout = 33 W Avg., IDQ = 1300 mA, f1 = 2112.5 MHz, f2 = 2122.5 MHz and f1 = 2157.5 MHz, f2 = 2167.5 MHz; IM3 measured over 3.84 MHz BW at f1 - 10 MHz and f2 +10 MHz referenced to carrier channel power.)

PCA8515T

Vendor:PHID/C:05+

Third Order Intermodulation Distortion (VDD = 28 Vdc, Pout = 33 W Avg., IDQ = 1300 mA, f1 = 2112.5 MHz, f2 = 2122.5 MHz and f1 = 2157.5 MHz, f2 = 2167.5 MHz; IM3 measured over 3.84 MHz BW at f1 - 10 MHz and f2 +10 MHz referenced to carrier channel power.)

PCA8515T/009

Each DCP can be used as a three-terminal potentio- meter or as a two terminal variable resistor in a wide variety of applications including the programming of bias voltages, the implementation of ladder networks, and three resistor programmable networks.

PCA8516P/028

Package Cooled:DIP

ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PCA8516P/028

Package Cooled:DIP

ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PCA8516T/039

Vendor:PHIPackage Cooled:SOP/24D/C:99+

hysteresis losses in an inductor, as well as ESR losses in capacitors, are the limiting factors in going to higher operating frequencies. Moreover, the effective impedance of capacitors and inductors at higher operating frequencies are dominated by ESL, ESR, and interlayer capacitance, which causes inductors to behave more like capacitors and capacitors to behave more like inductors.

PCA8521

Vendor:PHILIPSPackage Cooled:SOP20

Output of the error amplifier for compensation Analog ground return pin Input to the current limit comparator Inverting input to the error amplifier Non-inverting input to the error amplifier High current totem pole output A of the on-chip drive stage. High current totem pole output B of the on-chip drive stage. Ground return pin for the output driver stage Non-inverting input to the PWM comparator...

PCA8521BT/

Vendor:PHID/C:05+

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 874004AGwww.icst.com/products/hiperclocks.htmlREV. A JANUARY 21, 2005

PCA8521BT/003/050/051

Vendor:PHIPackage Cooled:SOP20WD/C:98+

PLL bandwidth is affected by loop filter component values, Mfec and Mfin values, and the PLL Loop Constants listed in AC Characteristics on pg. 8. The various Non-FEC ratio settings can be used to actively change PLL loop bandwidth in a given application. See FEC PLL Ratio Dividers Look-up Table (LUT) on pg. 3. PLL Simulator Tool Available A free PC software utility is available on the ICS website ...

PCA8521BT/007

Vendor:PHPackage Cooled:SOPD/C:98

NOTES: 1. Dimensions are in inches. 2. Metric equivalents are given for general information only. 3. Refer to rules for dimensioning semiconductor product outlines included in Publication No. 95. 4. Lead number 4 and 8 omitted on this variation. 5. Beyond r, TW must be held to a minimum length of .021 inch (.53 mm). 6. TL measured from maximum CD. 7. Details of outline in this zone optional.

PCA8521BT/007S1

Vendor:PHILPackage Cooled:00+D/C:06+

An additional toggle bit is available on I/O2 which can be used in conjunction with the toggle bit which is available on I/O6. While a sector is erase suspended, a read or a pro- gram operation from the suspended sector will result in the I/O2 bit toggling. Please see Status Bit Table for more details.

PCA8521BT/025

Vendor:PHPackage Cooled:SOPD/C:98

PCA8521BT/026

Vendor:PHPackage Cooled:SOPD/C:98

Drive Up To 15 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 22 ns 6-mA Output Drive at 5 V Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatible Eight D-Type Flip-Flops in a Single Package Full Parallel Access for Loading

PCA8521BT/034

Vendor:PHILPackage Cooled:SOPD/C:06+

In order to conserve power, the OTG Supplement allows an A-device to leave VBUS turned off when the bus is not being used. Then, when the B-device wants to use the bus, it follows the SRP pulsing protocol to request that the A-device supply power to VBUS. In the configuration in Figure 1, the OTG Host would be considered the A-device, and the USB20H04 Hub would be considered the B-device.

PCA8521BT/035

Vendor:PHPackage Cooled:SOPD/C:98

WR 17 WRITE-a low-to-high transition on this input, when CHIP SELECT is low, causes data to be written to the selected IXDP610 latch. If SELECT is low, the data is written to the pulse width latch. If SELECT is high, the data is written to the control latch.

PCA8521BT/037

Vendor:PHILPackage Cooled:SOPD/C:06+

This pin adjusts the peak current limit of the Sense FET. The feedback 0.9mA current source is diverted to the parallel combination of an internal 2.8kΩ resistor and any external resistor to GND on this pin to determine the peak current limit. If this pin is tied to Vcc or left floating, the typical peak cur- rent limit will be 0.7A.

PCA8521BT/04051

The Sequence Generator is a block oriented address gener- ator. This means that the desired address sequence is sub- divided into one or more address blocks, each containing a user defined number of addresses. User supplied configura- tion data determines the number of address blocks and the characteristics of the address sequence to be generated.

PCA8521BT/044

Vendor:PHIPackage Cooled:7.2mm

The output of the SAW filter drives amplifier RFA1. This amplifier in- cludes provisions for detecting the onset of saturation (AGC Set), and for switching between 35 dB of gain and 5 dB of gain (Gain Se- lect). AGC Set is an input to the AGC Control function, and Gain Se- lect is the AGC Control function output. ON/OFF control to RFA1 (and RFA2) is generated by the Pulse Generator & RF Amp Bias function....

PCA8521BT/044

Vendor:PHIPackage Cooled:7.2mm

The output of the SAW filter drives amplifier RFA1. This amplifier in- cludes provisions for detecting the onset of saturation (AGC Set), and for switching between 35 dB of gain and 5 dB of gain (Gain Se- lect). AGC Set is an input to the AGC Control function, and Gain Se- lect is the AGC Control function output. ON/OFF control to RFA1 (and RFA2) is generated by the Pulse Generator & RF Amp Bias function....

PCA8521BT/047

Package Cooled:SOP-20

fOSC(tc)Oscillator frequency over line and temperature Trimmed for 360 kHz (1) Ensured by design. Not production tested. (2) Maximum 450-kHz frequency can be achieved when both channels are enabled. (3) 270 kHz is the default frequency during start-up for both channels. (4) See Table 1. (5) See PWM detailed description

PCA8521BT/052

Vendor:PHPackage Cooled:SOPD/C:98

Receive data. These outputs carry 10-bit parallel data output from the transceiver to the protocol layer. The data is referenced to terminals RBC0 and RBC1. Received data byte 0, which contains the K28.5 character, is byte aligned to the rising edge of RBC1. RD0 is the first bit received.

PCA8521BT/055

Vendor:PHPackage Cooled:SOPD/C:98

SG2 applied V60, SG6 (NTSC) applied to V9. Decrease the input amplitude until the killer is turned on, and measure the input attenuation. SG2 applied V60, SG6 (PAL) applied to V9. Decrease the input amplitude until the killer is turned on, and measure the input attenuation.

PCA8521BT/067

Vendor:PHILIPSPackage Cooled:NULLD/C:NULL

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.

PCA8521BT/070

Notes: 1. Standard deviation number is based on measurement of at least 500 parts from three non-consecutive wafer lots during the initial characterization of this product and is intended to be used as an estimate for distribution of the typical specification. 2. IIP3 test condition: FRF1 = 1.91 GHz, FRF2 = 1.89 GHz with input power of -10 dBm per tone and LO power = -3 dBm at LO frequency FLO= 1.7 GHz. 3. ...

PCA8521BT/71S1

Vendor:PHILIPSPackage Cooled:SMD20D/C:08+

1. In Figure 1, test circuit electrolytic capacitors C1 and C2 are 100µF and have 0.2Ω maximum ESR. Higher ESR levels may reduce efficiency and output voltage. 2. The output resistance is a combination of the internal switch resistance and the external capacitor ESR. For maximum voltage and efficiency keep external capacitor ESR under 0.2Ω. 3. FOSC is tested with COSC = 100pF to minimiz...

PCA8521BT003

PCA8521BT00351

clock stream is corrupted during a transmission. In these two modes the DATA and CLK pins should not be clocked to re- duce noise in the captured pressure or temperature data. Any change in the DAR contents should be done during the Standby or Output Read Modes. Both the serial bit counter and the state of the DAR are un- defined following power up of the device. The serial bit count- er can be rese...

PCA8521BT017

PCA8521BT050

One Instruction/Clock Execution Core Clock Rate is 2x the Bus Clock Load/Store Programming Model Sixteen 32-Bit Global Registers Sixteen 32-Bit Local Registers (8 sets) Nine Addressing Modes User/Supervisor Protection Model Two-Way Set Associative Instruction Cache 80960JD - 4 Kbyte Programmable Cache Locking Mechanism Direct Mapped Data Cache 80960JD - 2 Kbyte Write Through Operation On-Ch...

PCA8521BT058

PCA8521BT067

500 Volt Motor Supply Voltage 10 Amp Output Switch Capability 100% Duty Cycle High Side Conduction Capable Shoot-Through/Cross Conduction Protection Hall Sensing and Commutation Circuitry on Board "Real" Four Quadrant Torque Control Capability Good Accuracy Around the Null Torque Point Isolated Package Design for High Voltage Isolation Plus Good Thermal Transfer 60/ 120º Phasing Selectable

PCA8521FT

Vendor:PHIPackage Cooled:SOP16D/C:00+

All voltages are referenced to ground. This is the absolute accuracy of the master oscillator frequency at the default settings. This is the change that is observed in master oscillator frequency with changes in voltage from nominal voltage at TA = +25C. This is the percentage frequency change from the +25C frequency due to temperature at VCC = 3.3V. The dither deviation of the master oscillator frequency i...