P1B27QUALPZ

P1C16C56/JW-S1

Vendor:MICROCHIPD/C:41

P1C16C58A

P1H17400VJ-6

SYSTEM INTERFACE FEATURES Host Port with DMA Capability for Glueless 8- or 16-Bit Host Interface 16-Bit External Memory Interface for up to 16M Words of Addressable Memory Space Three Full-Duplex Multichannel Serial Ports, with Support for H.100 and up to 128 TDM Channels with A-Law and -Law Companding Optimized for Telecom- munications Systems Two SPI-Compatible Ports with DMA Support UART Por...

P1H17405D7-6

The P1H17405D7-6 is a three-terminal low power voltage de- tector implemented in CMOP1H17405D7-6 technology. It detects a particular fixed voltage 2.2V. The voltage detector con- sists of a high-precision and low power consumption standard voltage source, a comparator, hysteresis cir- cuit, and an output driver. CMOP1H17405D7-6 technology ensures low power consumption.

P1H17405D7-6

The P1H17405D7-6 is a three-terminal low power voltage de- tector implemented in CMOP1H17405D7-6 technology. It detects a particular fixed voltage 2.2V. The voltage detector con- sists of a high-precision and low power consumption standard voltage source, a comparator, hysteresis cir- cuit, and an output driver. CMOP1H17405D7-6 technology ensures low power consumption.

P1L3N-K

D/C:袋TO-92

P1MD1T1B01M10QIN-1

P1MS1T2B04M70QIN

P1N1(11OSW)

Vendor:INFINEONPackage Cooled:PQFP-44D/C:06+

The HAL 805 features a temperature-compensated Hall plate with choppered offset compensation, an A/D converter, digital signal processing, a D/A converter with output driver, an EEPROM memory with redun- dancy and lock function for the calibration data, a serial interface for programming the EEPROM, and protection devices at all pins. The internal digital signal processing is of great benefit because...

P1N3W117SIP-18

P1S60F1020C7

P1T1E1903A

Vendor:availPackage Cooled:OTAXD/C:06+

Continuous Drain Current, VGS @ 5.0V Continuous Drain Current, VGS @ 5.0V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 screw.

P1T2B5303A-07

Vendor:ATD/C:08+

BVDSSDrain-to-Source Breakdown Voltage ∆BV DSS/∆T J Temperature Coefficient of Breakdown Voltage RDS(on)Static Drain-to-Source On-State Resistance VGS(th)Gate Threshold Voltage g fsForward Transconductance IDSSZero Gate Voltage Drain Current

P1T2B5309A-01

Vendor:ATD/C:08+

The maximum peak input current capability is dependent on the ambient temperature, improving as the temperature is reduced. Peak current curves are shown for ambient temperatures of 25oC and 105oC and a 15V power supply condition. The safe operating range of the transient peak current should be limited to no more than 75% of the measured overstress level for any given pulse width as shown in the curv...

P1XV3.0

Vendor:STPackage Cooled:QFP

For example a designer who needs a 14-bit accurate data acquisition system over the industrial temperature range (-40C to +85C), will need a voltage reference with a temperature coefficient (TC) of 1.0ppm/C if the reference is allowed to contribute an error equivalent to 1LSB. Figure 3 shows the required reference TC vs. T change from 25C for resolution ranging from 8 bits to 20 bits.

P1Z9ACR900W

Vendor:PRXPackage Cooled:NEW

Bidirectional 8-bit input/output port. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options). The PB can be used as analog input of the analog to digital converter (determined by options). Falling edge wake-up options: PB4, PB7

P2.5/5-10J2

P-2000-501G-15BN

Vendor:COPALPackage Cooled:SALE--STOCK!!D/C:08+

P2000SAL

Vendor:STPackage Cooled:DO214AAD/C:08+

Two-byte instruction can be referenced by using a REF instruction (An exception is XCH A, DA). If the MSB value of the first one-byte instruction in the reference area is 0, the instruction cannot be referenced by a REF instruction. Therefore, if you use REF to reference two 1-byte instruction stored in the reference area, specific combinations must be used for the first and second 1-byte instruction. These ...

P2000SALRP

Vendor:LF(TEC)Package Cooled:DO-214D/C:06+

Complete Power Management Solution for USB Bus-Powered Peripherals 3.3-V 200 mA Low-Dropout Voltage Regulator With Enable 3.3-V 340-mΩ (Typ) High-Side MOSFET 5-V 340-mΩ (Typ) High-Side MOSFET Independent Thermal- and Short-Circuit Protection for LDO and Each Switch 2.9-V to 5.5-V Operating Range CMOS- and TTL-Compatible Enable Inputs 75-µA (Typ) Supply Current Available in 8-Pin MSOP (P...

P2000SALRP

Vendor:LF(TEC)Package Cooled:DO-214D/C:06+

Complete Power Management Solution for USB Bus-Powered Peripherals 3.3-V 200 mA Low-Dropout Voltage Regulator With Enable 3.3-V 340-mΩ (Typ) High-Side MOSFET 5-V 340-mΩ (Typ) High-Side MOSFET Independent Thermal- and Short-Circuit Protection for LDO and Each Switch 2.9-V to 5.5-V Operating Range CMOS- and TTL-Compatible Enable Inputs 75-µA (Typ) Supply Current Available in 8-Pin MSOP (P...

P2000SARP

Vendor:20008Package Cooled:Teccor/LittelfuseD/C:N/A

The joint TLB also contains information to control the cache coher- ency protocol for each page. Specifically, each page has attribute bits to determine whether the coherency algorithm is uncached, non-coherent write-back, non-coherent write-through write-allocate or non-coherent write-through no write-allocate. Non-coherent write-back is typically used for both code and data on the RC4700; however, har...

P2000SB

Vendor:20008Package Cooled:06+D/C:N/A

Note 7: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).

P2000SBL

Vendor:STPackage Cooled:06+D/C:08+

The configuration bits work by acting as control inputs for the multiplexers in the macrocell. There are four mul- tiplexers: a product term input, an enable select, an out- put select, and a feedback select multiplexer. SG1 and SL0x are the control signals for all four multiplexers. In MC0 and MC7, SG0 replaces SG1 on the feedback mul- tiplexer. This accommodates CLK being the adjacent pin for MC7 an...

P2000SBLRP

Vendor:LF(TEC)Package Cooled:DO-214D/C:06+

The passive loop filter connected to Pin LF is designed for a loop bandwidth of BLoop = 100 kHz. This value for BLoop exhibits the best possible noise performance of the LO. Figure 2 shows the appropriate loop filter components to achieve the desired loop bandwidth. If the filter components are changed for any reason, please note that the maximum capacitive load at Pin LF is limited. If the capacitive load...

P2000SBMC

Vendor:STPackage Cooled:DO214AAD/C:08+

WREN - Set Write Enable Latch The FM25L16 will power up with writes disabled. The WREN command must be issued prior to any write operation. Sending the WREN op-code will allow the user to issue subsequent op-codes for write operations. These include writing the status register and writing the memory.

P2000SBRP

Vendor:20008Package Cooled:Teccor/LittelfuseD/C:N/A

The A8430 incorporates a power switch and feedback sense amplifier to provide a solution with minimum external components. The output current can be set by adjusting a single external sense resistor and can be varied with a voltage or filtered PWM signal when dimming control is required. The high switching frequency of 1.2 MHz allows the use of small inductor and capacitor values.

P2000SBRP

Vendor:20008Package Cooled:Teccor/LittelfuseD/C:N/A

The A8430 incorporates a power switch and feedback sense amplifier to provide a solution with minimum external components. The output current can be set by adjusting a single external sense resistor and can be varied with a voltage or filtered PWM signal when dimming control is required. The high switching frequency of 1.2 MHz allows the use of small inductor and capacitor values.

P2000SC

Vendor:30008Package Cooled:Teccor/LittelfuseD/C:N/A

Widebus  Family Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25C Ioff Supports Partial-Power-Down Mode Operation Supports Mixed-Mode Signal Operation on All Ports (5-V Input and Output Voltages With 3.3-V VCC ) Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 − 2000-V ...

P2000SCL

Vendor:STPackage Cooled:DO214AAD/C:08+

The PALCE29MA16 has 16 macrocells, one for each I/O pin. Each I/O macrocell can be programmed for combinatorial, registered or latched operation (see Fig- ure 2). Combinatorial output is desired when the PAL device is used to replace combinatorial glue logic. Reg- isters and Latches are used in synchronous logic applications. Registers and Latches with product term controlled clocks can also be used ...

P2000SCL

Vendor:STPackage Cooled:06+D/C:08+

The PALCE29MA16 has 16 macrocells, one for each I/O pin. Each I/O macrocell can be programmed for combinatorial, registered or latched operation (see Fig- ure 2). Combinatorial output is desired when the PAL device is used to replace combinatorial glue logic. Reg- isters and Latches are used in synchronous logic applications. Registers and Latches with product term controlled clocks can also be used ...

P2000SCLRP

Vendor:LF(TEC)D/C:06+

Military temperature range Output skew 2.0 ns typical Input to output delay 10 ns Operation from single +5.0V supply 16-lead ceramic DIP Package Outputs wont load line when VCC = 0V Output short circuit protection Meets the requirements of EIA standard RS-422 High output drive capability for 100Ω terminated transmission lines

P2000SCMCL

Vendor:STPackage Cooled:DO214AAD/C:08+

During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are...

P2000SCRP

Vendor:30008Package Cooled:06+D/C:N/A

Figure 1 shows the soft-start sequence for the typical application. At T0 the +5VSB bias voltage starts to ramp up (closely followed by the +5VDUAL voltage) crossing the 4.5V POR threshold at time T1. On the PWM section, the oscillators triangular waveform is compared to the clamped error amplifier

P2000SD

Vendor:50008Package Cooled:Teccor/LittelfuseD/C:N/A

FEATURE lOptions :- 10mm lead spread - add G after part no. Surface mount - add SM after part no. Tape&reel - add SMT&R after part no. lHigh Isolation Voltage (5.3kVRMS ,7.5kVPK ) l450V Peak Blocking Voltage lAll electrical parameters 100% tested lCustom electrical selections available

P2000SDL

Vendor:STPackage Cooled:DO214AAD/C:08+

P2000SDMCL

Vendor:STPackage Cooled:DO214AAD/C:08+

This data sheet provides an overview of the R4700s CPU features and architecture. A more detailed description of this processor is provided in the IDT79R4700 RISC Processor Hardware Users Manual, available from Integrated Device Technology (IDT). Information on development support, applications notes and complementary products is available on the IDT Web site www.idt.com or through your local IDT sal...

P2002IVG

Vendor:NIKOS?Package Cooled:08+D/C:2000

P2002IVG P-CHANNEL SOP8 Y1639

P2003BVG

Vendor:NIKOSPackage Cooled:08+D/C:3800

Four independent IEEE 802.3- compliant 10BASE-T or 100BASE- TX ports in a single chip. 100BASE-FX fiber-optic capable. Standard CSMA/CD or full-duplex operation. Supports auto-negotiation and legacy systems without auto-negotiation capability. Baseline wander correction. 100BASE-TX line performance over 130 meters.

P2003BVG

Vendor:NIKOSPackage Cooled:08+D/C:3800

Four independent IEEE 802.3- compliant 10BASE-T or 100BASE- TX ports in a single chip. 100BASE-FX fiber-optic capable. Standard CSMA/CD or full-duplex operation. Supports auto-negotiation and legacy systems without auto-negotiation capability. Baseline wander correction. 100BASE-TX line performance over 130 meters.

P2004T

Vendor:PULSEPackage Cooled:SMDD/C:2008+

Parallel LED Driver Supports All Forward Voltages Adaptive VOUT Adjustment to the Highest Diode Voltage Internally Matched LED Current Sources No External Components Needed to Set LED Current Built-in Charge Pump has Three Modes of Operation: C Linear Regulation VIN > 4.2V C 3/2 DC-DC Converter and Regulation 3.6V<VIN<4.2V C 2/1 DC-DC Converter and Regulation 2.7V<VIN<3.6V Up to 86% Ef&...

P20051212

Vendor:CIRRUSLOGI?Package Cooled:GECOD/C:06+

New high voltage technology designed for ZVS-switching in lamp ballasts IGBT with integrated reverse diode 4A current rating for reverse diode Up to 10 times lower gate capacitance than MOSFET Avalanche rated 150C operating temperature FullPak isolates 2.5 kV AC (1 min.)

P2005A

Vendor:ALLIANCEPackage Cooled:SOP-8D/C:04+

Description BD52XXG/FVE, BD53XXG/FVE are series of high-accuracy detection voltage and low current consumption VOLTAGE DETECTOR ICs adopting CMOS process. New lineup of 152 types with delay time circuit have developed in addition to well-reputed 152 types of VOLTAGE DETECTOR ICs. Any delay time can be established by using small capacitor due to high-resistance process technology. Total 152 types of ...

P2005T

Designed for broadband commercial and industrial applications with frequencies from 470 to 860 MHz. The high gain and broadband performance of this device make it ideal for large - signal, common - source amplifier applications in 32 volt analog or digital television transmitter equipment. • Typical Narrowband Two - Tone Performance @ 860 MHz: VDD = 32 Volts, IDQ = 1600 mA, Pout = 270 Watts PEP ...

P200EH4G

Package Cooled:SOPD/C:0

Spartan series devices achieve high-performance, low-cost operation through the use of an advanced architecture and semiconductor technology. Spartan and Spartan-XL devices provide system clock rates exceeding 80 MHz and internal performance in excess of 150 MHz. In contrast to other FPGA devices, the Spartan series offers the most cost-effective solution while maintaining leading-edge per- formance. ...

P200EH4G

Package Cooled:SOPD/C:0

Spartan series devices achieve high-performance, low-cost operation through the use of an advanced architecture and semiconductor technology. Spartan and Spartan-XL devices provide system clock rates exceeding 80 MHz and internal performance in excess of 150 MHz. In contrast to other FPGA devices, the Spartan series offers the most cost-effective solution while maintaining leading-edge per- formance. ...

P200W2C-G

4-A Output Current Wide-Input Voltage (9 V to 29 V) Wide-Output Voltage Adjust (C15 V to C3 V) High Efficiency (Up to 87%) Output Current Limit Overtemperature Shutdown Undervoltage Lockout Operating Temperature: C40C to 85C Surface-Mount Package Available

P200Z

The CLC425's combination of ultra-low noise, wide gain-band- width, high slew rate and low dc errors will enable applications in areas such as medical diagnostic ultrasound, magnetic tape & disk storage, communications and opto-electronics to achieve maximum high-frequency signal-to-noise ratios.

P2010-10

Vendor:HSTD/C:1790

Note 5: Limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate Nationals Averaging Outgoing Quality Level (AOQL).

P2010AS009

* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to a...

P2010AS009

* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to a...

P2010B

Vendor:AGEREPackage Cooled:BGAD/C:206

Read. A low on this input informs the 73K322L that data or status information is being read by the processor. The falling edge of the RD signal will initiate a read from the addressed register. The RD signal must continue for eight falling edges of EXCLK in order to read all eight bits of the referenced register. Read data is provided LSB first. Data will not be output unless the RD signal is active.

P2010B

Vendor:AGEREPackage Cooled:BGAD/C:206

Read. A low on this input informs the 73K322L that data or status information is being read by the processor. The falling edge of the RD signal will initiate a read from the addressed register. The RD signal must continue for eight falling edges of EXCLK in order to read all eight bits of the referenced register. Read data is provided LSB first. Data will not be output unless the RD signal is active.

P2010B1

Vendor:AGEREPackage Cooled:QFN68D/C:0235+

Fast Transient Response 10-mA to 3-A Load Current Short Circuit Protection Maximum Dropout of 450-mV at 3-A Load Current Separate Bias and VIN Pins Available in Adjustable or Fixed-Output Voltages 5-Pin Package Allows Kelvin Sensing of Load Voltage Reverse Current Protection

P2010B1

Vendor:AGEREPackage Cooled:QFN68D/C:0235+

Fast Transient Response 10-mA to 3-A Load Current Short Circuit Protection Maximum Dropout of 450-mV at 3-A Load Current Separate Bias and VIN Pins Available in Adjustable or Fixed-Output Voltages 5-Pin Package Allows Kelvin Sensing of Load Voltage Reverse Current Protection

P2010E12R1FBT

P-2012E

P2012R4-826401

P2023RS28Q1

Vendor:ANADIGICD/C:05+

The Hynix HYM7V75A801B F-Series are 8Mx72bits ECC Synchronous DRAM Modules. The modules are composed of nine 8Mx8bit CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin glass-epoxy printed circuit board. A 0.33uF and a 0.1uF decoupling capacitors per each SDRAM are mounted on the PCB.

P2023RS28Q1

Vendor:ANADIGICD/C:05+

The Hynix HYM7V75A801B F-Series are 8Mx72bits ECC Synchronous DRAM Modules. The modules are composed of nine 8Mx8bit CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin glass-epoxy printed circuit board. A 0.33uF and a 0.1uF decoupling capacitors per each SDRAM are mounted on the PCB.

P2027-08SR

P2027A-08TR

Vendor:ALLIANCEPackage Cooled:MSOP8D/C:0045+

Once the signal is acquired, variation in the stored-signal level during the hold-period is of concern. This variation is primarily a function of the cutoff leakage current of the CA3080A (a maxi- mum limit of 5nA), the leakage of the storage element, and other extraneous paths. These leakage currents may be either positive or negative and, consequently, the stored-signal may rise or fall during the ho...

P2033

Vendor:PAISEPackage Cooled:04+D/C:04+

regulator and the load is gained up by the factor of (1+R2/ R1), or the effective resistance will be RP(eff)=RP3(1+R2/ R1). It is important to note that for high current applica- tions, this can represent a significant percentage of the overall load regulation and one must keep the path from the regulator to the load as short as possible to mini- mize this effect.

P2040--08TR

Vendor:PULSECOREPackage Cooled:TSOPD/C:03+

The CD54AC164/3A and CD54ACT164/3A are 8-bit serial- in/parallel-out shift registers with asynchronous reset that utilize the Harris Advanced CMOS Logic technology. Data are shifted on the positive edge of the clock (CP). A LOW on the Master Reset (MR) pin resets the shift register and all outputs go to the LOW state regardless of the input condi- tions. Two Serial Data inputs (DS1 and DS2) are provide...

P2040A-08SR

Vendor:ALLIANCEPackage Cooled:SOP-8PD/C:2003

Electrically isolated metal tab. Recommend the use of thermal grease between metal tab and heat sink. Thermal design should account for a thermal resistance between resistor and tab of 5.9C/W and a maximum resistor temperature of 155C. Current rating: 25A maximum. Surface mount package also available, please call factory.

P2040A-08TR

Vendor:ALLIANCEPackage Cooled:TSSOP/8D/C:03+

The MT9T001 produces extraordinarily clear, sharp digital pictures, and its ability to capture both continu- ous video and single frames makes it the perfect choice for a wide range of consumer and industrial applica- tions, including digital still cameras, digital video cam- eras, and PC cameras.

P2040B-08SR

Package Cooled:SOP8

P2040BF-08-ST

P2040BF-08TR

Vendor:AlliancePackage Cooled:TSSOP-8D/C:03+

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

P2040C

Package Cooled:SOP-8

• PC100 functionality • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes ̶...

P2040C

Package Cooled:SOP-8

• PC100 functionality • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes ̶...

P2040C-08SR

Package Cooled:SOPD/C:2500

Each slave carries an address. The data transfer is initiated by a start signal (S). Each transfer segment is 1 byte in length. The slave address and the read/write bit are first sent from the master device after the start signal. The addressed slave device must acknowledge (Ack) the master device. Depending on the Read/Write bit, the master device will either write data into (logic 0) or read data (lo...

P2040C-08ST

Vendor:ALLIANCED/C:SOP8

♦ Programmable Fan-Control Characteristics ♦ Automatic Fan Spin-Up Ensures Fan Start ♦ Controlled Rate-of-Change Ensures Unobtrusive Fan-Speed Adjustments ♦ 4% Fan-Speed Measurement Accuracy ♦ Temperature Monitoring Begins at POR for Fail- Safe System Protection ♦ OT and THERM Outputs for Throttling or Shutdown ♦ Measures Temperatures Up to +150C ♦ Tin...

P2040C-08TR

Vendor:AlliancePackage Cooled:TSSOP-8D/C:03+

P2040CF-08SR

Vendor:AlliancePackage Cooled:SOP-8D/C:04+

• 10-bit Analog-to-Digital Converter module (A/D) with: - Fast sampling rate - Conversion available during sleep - DNL = 1 LSb, INL = 1 LSb • Programmable Low-Voltage Detection (LVD) module - Supports interrupt on low voltage detection • Programmable Brown-out Reset (BOR)

P2040CF-08-ST

P20418

VIN (Pin 1): Positive Input Supply. When VIN > 4.2V, the internal undervoltage lockout enables the main switch that connects VIN to VOUT. Bypass VIN with a 10µF ceramic capacitor and a 1Ω resistor in series or use a 10µF capacitor with at least 1Ω minimum ESR. This minimizes the voltage transient that can occur when the input is hot switched.

P20418

VIN (Pin 1): Positive Input Supply. When VIN > 4.2V, the internal undervoltage lockout enables the main switch that connects VIN to VOUT. Bypass VIN with a 10µF ceramic capacitor and a 1Ω resistor in series or use a 10µF capacitor with at least 1Ω minimum ESR. This minimizes the voltage transient that can occur when the input is hot switched.

P2042A

Vendor:ALLIANCEPackage Cooled:SOP8D/C:02+

Advanced multi-bit Delta-Sigma architecture 24-bit conversion Supports all audio sample rates including 192 kHz 101 dB Dynamic Range at 5 V -94 dB THD+N High-pass filter to remove DC offsets Analog/digital core supplies from 3.3 V to 5 V Supports logic levels between 1.8 V and 5 V Low-latency digital filter Auto-mode selection Pin compatible with the CS5341

P2042A

Vendor:ALLIANCEPackage Cooled:SOP8D/C:02+

Advanced multi-bit Delta-Sigma architecture 24-bit conversion Supports all audio sample rates including 192 kHz 101 dB Dynamic Range at 5 V -94 dB THD+N High-pass filter to remove DC offsets Analog/digital core supplies from 3.3 V to 5 V Supports logic levels between 1.8 V and 5 V Low-latency digital filter Auto-mode selection Pin compatible with the CS5341

P2042A-08TR

Package Cooled:02D/C:2500

The maximum allowable power dissipation is function of the maximum ambient temperature (TAMAX). The maximum allowable die temperature (125C) and the thermal resistance from junction-to-air (JA). The 5- pin SOT-23A package has a JA of approximately 220C/Watt when mounted on a single layer FR4 dielectric copper clad PC board.

P2042A-08TR

Package Cooled:02D/C:2500

The maximum allowable power dissipation is function of the maximum ambient temperature (TAMAX). The maximum allowable die temperature (125C) and the thermal resistance from junction-to-air (JA). The 5- pin SOT-23A package has a JA of approximately 220C/Watt when mounted on a single layer FR4 dielectric copper clad PC board.

P2042AF

Vendor:ALLIANCEPackage Cooled:SSOP8D/C:06+

MATERIAL: Units are encapsulated in a low thermal resistance molding compound which has excellent chemical resistance, wide operat- ing temperature range, and good electrical properties under high hu- midity environments. The encapsu- lant and outer shell of the unit have UL94V-0 ratings. Lead material is brass with a solder plated surface to allow ease of solderability.

P2042AF-08TR

Vendor:ALLIANCEPackage Cooled:TSSOP-8D/C:0634.

The HYM71V75S3201 N-Series are Dual In-line Memory Modules suitable for easy interchange and addition of 256Mbytes memory. The HYM71V75S3201 N-Series are offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. The DIMM /CAS latency in...

P2067

Vendor:DIPD/C:98+

In the intended application, it is expected that the transmitter will spend a large proportion of time in stand by not transmitting data. To maximise battery life it is important that very little quiescent current is taken in this mode. The stand by mode is selected by setting pin TXEN low and similarly the transmitter is enabled by setting TXEN high. To minimize standCby current TXEN is used to bias...

P20L8ACNL

4.4.2 Group B inspection. Group B inspection shall be conducted in accordance with the conditions specified for subgroup testing in appendix E, table VIa (JANS) and table VIb (JAN, JANTX and JANTXV) of MIL-PRF-19500, and herein. Electrical measurements (end-points) and delta requirements shall be in accordance with table III herein.

P20L8BXV

Vendor:NSD/C:O9+

* The products contained herein may also be controlled under the U.S. Export Administration Regulations and/or subject to the approval of the U.S. Department of Commerce or U.S. Department of State prior to export. Any export or re-export, directly or indirectly in contravention of any of the applicable export laws and regulations, is hereby prohibited.

P20NM50FP

Vendor:907

All DATEL sampling A/D converters are fully characterized and specified over operating temperature (case) ranges of 0 to +70C and C55 to +125C. All room-temperature (TA = +25C) production testing is performed without the use of heat sinks or forced-air cooling. Thermal impedance figures for each device are listed in their respective specification tables.

P20SCHA

P2100R

Package Cooled:DIP-8

C Serial port hardware handshaking with CTS, RTS, ENRX, and RTR selectable for each port C Improved serial port operation enhances 9-bit DMA support C Independent serial port baud rate generators C DMA to and from the serial ports C Watchdog timer can generate NMI or reset C A pulse-width demodulation option C A data strobe, true asynchronous bus interface option included for DEN C Reset config...

P2100R

Package Cooled:DIP-8

C Serial port hardware handshaking with CTS, RTS, ENRX, and RTR selectable for each port C Improved serial port operation enhances 9-bit DMA support C Independent serial port baud rate generators C DMA to and from the serial ports C Watchdog timer can generate NMI or reset C A pulse-width demodulation option C A data strobe, true asynchronous bus interface option included for DEN C Reset config...

P2100SBMCL

Vendor:STPackage Cooled:DO214AAD/C:08+

To use the long frame mode, both the frame sync pulses, FSX and FSR, must be three or more bit clock periods long, with timing relationships specified in Figure 3. Based on the transmit frame sync, FSX, the COMBO will sense whether short or long frame sync pulses are being used. For 64 kHz operation, the frame sync pulse must be kept low for a minimum of 160 ns. The DX TRI-STATE output buffer is enabl...

P2100SC

Vendor:TECCORPackage Cooled:DO214AAD/C:08+

High speed output rise and fall (20 ns typ) at load capacitance (CL) of 1000 pF Direct drive of input block by TTL eliminates the need for external components Output swing voltage of 12 V; output current of 1 A available for both sink and source Output wave cross point 50% typ

P2101

The MAX4380CMAX4384 family of op amps are unity- gain-stable devices that combine high-speed perfor- mance, Rail-to-Rail ® outputs, and high-impedance disable mode. These devices operate from a +4.5V to +11V single supply or from 2.25V to 5.5V dual sup- plies. The common-mode input voltage range extends beyond the negative power-supply rail (ground in sin- gle-supply applications). The MAX4380CMAX4384 r...

P21010-07

Package Cooled:DIPD/C:03+

Low power consumption and flexible power management allow selective shutdown of DAC functions, thus extending battery life in portable applications. Couple this design solution with the industrys smallest package, the TI proprietary MicroStar Junior using only 25 mm2 of board area, powerful portable stereo audio designs are easily realizable in a cost effective, space saving total analog solution.

P2101010

Vendor:intPackage Cooled:intD/C:dc89

Output Threshold Adjust The state of the OUT pin is driven by a voltage comparator whose output state depends on the level of the input voltage on the sample capacitor and the level of an adjustable 8-bit threshold voltage. The threshold is adjusted by shifting data bits into the D/A Register (DAR) via the DATA pin while clocking the CLK pin. The timing of this data is shown in Figure 4. Data is transferr...

P21010-10

The Toshiba P21010-10 consists of an aluminum gallium arsenide infrared emitting diode optically coupled to a photo-MOSFET in a SOP, which is suitable for surface mount assembly. The P21010-10 is suitable for the modem applications which require space savings.

P21014-06

Brooktree products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a Brooktree product can reasonably be expected to result in personal injury or death. Brooktree customers using or selling Brooktree products for use in such applications do so at their own risk and agree to fully indemnify Brooktree for any damages resulting from such improper use o...