PG0040.XXXT

PG0041.474T

PG0041.684T

PG0051.222T

Vendor:PULSED/C:.

Except the build-in USB 1.1 interface, the capability of cooperating with USB 2.0 and IEEE 1394 interface controller also expand the scalability of GeneScan TMII to fit customer's further requirement of supporting high speed interface standards.

PG0051.473T

Lead Style Channels Common Channel Wiring Agilent Part # & Options Commercial MIL-PRF-38534 Class H MIL-PRF-38534 Class K Standard Lead Finish Solder Dipped Butt Cut/Gold Plate Gull Wing/Soldered Crew Cut/Gold Plate Class H SMD Part # Prescript for all below Either Gold or Solder Gold Plate Solder Dipped Butt Cut/Gold Plate Butt Cut/Soldered Gull Wing/Soldered Crew Cut/Gol...

PG0063.102T

PG0063.104T

PG0063.105T

PG0063.222NL

Vendor:PulseD/C:07+

PG0063.223T

PG0063.333T

PG0063.334T

PG0063.472T

PG0063.473T

PG0063.474T

PG0067.222T

PG0067.301T

PG0067.601T

PG0077.142T

Vendor:PulsePackage Cooled:07+D/C:600

PG0083.402T

PG0084.222T

PG0085.104T

PG0085.152T

PG0085.224T

PG0085.332

PG0085.473T

PG0086.334T

PG0086.604T

PG0086.684T

PG0087.103

PG0087.682NL

PG0109.223

In addition, Dallas Semiconductor's continuous reliability monitor program ensures that all outgoing assemblies will continue to meet Maxim's quality and reliability standards. The current status of the reliability monitor program can be viewed at http://www.maxim-ic.com/TechSupport /dsreliability.html.

PG0124.103

PG0137.101T

PG0137.501T

PG0138.102T

PG0138.472T

PG0200.351

PG0200.451

PG0202

PG0221NL

PG0230.451

Vendor:RIVERD/C:07+

PG0271

PG0279

D/C:05+

When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Additionally, easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory.

PG0377.8O1T

Vendor:PULSED/C:05+06+

PG0392NL

PG05FSESC

Vendor:KECPackage Cooled:603D/C:3

shows the current waveform for the 8kV IEC 1000-4-2 Level 4 ESD Contact Discharge test. The Air-Gap test involves approaching the device with a charged probe. The Contact Discharge method connects the probe to the device before the probe is energized.

PG05FSESC

Vendor:KECPackage Cooled:603D/C:3

shows the current waveform for the 8kV IEC 1000-4-2 Level 4 ESD Contact Discharge test. The Air-Gap test involves approaching the device with a charged probe. The Contact Discharge method connects the probe to the device before the probe is energized.

PG05FSESC-RTK/P

Vendor:KECPackage Cooled:SOD523D/C:05+Pb

The SO-8 has been modified through a customized leadframe for enhanced thermal characteristics and multiple-die capability making it ideal in a variety of power applications. With these improvements, multiple devices can be used in an application with dramatically reduced board space. The package is designed for vapor phase, infrared, or wave soldering techniques.

PG05GBUSV-RTK

Vendor:KECPackage Cooled:SOT353D/C:2003

Note 5 This specification tests ICC with all power fail circuitry disabled by setting D7 of Interrupt Control Register 1 to 0 Note 6 This specification tests ICC with all power fail circuitry enabled by setting D7 of Interrupt Control Register 1 to 1

PG10-48-1R5

Vendor:LAMBDAPackage Cooled:ModuleD/C:N/A

The LM3200 is a DC-DC converter optimized for powering RF power amplifiers (PAs) from a single Lithium-Ion cell. It steps down an input voltage of 2.7V to 5.5V to a variable output voltage of 0.8V to 3.6V. The output voltage is set using an analog input ( VCON) for optimizing efficiency of the RF PA at various power levels.

PG104KL

Vendor:OHIZUMIPackage Cooled:DipD/C:09+

PG108RS

PG10NG

Package Cooled:08+D/C:2000

When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into the programmable registers for parallel programming, and when enabled by SEN, the rising edge of WCLK writes one bit of data into the programmable register for serial programming.

PG10NG

Package Cooled:08+D/C:2000

When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into the programmable registers for parallel programming, and when enabled by SEN, the rising edge of WCLK writes one bit of data into the programmable register for serial programming.

PG1101F

Vendor:STANLEYD/C:08+

PG1101F-TR

D/C:07+

Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Sync amplitude = 5VP-P, pulse width = 50ns. Verify output (A-F) frequency = 1/2 sync frequency. Note 3: Includes leading edge blanking delay, RLEB = 20k. Note 4: FB is driven by a servo-loop amplifier to control VCOMP for these tests.

PG1101H-TR

Vendor:STANLEY ?Package Cooled:N/A?D/C:2030

For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs.

PG1101W

s 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package. s 8 kB to 40 kB of on-chip static RAM and 32 kB to 512 kB of on-chip flash memory. 128-bit wide interface/accelerator enables high-speed 60 MHz operation. s In-System Programming/In-Application Programming (ISP/IAP) via on-chip boot loader software. Single flash sector or full chip erase in 400 ms and programming of 256 by...

PG1101W-TR

D/C:07+

The PG1101W-TR and PG1101W-TR 3-STATE buffers utilize advanced silicon-gate CMOS technology and are general purpose high speed inverting and non-inverting buffers. They possess high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits achieve speeds comparable to low power Schottky devices, while retaining the low power consumption of CMOS. ...

PG1102W

Vendor:STANLEYD/C:08+

The MAX3060E features slew-rate-limited drivers that minimize EMI and reduce reflections caused by improperly terminated cables, allowing error-free data transmission up to 115kbps. The MAX3061E, also slew- rate limited, transmits up to 500kbps. The MAX3062E driver is not slew-rate limited, allowing transmit speeds up to 20Mbps. All transmitter outputs are protected to 15kV using the Human Body Model.

PG1102W-TR

Vendor:STANLEYD/C:954

GATA: Gate drive for an external N-channel power MOSFET to select −VINA. When CVINA is more negative than CVINB, GATA is pulled 14 V above CVINA, turning on the CVINA power FET. When CVINB is more negative than CVINA, GATA is pulled down to CVINB, turning off the CVINA power FET.

PG1111C-TR

Vendor:STANLEYD/C:.

The HYM72V64736(L)T8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 512Mbytes memory. The HYM72V64736(L)T8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.

PG1111C-TR

Vendor:STANLEYD/C:.

The HYM72V64736(L)T8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 512Mbytes memory. The HYM72V64736(L)T8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.

PG1112H-TR

Vendor:STANLEYD/C:.

High Efficiency: Up to 90% 3A Output Current Symmetrical Source and Sink Output Current Limit Low RDS(ON) Internal Switch: 85mΩ No Schottky Diode Required 2.25V to 5.5V Input Voltage Range VOUT = VREF /2 1% Output Voltage Accuracy Programmable Switching Frequency: Up to 2MHz Power Good Output Voltage Monitor Overtemperature Protected Available in 16-Lead TSSOP Exposed Pad Package

PG1113F-TR

D/C:07+

Sony provides the new CXA3572R system IC, which was developed along with the PG1113F-TRAK. This system IC integrates the timing generator and the RGPG1113F-TR drivers on a single chip. The CXA3572R supports both NTSC and PAL, and accepts either Y/color differ- ence or RGPG1113F-TR signals as input. It includes up/down and/or right/left inversion functions to take advantage of the pan- els features...

PG1204W

PG123

Vendor:N/APackage Cooled:6PIND/C:2000

PG124S-15

Vendor:FUJIPackage Cooled:TO-3P-2LD/C:02+/03+

PG127S17

Vendor:1200Package Cooled:FUID/C:N/A

Four channels of EMI filtering with ESD protection Greater than 30dB of attenuation from 800MHz to 3GHz 15kV ESD protection (IEC 61000-4-2, contact discharge) 30kV ESD protection (HBM) 8-lead TDFN package (2mm x 2mm), 0.5mm pitch Lead-free version available

PG135KL

Vendor:OHIZUMIPackage Cooled:DipD/C:09+

PG14111

Vendor:NichibutsuPackage Cooled:DIP40D/C:2007+

The emulator consists of a base unit that connects to the PC by way of the parallel or USB port. The base unit is universal and will operate with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation.

PG150

PG152

PG152R

PG153J

Vendor:SUNGHYUNPackage Cooled:NTC-15K

PG156R

PG176B 5962-9215601MXC

Vendor:ACTEL

PG1A-05

Vendor:NECPackage Cooled:(LX)high-frequency

The recommended input capacitance is determined by 350 milli-amperes (rms) minimum ripple current rating and 100µF minimum capacitance. Capacitors placed at the input must be rated for a minimum of twice the input voltage with +5V operation. Ripple current and 200mΩ Equivalent Series Resistance (ESR) values are the major considerations, along with temperature, when selecting the proper inp...

PG1A-05D

Vendor:1200

OVER- AND UNDER-SCALE LIMITING Over-Scale DAC: 16 Steps Adjustment Range RTO(6) of Current Amplifier RTO(6) of PGA Step Size RTO(6) of Current Amplifier RTO(6) of PGA Accuracy Under-Scale DAC: 8 Steps Adjustment Range RTO(6) of Current Amplifier RTO(6) of PGA Step Size RTO(6) of Current Amplifier RTO(6) of PGA Accuracy

PG1A-12D

Vendor:TOKINPackage Cooled:relayD/C:00+

The Acknowledge (ACK) Bit shown in Figure 2 is provided by the Configurator receiving the byte. The receiving Configurator can accept the byte by asserting a Low value on the cSDA line, or it can refuse the byte by asserting (allowing the signal to be externally pulled up to) a High value on the cSDA line. All bytes from accepted messages must be terminated by either an Acknowledge Bit or a Stop Condition....

PG-200

Vendor:COPALPackage Cooled:SALE--STOCK!!D/C:08+

PG204KL

Vendor:OHIZUMIPackage Cooled:DipD/C:09+

PG211

Vendor:SMDPackage Cooled:00+D/C:2004+

When the voltage drop to the positive input of the comparator (i.e. VB) is higher than Vref, VOUT goes high, and VB is ex- pressed as VBH=VDD ´ (RB+RC) / (RA+RB+RC). If VDD is decreased so that VB falls to a value less than Vref, the com- parator output inverts from high to low, VOUT goes low, VC is high, RC is bypassed, and VB becomes: VBL=VDD ´ RB/(RA+RB), which is less than VBH. By so doing, t...

PG2202S

PG2255

PG24064ERUGNNB

Vendor:powertipPackage Cooled:powertipD/C:dc00

FEATURES Fast Throughput Rate: 100kSPS Specified for VDD of 2.5 V to 5.25 V Low Power: 2.5mW typ at 100kSPS with 3V Supplies 15mW typ at 100kSPS with 5V Supplies Wide Input Bandwidth: 85dB SNR at 10kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High Speed Serial Interface SPI/QSPI/µWire/DSP Compatibleµ Standby Mode: 0.5 µA max 6-Lead SOT-23, a...

PG243002

Vendor:YCLPackage Cooled:08+D/C:2400

DESCRIPTION The 74LVQ541 is a low voltage CMOS OCTAL BUS BUFFER with 3 STATE OUTPUTS NON INVERTED fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications.

PG2BCABD

PG302R

PG3-479S-1.27MSB(33)

PG3R13

Vendor:SHARPPackage Cooled:TO-220D/C:02+

PG4002S

PG4003S

PG4004

PG4006

PG4006S

PG4007

PG403HL

Vendor:A/NPackage Cooled:DIP-40K 4

PG403JL

Vendor:A/NPackage Cooled:DIP-40K 4