QL5432-33APQ208I

Vendor:QUICKLOGICPackage Cooled:QFP208D/C:03+

QL5732-33BPS484C

Vendor:QUICKLOGICPackage Cooled:BGA484D/C:03+

QL6250-4PQ208C

Package Cooled:QFPD/C:08+09+

QL6250-4PQ208C

Package Cooled:QUICKLOGICD/C:08+09+

QL6250-6PB516C

Vendor:QUICKLOGICPackage Cooled:BGA516D/C:03+

QL6250E-6PS484I

Vendor:QUICKLOGICPackage Cooled:BGA484D/C:04+

QL6325-4PS484C

Vendor:QLOGICPackage Cooled:BGAD/C:N/A

QL6325-6PS484C

Vendor:QUICJKLOGILPackage Cooled:BGAD/C:2004+

After setting SDP, any attempt to write to the device without the three-byte command sequence will start the internal write timers. No data will be written to the device; how- ever, for the duration of tWC, a read operation will effectively be a polling operation.

QL6325-6PS484C

Vendor:QUICJKLOGILPackage Cooled:BGAD/C:2004+

After setting SDP, any attempt to write to the device without the three-byte command sequence will start the internal write timers. No data will be written to the device; how- ever, for the duration of tWC, a read operation will effectively be a polling operation.

QL6325E-7

Vendor:QUICKLOGICPackage Cooled:QFP208D/C:05+

QL6325-ESPQ208C

Vendor:QUICKLOGICPackage Cooled:QUICKLOGICD/C:01+

QL7-4

Vendor:双菱Package Cooled:桥D/C:05+

QL8025-6PF144C

Vendor:QUICKLOGICPackage Cooled:QFP144D/C:04+

QL8050-TQFP144C

These three terminal positive regulators are supplied in a hermetically sealed metal package whose outline is similar to the industry standard TO-220 plastic package. All protective features are designed into the circuit, including thermal shutdown, current limiting and safe-area control. With heat sinking, they can deliver over 3.0 amps of output current. These units feature 2% initial voltage tolerance, ...

QL80FC-APQ208C

Vendor:QUICKLOGICPackage Cooled:QFP208D/C:03+

The Fujitsu MB81ES171625/173225 is a Fast Cycle Random Access Memory (FCRAM*) containing 16,777,216 bit memory cells accessible in a 2512K16 bit / 2256K32 bit format. The MB81ES171625/173225 features a fully synchronous operation referenced to a positive edge clock same as that of SDRAM operation, whereby all operations are synchronized at a clock input which enables high performance and simple user inter...

QL8150-6PQ208C

Vendor:QUICKLOGICPackage Cooled:QFP208D/C:05+

QL8150-6PT196I

Vendor:QUICKLOGICPackage Cooled:BGA196D/C:04+

QL8325-6PT280C

Vendor:QUICKLOGICPackage Cooled:QUICKLOGICD/C:04+

QL8X12-2PL68C

Vendor:QUICKLOG..Package Cooled:N/AD/C:17

This family is a 16M bit dynamic RAM organized 2,097,152 x 8-bit configuration with Extended Data Out mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time(60, 70 or 80ns) and refresh cycle(2K ref. or 4K ref.) and power consu...

QL8X1280PL44C

The ISL9R30120G2 is a Stealth™ diode optimized for low loss performance in high frequency hard switched applications. The Stealth™ family exhibits low reverse recovery current (IRM(REC)) and exceptionally soft recovery under typical operating conditions.

QL8X12A

Vendor:QLPackage Cooled:PLCC68D/C:07/08+

QL8X12A-1PL68C

Vendor:QUALCOMMPackage Cooled:PLCC68

The DSTINIm400 is a fully assembled and tested circuit board that evaluates the DS80C400 network microcontroller. In addition to the DS80C400, the DSTINIm400 includes a real-time clock, 1MB flash, 1MB static RAM, and support for an external Ethernet PHY for connecting to a wide variety of networks. The circuit board is designed as a module to be plugged into a 144-pin SODIMM connector. For evaluation, the D...

QL8X12A-2PL68C

Vendor:QUICKLOGICPackage Cooled:07+D/C:50

1/ Parameter guaranteed by line and load regulation tests. 2/ Bandwidth guaranteed by design. Tested for 20 kHz to 2 MHz. 3/ Capacitive load may be any value from 0 to the maximum limit without compromising dc performance. A capacitive load in excess of the maximum limit will not disturb loop stability but may interfere with the operation of the load fault detection circuitry, appearing as a short circui...

QL8X12A-3PL68C

Vendor:QUICKLOG..Package Cooled:PLCCD/C:N/A

QL8X12A-OPL

QL8X12B0PF100C

Vendor:QUICK LOGICD/C:06+

Sync (HUM-70 only) • Range 525 min to 625 max kHz • Duty cycle 40% min to 60% max • Logic low 0.8V, max • Logic high 4.5 V, min • Referenced to input common • If sync is not used, leave unconnected Inhibit TTL Open Collector • Logic low (output disabled) Logic low voltage 0.8 V max Inhibit pin current 15 mA • Referenced to input common ̶...

QL8X12B-0PF100C

Vendor:QLPackage Cooled:QFPD/C:08+09+

see BAT15-013 see BAT15-013 see BAT15-013 see BAT15-013 see BAT15-013 see BAT15-013 see BAT15-013 see BAT15-013 see BAT15-013 see BAT15-013 see BAT15-013 see BAT15-013 see BAT15-013 see BAT15-013 see BAT15-013 see BAT15-013 see BAT15-013

QL8X12B-0PL44C

Vendor:OUICKLOGICD/C:05+

precision LCD panel display can be assembled using the NT7702. In the segment mode, the data input is selected as 4bit parallel input mode or as 8bit parallel input mode by a mode (MD) pin. In the common mode, the data input/output pins are bi-directional and the four data shift directions are pin-selectable.

QL8X12B0PL68C

PROTECTION SECTION Peak Current Limit Current Limit Delay Time(3) Thermal Shutdown Temperature(3) Shutdown Feedback Voltage Over Voltage Protection Shutdown Delay Current Leading Edge Blanking Time TOTAL DEVICE SECTION Operating Supply Current (control part only) Start-Up Charging Current Vstr Supply Voltage

QL8X12B-1PF100C

Vendor:QUICKLOG..Package Cooled:N/AD/C:16

The RESET (SVS, POR, or power on reset) output of the TPS752xxQ initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS752xxQ monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When the output reaches 95% of its regulated voltage, RESET goes to a high-impedance ...

QL8X12B-1PL44C

Vendor:QUICKLOG..Package Cooled:N/AD/C:148

The Start Circuitry generates the internal START signal which causes the Sequence Generator to initiate an addressing sequence. The START signal is produced by writing the Processor Interfaces Sequencer Start address (see Processor Interface text), by asserting the STARTlN input, or by the terminal address of a sequence generated under One-Shot Mode with Restart (see Sequence Gener- ator Section). Ca...

QL8X12B-1PL68I

Vendor:QUICKLOG..Package Cooled:N/AD/C:100

2.5% output accuracy (25˚C) Low dropout voltage: 450mV @ 1A (typ, 5V out) Wide input voltage range (2.7V to 10V) Precision (trimmed) bandgap reference Guaranteed specs for -40˚C to +125˚C 1µA off-state quiescent current Thermal overload protection Foldback current limiting T0-252, SOT-223 and 6-Lead LLP packages Enable pin (LP38692)

QL8X12B-1QL12X16B

Vendor:QUICKLOGLCPackage Cooled:PLCC68D/C:08+

QL8X12B-2PF100I

Vendor:QUICKLOGICPackage Cooled:TQFP

Hynix HYMD232M646(L)8-K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline Dual In-Line Memory Modules (SO-DIMMs) which are organized as 32Mx64 high-speed memory arrays. Hynix HYMD232M646(L)8-K/H/L series consists of eight 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 200pin glass- epoxy substrate. Hynix HYMD232M646(L)8-K/H/L series provide a high performance 8-byte interface ...

QL8X12B-2PL44C

Vendor:QUICKLOG..Package Cooled:N/AD/C:4

4.3 Screening. Screening shall be in accordance with appendix E, table IV of MIL-PRF-19500, and as specified herein. The following measurements shall be made in accordance with table I herein. Devices that exceed the limits of table I herein shall not be acceptable.

QL8X12B-2PL68C

Vendor:QUICKLOGICPackage Cooled:QUICKLOGICD/C:35

Fault Status (Output): Open drain N-Channel device, active low. This pin indicates an overcurrent or thermal shutdown condition. For an overcurrent event, /FAULT is asserted if the duration of the overcurrent condition lasts longer than 32ms.

QL8X12BL-1PL68I

Vendor:OUICKLOGICD/C:05+

Read. A low on this input informs the 73K322L that data or status information is being read by the processor. The falling edge of the RD signal will initiate a read from the addressed register. The RD signal must continue for eight falling edges of EXCLK in order to read all eight bits of the referenced register. Read data is provided LSB first. Data will not be output unless the RD signal is active.

QL8X12BL-OPL44C

Vendor:QUICKLOG..Package Cooled:PLCCD/C:N/A

Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the address during the clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQs ...

QL8X12BL-OPL44C

Vendor:QUICKLOG..Package Cooled:PLCCD/C:N/A

Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the address during the clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQs ...

QL8X12B-OPL44C

Vendor: QUICKLOG Package Cooled:PLCCD/C:08+09+

PWM With Tri-State Enable 12-V Low-Side Gate Drive (SiP41109) 8-V Low-Side Gate Drive (SiP41110) Undervoltage Lockout Internal Bootstrap Diode Switching Frequency Up to 1 MHz 30-ns Max Propagation Delay Drive MOSFETs In 5- to 48-V Systems Adaptive Shoot-Through Protection

QL8X12BOPL68C

Vendor:availD/C:04+

NOTES: 1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics. 2. Per TLL driven input (VIN = 3.4V, control inputs only). I and Y pins do not contribute to ∆Icc. 3. This current applies to the control inputs only and represents the current required to switch internal capacitance at the specified frequency. The I and Y inputs generate no sig...

QL8X12BOPL68C

Vendor:availPackage Cooled:QUICKLOG..D/C:04+

NOTES: 1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics. 2. Per TLL driven input (VIN = 3.4V, control inputs only). I and Y pins do not contribute to ∆Icc. 3. This current applies to the control inputs only and represents the current required to switch internal capacitance at the specified frequency. The I and Y inputs generate no sig...

QL8X12B-OPL68L

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage ...

QL8X12B-XPF100C

Package Cooled:ＱＦＰ

Complete support for the XC5200 family is delivered through the familiar XACT software environment. The XC5200 family is fully supported on popular workstation and PC platforms. Popular design entry methods are fully supported, including ABEL, schematic capture, and synthesis. Designers utilizing logic synthesis can use their existing Synopsys, Viewlogic, Mentor, and Exemplar tools to design with the...

QL8X12B-XPL68I

Vendor:QUICKLOGPackage Cooled:PLCCD/C:0403+

DESCRIPTION The L7800 series of three-terminal positive regulators is available in TO-220, TO-220FP, TO-220FM, TO-3 and D2PAK packages and several fixed output voltages, making it useful in a wide range of applications. These regulators can provide local on-card regulation, eliminating the distribution problems associated with single point regulation. Each type employs internal current limiting, t...

QL8X12B-ZPL44C

Vendor:QUICKLOGPackage Cooled:PLCC

Analog Signal Range On Resistance, +25C 0 to +70C C55 to +125C RON versus VIN Input Leakage Current (Off) +25C 0 to +70C C55 to +125C Output Leakage Current (Off) +25C 0 to +70C C55 to +125C On Channel Leakage Current +25C 0 to +70C C55 to +125C Channel Input Capacitance Off On Channel Output Capacitance On Nonlinearity Large signal bandwidth (C3dB)

QL8X12M4U

QL8X12-OPL68C

Vendor:QUALCOMMPackage Cooled:PLCC68

Any offset and/or gain calibration procedures should not be implemented until devices are fully warmed up. To avoid interaction, offset must be adjusted before gain. The ranges of adjustment for the circuit in Figure 2 are guaranteed to compensate for the ADS-944's initial accuracy errors and may not be able to compensate for additional system errors.

QL8X16B

Vendor:QUICKLOGICPackage Cooled:407D/C:35

The circuit of the TSOP11..SK1 is designed in that way that unexpected output pulses due to noise or disturbance signals are avoided. A bandpass filter, an integrator stage and an automatic gain control are used to suppress such disturbances. The distinguishing mark between data signal and dis- turbance signal are carrier frequency, burst length and duty cycle. The data signal should fulfill the fol...

QLA694BYG

NOTES: 1. All typical values are at VCC = 5 V, Tamb = +25C ambient and maximum loading. 2. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (A or B) terminals. 3. These parameters are determined by device characterization, but is not production tested. 4. Not more than one outpu...

QLC895197MCIN

Vendor:N/APackage Cooled:N/A

QLCPB248E

Vendor:hpPackage Cooled:hpD/C:dc99

Thus when the voltage across the inductor is positive (State 1), the inductor current increases; when the voltage across the inductor is negative (State 2), the inductor current decreases. The net current through the inductor is shown in Figure 2:

QLCPB248E

Vendor:hpPackage Cooled:hpD/C:dc99

Thus when the voltage across the inductor is positive (State 1), the inductor current increases; when the voltage across the inductor is negative (State 2), the inductor current decreases. The net current through the inductor is shown in Figure 2:

QLCPB248F

Vendor:hpPackage Cooled:hpD/C:dc99

DRIVE INTERRUPTS These signals are used to interrupt the host system CH1 INTRQ is asserted only when the drive(s) on channel 1 has a pending interrupt and the host has cleared nIEN in the drives Device Control Register CH2 INTRQ is asserted only when the drive(s) on channel 2 has a pending interrupt and the host has cleared nIEN in the Device Control Register

QLCPB248F

Vendor:hpPackage Cooled:hpD/C:dc99

DRIVE INTERRUPTS These signals are used to interrupt the host system CH1 INTRQ is asserted only when the drive(s) on channel 1 has a pending interrupt and the host has cleared nIEN in the drives Device Control Register CH2 INTRQ is asserted only when the drive(s) on channel 2 has a pending interrupt and the host has cleared nIEN in the Device Control Register

QLCP-M082

QLCP-M089

Vendor:hp/AgilentPackage Cooled:01/02+D/C:35830

Short circuit withstand time C 10µs Designed for : - Soft Switching Applications - Induction Heating Trench and Fieldstop technology for 1200 V applications offers : - very tight parameter distribution - high ruggedness, temperature stable behavior - easy parallel switching capability due to positive temperature coefficient in VCE(sat) Very soft, fast recovery anti-parallel EmCon™ HE ...

QLCP-M089

Vendor:hp/AgilentPackage Cooled:01/02+D/C:35830

Short circuit withstand time C 10µs Designed for : - Soft Switching Applications - Induction Heating Trench and Fieldstop technology for 1200 V applications offers : - very tight parameter distribution - high ruggedness, temperature stable behavior - easy parallel switching capability due to positive temperature coefficient in VCE(sat) Very soft, fast recovery anti-parallel EmCon™ HE ...

QLCTS75A-751N

D/C:95

QLD128B

When VCC is within nominal limits (VCC > 4.5 volts) the DS1642 can be accessed as described above by read or write cycles. However, when VCC is below the power-fail point VPF (point at which write protection occurs) the internal clock registers and RAM is blocked from access. This is accomplished internally by inhibiting access via the CE signal. When VCC falls below the level of the internal battery supp...

QLL04

Package Cooled:DIP

A 1.5 MΩ value of RREF from log average to C15 V will establish a 10 µA reference current in the logging transistor (Q1). This will bias the transistor in the middle of the detectors dynamic current range in dB to optimize dynamic range and accuracy. The LOG AV outputs are buffered and amplified by unipolar drive op amps. The 39 kΩ, 1 kΩ resistor network at the THRESH pin provides...

QLL04

Package Cooled:DIP

A 1.5 MΩ value of RREF from log average to C15 V will establish a 10 µA reference current in the logging transistor (Q1). This will bias the transistor in the middle of the detectors dynamic current range in dB to optimize dynamic range and accuracy. The LOG AV outputs are buffered and amplified by unipolar drive op amps. The 39 kΩ, 1 kΩ resistor network at the THRESH pin provides...

QLM9S470U684

QLMA86002

QLMADEL86

BVDSSDrain-to-Source Breakdown Voltage-200 ∆BV DSS /∆T J Temperature Coefficient of Breakdown Voltage RDS(on)Static Drain-to-Source On-State Resistance VGS(th)Gate Threshold Voltage-2.0 g fsForward Transconductance4.0 IDSSZero Gate Voltage Drain Current

QLMA-PJ49

D/C:1500

Note 1: In the typical PECL 100K logic output Voh is 2.35 volts and Vol is 1.60 volts at 3.3 Vcc. The center voltage of the PECL is therefore1.975 volts. If a 50 ohm resistor is placed between the output and Vcc C 2 volts (1.3 volts), the current through the resistor is (1.975 C 1.3) / 50 = 13.5 mA. The same load can be simulated by a resistor of 147 1% ohms to ground (1.975 / 0.0135 = 146.29 ohms). If add...

QLMA-PL47-NP011

D/C:08+

QLMAQH4911

QLMCP00311

QLMCP01031

QLMP0894

Eight 8-bit registers are provided for control, option select, and status monitoring. These registers are addressed with the AD0, AD1, and AD2 multiplexed address lines (latched by ALE) and appear to a control microprocessor as seven consecutive memory locations. Six control registers are read/write memory. The detect and ID registers are read only and cannot be modified except by modem response to monitore...

QLMP-2316

Vendor:hp/AgilentPackage Cooled:01/02+D/C:3763

In nibble interface mode, data is input most-significant nibble first, aligned to the rising edge of TCLKB, followed by the least-significant nibble aligned to the falling edge. When CODE = high, TDBA3 acts as the K-character indicator for channel A.

QLMP-2389

Vendor:hp/AgilentPackage Cooled:01/02+D/C:4667

DESCRIPTION The STV5346 decoder is a computer-controlled teletext device including an 8 page internal mem- ory. Data slicing and capturing extracts the teletext information embedded in the composite video sig- nal. Control is accomplished via a two wire serial I2C bus ®. Internal ROM provides a character set suitable to display text using up to seven national languages. Different ROM versions wi...

QLMP-2447

Vendor:AGLIENTPackage Cooled:2000D/C:DIP

Dual output: 5 V and 15 V High input voltage range: up to 45 V High output current capability High output voltage accuracy Very low current consumption Short circuit protected Over-temperature protected Thermal and space optimized package

QLMP-2589

Vendor:AGLIENTPackage Cooled:2000D/C:DIP

FEATURES Meets SONET Requirements for Jitter Transfer/ Generation/Tolerance Quantizer Sensitivity: 4 mV Typ Adjustable Slice Level: 100 mV 1.9 GHz Minimum Bandwidth Patented Clock Recovery Architecture Loss of Signal Detect Range: 3 mV to 15 mV Single Reference Clock Frequency for Both Native SONET and 15/14 (7%) Wrapper Rate Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz REFCLK LVPEC...

QLMP-2632

Caution: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied.

QLMP-2832

Vendor:hp/AgilentPackage Cooled:01/02+D/C:2831

QLMP-2976

Vendor:hp/AgilentPackage Cooled:01/02+D/C:1400

3. Circuit board traces from the DAAs TIP and RING pins must exceed 0.1 inch spacing from all other traces or other conducting material. The purpose for this pacing is to maintain 1000 VAC isolation between the phone line and the other traces. Traces should have a nominal width of 0.020 inches or greater.

QLMP6388011

Vendor:hpPackage Cooled:hpD/C:dc94

VREFL+ Lch Positive Voltage Reference Output Pin, 3.75V Normally connected to AGND with a large electrolytic capacitor and connected to VREFL− with a 0.22µF ceramic capacitor. VREFL− Lch Negative Voltage Reference Output Pin, 1.25V Normally connected to AGND with a large electrolytic capacitor and connected to VREFL+ with a 0.22µF ceramic capacitor. ZCAL Zero Calibration Cont...

QLMP6388011

Vendor:hpPackage Cooled:hpD/C:dc94

VREFL+ Lch Positive Voltage Reference Output Pin, 3.75V Normally connected to AGND with a large electrolytic capacitor and connected to VREFL− with a 0.22µF ceramic capacitor. VREFL− Lch Negative Voltage Reference Output Pin, 1.25V Normally connected to AGND with a large electrolytic capacitor and connected to VREFL+ with a 0.22µF ceramic capacitor. ZCAL Zero Calibration Cont...

QLMP6488011

Vendor:hpPackage Cooled:hpD/C:dc94

Collector-emitter voltage peak value Collector-emitter voltage (open base) Collector current (DC) Collector current peak value Total power dissipation Collector-emitter saturation voltage Collector saturation current Diode forward voltage Fall time

QLMP6523

Output skew with respect to the REF input is adjustable to compensate for PCB trace delays, backplane propagation delays or to accommodate requirements for special timing relationships between clocked compo- nents. Skew is selectable as a multiple of a time unit tU which is of the order of a nanosecond (see PLL Programmable Skew Range and Resolution Table). There are nine skew configurations available for ea...

QLMP6535

Regulates voltage over a broad operating current and temperature range Wide selection from 3.3 to 100 V Leadless package for surface mounting Ideal for high density mounting Nonsensitive to ESD Hermetically sealed glass package Specified capacitance (see Figure 2) Inherently radiation hard per MicroNote 050

QLMP-6569

Package Cooled:HPD/C:06

Power Up and Down Recommendations. There are no restrictions on the power-up or power- down conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC VH, VL, VW. The VCC ramp rate specification is always in effect.

QLMP6789

QLMP-6896

Vendor:hpPackage Cooled:97D/C:2970

The QLMP-6896/QLMP-689641/QLMP-6896 are low-noise, preci- sion voltage references with extremely low, 0.5ppm/C typical temperature coefficients and excellent, 0.02% initial accuracy. These devices feature buried-zener technology for lowest noise performance. Load-regula- tion specifications are guaranteed for source and sink currents up to 15mA. Excellent line and load regulation and low output impedance at ...

QLMP7036

-12V TCK GND TDO VCC VCC INTB- INTD- PRSNT1- RSVD PRSNT2- GND GND RSVD GND CLK GND REQ- VCC AD31 AD29 GND AD27 AD25 +3.3V C/BE3- AD23 GND AD21 AD19 +3.3V AD17 C/BE2- GND IRDY- +3.3V DEVSEL- GND LOCK- PERR- +3.3V SERR- +3.3V C/BE1- AD14 GND AD12 AD10 GND

QLMPD169

The TELUX™ series is a clear, non diffused LED for high end applications where supreme luminous flux is required. It is designed in an industry standard 7.62 mm square package utilizing highly developed InGaN technology. The supreme heat dissipation of TELUX™ allows applications at high ambient temperatures. All packing units are binned for luminous flux and color to achieve best homogen...

QLMPJ593STR

QLMPK146STR

QLMPK385

The IC41C1665 and the IC41LV1665 are CMOS DRAMs optimized for high-speed bandwidth, low-power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 16 address bits. These are entered nine bits (A0-A7) at a time. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first ei...

QLMPK531RR2

NOTES: 1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics. 2. Per TTL-driven input (VIN = 3.4V). A and B pins do not contribute to ∆Icc. 3. This current applies to the control inputs only and represents the current required to switch internal capacitance at the specified frequency. The A and B inputs generate no significant AC or DC curre...

QLMP-P147-QR011

Vendor:JATPackage Cooled:AGILENTD/C:05+

<1mV/mA (see Figure 1) Low Crosstalk Between Switches Pin Compatible with SN74HC4052, SN74LV4052A, and CD4052B 2-V to 6-V VCC Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101)

QLMP-P147-QR011

Vendor:JATPackage Cooled:AGILENTD/C:05+

<1mV/mA (see Figure 1) Low Crosstalk Between Switches Pin Compatible with SN74HC4052, SN74LV4052A, and CD4052B 2-V to 6-V VCC Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101)

QLMT-PH49-ST014

Vendor:AGILENT ?Package Cooled:2002?D/C:4996

The Hyundai HYM72V64C736AT4 Series are 64Mx72bits ECC Synchronous DRAM Modules. The modules are composed of eigh- teen 64Mx4bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on 512Mbytes memory. The Hyundai HYM72V64C736AT4 Series are full...

QLOGIC10811-00

The MWS W-CDMA is a high- efficiency linear amplifier targeting 3V mobile handheld systems. The device is manufacturedinanadvanced InGaP/GaAs Heterojunction Bipolar Transistor (HBT) RF IC fab process. It is designed for use as a final RF amplifier in 3V W-CDMA and CDMA2000, spread spectrum systems,

QLS20ZG-NT

• AC RIPPLE VOLTAGE: Permissible AC ripple volt- age is related to the ESR of the capacitor and the power dissipation capabilities of a particular case size. Thermal capacities for the various case sizes have been determined empirically and are listed below. For additional description see page 78.

QLS30ZA

FEATURES Low Cost Single (AD8057) and Dual (AD8058) High Speed 325 MHz, C3 dB Bandwidth (G = +1) 1000 V/ s Slew Rate Gain Flatness 0.1 dB to 28 MHz Low Noise 7 nV/Hz Low Power 5.4 mA/Amplifier Typical Supply Current @ +5 V Low Distortion C85 dBc @ 5 MHz, RL = 1 k Wide Supply Range from 3 V to 12 V Small Packaging AD8057 Available in SOIC-8 and SOT-23-5 AD8058 Available in SOIC-8 and SOIC

QLT2012-4R7K-SP

Vendor:台产Package Cooled:O805D/C:03+

QLT702

Vendor:LTPackage Cooled:DIPD/C:98+

Bank Select Address (BA0 and BA1) defines which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. CAS, in conjunction with the RAS and WE, forms the device command. See the Command Truth Table for details on device commands.