Index "Q"Vendor:FAIRCHILDPackage Cooled:06+D/C:06+
PAGE READ: The page read operation of the device is controlled by CE, OE, and AVD inputs. The CLK input is ignored during a page read operation and should be tied to GND. The page size can be four words (default value) or eight words depending on what value bit B14 of the burst configuration register is programmed to. During a page read, the AVD signal can transi- tion low and then transition high, transit...
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n No special start-up sequence required between clock/data and /PD pins. Input signal (clock and data) can be applied either before or after the device is powered. n Support Spread Spectrum Clocking up to 100kHz frequency modulation & deviations of 2.5% center spread or −5% down spread. n "Input Clock Detection" feature will pull all LVDS pairs to logic low when input clock ...
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n No special start-up sequence required between clock/data and /PD pins. Input signal (clock and data) can be applied either before or after the device is powered. n Support Spread Spectrum Clocking up to 100kHz frequency modulation & deviations of 2.5% center spread or −5% down spread. n "Input Clock Detection" feature will pull all LVDS pairs to logic low when input clock ...
The device utilizes advanced temperature compensation for the high-pass filter, sensitivity, and the Schmitt trigger switchpoints, guaranteeing optimal operation to low frequencies over a wide range of air gaps and temperatures.
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Life Support Policy: HY-LINE does not authorize the use of any of its products for use in life support devices or systems without the express written approval of an officer of the Company. Life support systems are devices which support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in sign...
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High Data Integrity Applications Data storage applications that use Flash memory or other non-volatile media must take into consideration the possibil- ity of noise or other adverse system conditions that may affect data integrity. For those applications that require higher levels of data integrity it is a recommended practice to use Error Correcting Code (ECC) techniques. The NexFlash Serial Flash De...
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VBUS Pulsing: USB20H04 will drive VBUS long enough to cause the capacitance on VBUS to be charged to 2.1V when connected to an OTG Host. Because the maximum allowed capacitance on a dual-role OTG device is 6.5uF, the line will be driven to at least 2.1V. This pulse will wake up the sleeping OTG Host. However, if the USB20H04 is connected to a standard host, the capacitance will be greater than 96uF; therefo...
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VBUS Pulsing: USB20H04 will drive VBUS long enough to cause the capacitance on VBUS to be charged to 2.1V when connected to an OTG Host. Because the maximum allowed capacitance on a dual-role OTG device is 6.5uF, the line will be driven to at least 2.1V. This pulse will wake up the sleeping OTG Host. However, if the USB20H04 is connected to a standard host, the capacitance will be greater than 96uF; therefo...
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Vendor:QTPackage Cooled:10D/C:1590
Internal Organization When ORG is connected to VDD or ORG is floated, the (´16) memory organi- zation is selected. When ORG is tied to VSS, the (´8) memory organization is selected. There is an internal pull-up resistor on the ORG pin. (HT93LC66-A)
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• Plastic package has Underwriters Laboratory Flammability Classification 94V-0 • Dual rectifier construction, positive center tap • Metal silicon junction, majority carrier conduction • Low power loss, high efficiency • Guardring for overvoltage protection • For use in low voltage, high frequency inverters, free wheeling, and polarity protection applications R...
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All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.
The EL2245 and EL2445 also feature an extremely wide output voltage swing of 13.6V with VS = 15V and RL = 1kΩ. At 5V, output voltage swing is a wide 3.8V with RL = 500Ω and 3.2V with RL = 150Ω. Furthermore, for single-supply operation at +5V, output voltage swing is an excellent 0.3V to 3.8V with RL = 500Ω.
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High voltage line feeding Internal ring and metering signal injection Sensing of transversal and longitudinal line current Reliable 170 V Smart Power Technology Battery voltage C 24 V C 80 V Boosted battery mode for long telephone lines and up to 85 Vrms balanced ringing • Polarity reversal • Small P-DSO-20-5 power package
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Organization . . . 512K 16 2 Banks 3.3-V Power Supply ( 10% Tolerance) Two Banks for On-Chip Interleaving (Gapless Accesses) High Bandwidth C Up to 83-MHz Data Rates CAS Latency (CL) Programmable to 2 or 3 Cycles From Column-Address Entry Burst Sequence Programmable to Serial or Interleave Burst Length Programmable to 1, 2, 4, 8, or Full Page Chip Select and Clock Enable for Enhanced-System Interfacin...
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2. Using a CAS-before-RAS refresh cycle. CAS-before- RAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 10-bit counter provides the row ad- dresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state du...
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The CHARGE pin gives full control of the part to the user. Driving CHARGE low puts the part in shutdown. The DONE pin indicates when the part has completed charging. The QTLP670C-IW series of parts are housed in tiny low profile (1mm) SOT-23 packages.
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The DM9601 provides USB transceiver which is compliant with USB1.1, 10/100M PHY, MAC controller, memory controller and an external MII interface, to connect HPNA device or other transceivers that support MII interface. This chip already integrates into 16K byte
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"Write Disturb" means a phenomenon that frequent write cycles executed to pages in Flash memory may cause a data error in another page to which write operations are not performed. For example, 20,001 to 50,000 write operations performed to pages other than page "n" may cause a 1-bit error in page "n".
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"Write Disturb" means a phenomenon that frequent write cycles executed to pages in Flash memory may cause a data error in another page to which write operations are not performed. For example, 20,001 to 50,000 write operations performed to pages other than page "n" may cause a 1-bit error in page "n".
Using the latest high voltage technology based on a patented strip layout, STMicroelectronics has designed an advanced family of IGBTs, the PowerMESH™ IGBTs, with outstanding performances. The built in collector-gate zener exhibits a very precise active clamping while the gate-emitter zener supplies an ESD protection.
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SOFTWARE DATA PROTECTION: A software controlled data protection feature has been implemented on the AT28C010-12DK. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C010-12DK is shipped from Atmel with SDP disabled.
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The e1217X is an integrated circuit in CMOS silicon gate technology for analog watches. It consists of a 32-kHz oscillator, frequency dividers down to 1/64 Hz, output pulse formers and push-pull motor drivers. Integrated capacitors are provided (select- able mask option) for tuning of the crystal. Low current consumption and high oscillator stability are enabled by an on-chip voltage regulator.
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The functions for this block are: 1. Decode the internal address bus to generate chip selects to each block. 2. Contains internal registers whose outputs are control bits used by internal blocks for control/selection. 3. Summarizes all system IRQs (UART, CODEC, etc.) to generate a single AudioPCI 97 IRQ to the host. This also includes the playback and record DMA channels. Any IRQ masking is performed wi...
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Vendor:QT ?Package Cooled:N/A?D/C:4000
NOTES: 1. Designators in TYPE: P: power supply and ground, DI: digital input, DO: digital output, AI: analog input, AO: analog output 2. Must be connected to ground with a bypass capacitor. The recommended value is 0.1 µF to 0.22 µF, however it depends on the application environment. Refer to the optical black level clamp loop section for details. 3. Must be connected to ground with a bypas...
To remove this residual error, Thaler Corporation has developed a nonlinear compensation network of thermistors and resistors that is used in the VRE114 series references. This proprietary network eliminates most of the nonlinearity in the voltage vs. temperature function. By then adjusting the slope, Thaler Corporation produces a very stable voltage over wide temperature ranges. This network is less than...
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Vendor:FAIRCHILDPackage Cooled:06+D/C:发光管
NOTES: 1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to applying inputs on the I/Os and controls for that port. 2. OPTX selects the operating voltage levels on that port. If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that port's I/Os and controls will operate...
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TACHYON Architecture Tachyon TL continues with the TACHYON architecture, a complete hardware-based state machine design. This architec- ture does not require an addi- tional on-board microprocessor and therefore avoids reduced performance issues relating to processor cycles per second and access time to firmware. Rather, the TACHYON architecture is designed to be a single chip Fibre Channe...
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TAOperating free-air temperatureC55125070C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Vendor:QT ?Package Cooled:N/A?D/C:1000
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum. Al...
Vendor:QT ?Package Cooled:N/A?D/C:1000
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum. Al...
Vendor:FAIRCHILDPackage Cooled:06+D/C:08+
Second, keep the maximum currents relatively large (1mA or 2mA) to minimize the error due to Q7. Higher currents could be used, but the small geometry transistors used in the 8038 could give problems due to VCE(SAT) and bulk resistance, etc.
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