Q4030LH5

Vendor:6008Package Cooled:Teccor/LittelfuseD/C:N/A

50mVp-p 50mVp-p 50mVp-p 50mVp-p 50mVp-p 75mVp-p 75mVp-p 120mVp-p 150mVp-p 100mVp-p 50 / 75mVp-p 50 / 75mVp-p 50 / 75mVp-p 50 / 75mVp-p 50mVp-p 50mVp-p 50mVp-p 50mVp-p 50mVp-p 75mVp-p 75mVp-p 120mVp-p 150mVp-p 100mVp-p 50 / 75mVp-p 50 / 75mVp-p 50 / 75mVp-p 50 / 75mVp-p 50mVp-p 50mVp-p 50mVp-p 50mVp-p 50mVp-p 75mVp-p 75mVp-p 120mVp-p 150mVp-p 100mVp-p...

Q4035NH5

Vendor:TECCORPackage Cooled:05+

NOTES: (1) This part may also be used in Pollution Degree 3 environments where the rated mains voltage is 300Vrms (per DIN VDE0109/12.83). (2) IMRR = 20 log (∂VIN/∂VISO). (3) Time averaged value. (4) VIN+ = VINC = VCM. CMRR = 20 log (∂VCM/∂VOS). (5) The slope of the best-fit line of (VOUT+ C VOUTC) vs (VIN+ CVINC). (6) Change in nonlinearity vs temperature or supply voltage expressed ...

Q4035RH5

Vendor:6008Package Cooled:Teccor/LittelfuseD/C:N/A

The AHC240 devices are organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

Q4035RH5

Vendor:6008Package Cooled:Teccor/LittelfuseD/C:N/A

The AHC240 devices are organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

Q4040J7

Vendor:LF(TEC)Package Cooled:TO-218D/C:07+

Once the FIFO has been enabled (pin 23 high), digital data is automatically written to it, regardless of the status of FIFO READ (pin 10). Assuming the FIFO is initially empty, it will accept data (18-bit words) from the next 16 consecutive A/D conversions. As a precaution, pin 10 (which controls the FIFO's READ function) should not be low when data is first written to an empty FIFO.

Q4040J7

Vendor:LF(TEC)Package Cooled:TO-218XD/C:07+

Once the FIFO has been enabled (pin 23 high), digital data is automatically written to it, regardless of the status of FIFO READ (pin 10). Assuming the FIFO is initially empty, it will accept data (18-bit words) from the next 16 consecutive A/D conversions. As a precaution, pin 10 (which controls the FIFO's READ function) should not be low when data is first written to an empty FIFO.

Q40ALQ8-1AA3

Note 1: Absolute maximum ratings are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of Electrical Characteristics provide conditions for actual device operation.

Q4112-0003

Q4123-A

Vendor:COILCRAFT/线艺Package Cooled:/D/C:02+

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values ar...

Q416ATS

Vendor:QUALCOMMPackage Cooled:PLCC44D/C:08+

Q42724211000200

Vendor:SEIKO EPSON CORP

Q4401I-1S1

Vendor:UALCOMMPackage Cooled:PQFP

No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property lose.

Q45ULIU64BCR

Q4648

Vendor:QTCPackage Cooled:06+D/C:00+

Q474F

Vendor:NQRTELPackage Cooled:QFPD/C:03+

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltages...

Q4760

Vendor:PHILIPSD/C:08+

Input coupling capacitor which blocks the DC voltage at the amplifiers input terminals. Also creates a high-pass filter with Ri at fc = 1/(2RiCi). Refer to the section Proper Selection of External Components, for an explanation of how to determine the value of Ci.

Q48SL12010N12FA

Q48T20050-NBB0

Vendor:DI/DTPackage Cooled:214D/C:25

Signal Processors (DSPs) − TMS320C62x − 5-, 4-, 3.33-ns Instruction Cycle Time − 200-, 250-, 300-MHz Clock Rate − Eight 32-Bit Instructions/Cycle − 1600, 2000, 2400 MIPS C6202 and C6203B GLS Ball Grid Array (BGA) Packages are Pin-Compatible With the C6204 GLW BGA Package† C6202B and C6203B GNZ and GNY Packages are Pin-Compatible VelociTI Advanced Very-Lo...

Q48T25033-NBBO

Q48T25033NBCO

Q48T30015-NAA0

Q48T30015-NBB0

The MC623 consists of a positive temperature coefficient (PTC) temperature sensor and dual threshold detector. Temperature set point programming is easily accomplished with external programming resistors from the HIGH SET and LOW SET inputs to VCC. The HIGH LIMIT and LOW LIMIT outputs remain inactive (low) as long as the measured temperature is below setpoint values. As temperature increases, the LOW ...

Q4N3RP

Vendor:200008Package Cooled:Teccor/LittelfuseD/C:N/A

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute max- imum rating conditions for extended periods may affect device reliability.

Q4N4RP

Vendor:200008Package Cooled:Teccor/LittelfuseD/C:N/A

RS is perhaps the easiest to measure accurately. The V-I curve is measured for the diode under forward bias, and the slope of the curve is taken at some relatively high value of current (such as 5 mA). This slope is converted into a resistance Rd.

Q4X3LRP

Vendor:LF(TEC)Package Cooled:DO-214D/C:06+

N1 (IOH) = total maximum output high current for all outputs tied to pull-up resistor N2 (IIH) = total maximum input high current for all inputs tied to pull-up resistor N3 (IIL) = total maximum input low current for all inputs tied to pull-up resistor

Q4X3RP

Vendor:200008Package Cooled:DO-214D/C:N/A

VIA Twister chip with Integrated S3 Savage4 2D/3D/ Video Accelerator 8/16/ 32 MB frame buffer using system memory CRT Mode:1280 x 1024@16 bpp (60 Hz), 1024 x 768@16 bpp (85 Hz) LCD/Simultaneous Mode: 1280 x1024@16bpp (60 Hz), 1024 x 768@16 bpp (60 Hz) 4X AGP VGA/LCD interface, Support for 9, 12, 18, 24, 36,48-bit TFT and 16 or 24-bit DSTN panels up to SXGA resolution. 2-Channel ( 2 x 18-bit) LVDS interfac...

Q4X3RP

Vendor:200008Package Cooled:Teccor/LittelfuseD/C:N/A

VIA Twister chip with Integrated S3 Savage4 2D/3D/ Video Accelerator 8/16/ 32 MB frame buffer using system memory CRT Mode:1280 x 1024@16 bpp (60 Hz), 1024 x 768@16 bpp (85 Hz) LCD/Simultaneous Mode: 1280 x1024@16bpp (60 Hz), 1024 x 768@16 bpp (60 Hz) 4X AGP VGA/LCD interface, Support for 9, 12, 18, 24, 36,48-bit TFT and 16 or 24-bit DSTN panels up to SXGA resolution. 2-Channel ( 2 x 18-bit) LVDS interfac...

Q4X4LRP

Vendor:LF(TEC)Package Cooled:DO-214D/C:06+

NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 Ω, tr v 2.5 ns, tf v 2.5 ns. C. The outputs are measured one at a time with one input transition per measurement.

Q4X4RP

Vendor:200008Package Cooled:Teccor/LittelfuseD/C:N/A

Assembly Procedure Epoxy or eutectic die attach are both acceptable attachment methods. Top and bottom metallization are gold. Conductive silver-filled epoxies are recommended. This procedure involves the use of epoxy to form a joint between the backside gold of the chip and the metallized area of the substrate. A 150C cure for 1 hour is necessary. Recommended epoxy is Ablebond 84-1LMI from Ablestik.

Q4X8E3

Vendor:70008Package Cooled:Teccor/LittelfuseD/C:N/A

The UCC3813-0/-1/-2/-3/-4/-5 family offers a variety of package options, temperature range options, choice of maximum duty cycle, and choice of critical voltage levels. Lower reference parts such as the UCC3813-3 and UCC3813-5 fit best into battery operated systems, while the higher reference and the higher UVLO hysteresis of the UCC3813-2 and UCC3813-4 make these ideal choices for use in off-line power ...

Q4X8E4

Vendor:100008Package Cooled:Teccor/LittelfuseD/C:N/A

The DEU is used for bulk data encryption. It can also execute the Triple-DES algorithm, which is based on DES. The host processor supplies data to the DEU as input, and this data is encrypted and made available for reading. The session key is input to the DEU prior to encryption. The DEU computes the data encryption standard algorithm (ANSI X3.92) for bulk data encryption and decryption.

Q5000-0019B

Vendor:AMCCPackage Cooled:PGA

Q5000-0024B

Q5000-0025B

Q5000-0040B

Q5000T-0012B QMV332AY1

Vendor:AMCCPackage Cooled:CPGA225D/C:96/97

Q5000T-0013B

Package Cooled:06+D/C:800

Figure 4 shows the typical effect of the coarse and fine tuning mechanisms. The difference in VCXO frequency in parts-per-million (ppm) is shown as the fine tuning volt- age on the XTUNE pin varies from 0V to 5V. The coarse tune range as shown is about 350ppm. As the crystal load capacitance is increased (with increasing Coarse Tune setting) the frequency is pulled somewhat less with each coarse step...

Q5000T-0019A

Q5000T-0019B 160-6559-00

Vendor:AMCCPackage Cooled:CPGA149D/C:93/94

Q5000T0050B

Sirenza Microdevices SVG-2066 is an IC based 6-bit digi- tal 31.5dB range attenuator cascaded with a linear class A amplifier in a low-cost surface-mountable 6x6 QFN plastic package. This product is specifically designed as a high lin- earity variable gain amplifier for infrastructure equipment that can be used in either the RF transmit or RF receive path. It features both parallel or serial programmability, ...

Q5000T-0053A

Vendor:AMCCPackage Cooled:PGA

NOTES: (1) If clock is stopped between input of 18-bit data words, latch enable (LE) must remain low until after the first clock of the next 18-bit data word stream. (2) Data format is binary twos complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Latch enable (LE) must remain low at least one clock cycle after going negative. (4) Latch enable (LE) must be hig...

Q5006FT1

Q5006T

Q5008FT1

Q5008L4A

Q5008LTA

Q5010A

Q5010FT1

Q5010LT

Vendor:TECCORPackage Cooled:TO-220

The SN74LVC16373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

Q5015H

Q5025C

Q5025L5

Four stereo 24-bit multi-bit sigma delta DACs are used with oversampling digital interpolation filters. Digital audio input word lengths from 16-32 bits and sampling rates from 8kHz to 192kHz are supported. Each DAC channel has independent digital volume and mute control.

Q5025L6

Vendor:TECCORPackage Cooled:TO-220

Q5040P

Vendor:TECCORPackage Cooled:MU-211

Four package terminals are used as inputs to set four configuration status bits in the self-identification (Self-ID) packet. These terminals are hardwired high or low as a function of the equipment design. PC0 C PC2 are the three terminals that indicate either the need for power from the cable or the ability to supply power to the cable. The fourth terminal, C/LKON, indicates whether a node is a contender...

Q511(6503B)

D/C:06+PB

Stresses above the ratings listed below can cause permanent damage to the ICS601-01. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods ...

Q5112-14N

The shaft locking device consists of a tapered nut tightening a slotted notched washer against both bushing and shaft. DBAN tightening torque is 200 Ncm, shaft locking torque being 30 Ncm. DBAN is also available with all special types. This device is normally supplied in a separate bag. Can be pre-mounted on request.

Q5112-1N

Vendor:QUALCOMD/C:07/08+

Input Equivalent Circuit To prevent static charges, protective diodes are provided for each pin except the power supply. In addition, protective resistors are added to all pins except video signal input. The equivalent circuit of each input pin is shown below. (The resistor value: typ.)

Q5114

Vendor:QUALCOMMPackage Cooled:PLCC68D/C:07/08+

Q5114

Vendor:QUALCOMMPackage Cooled:PLCC68D/C:07/08+

Q5114C-1N

Vendor:QUALCOMMPackage Cooled:PLCCD/C:07+

For example, the part may be programmed to use S0, S1, and S2 (0,0,0 to 1,1,1) to control eight different values of P and Q on PLL1. For each PLL1 P and Q setting, one of the two CLKA and CLKB divider registers can be chosen. Any divider change as a result of switching S0, S1, or S2 is guaranteed to be glitch free.

Q5114C-1N

Vendor:QUALCOMMD/C:07+

For example, the part may be programmed to use S0, S1, and S2 (0,0,0 to 1,1,1) to control eight different values of P and Q on PLL1. For each PLL1 P and Q setting, one of the two CLKA and CLKB divider registers can be chosen. Any divider change as a result of switching S0, S1, or S2 is guaranteed to be glitch free.

Q5114C2N

©2002 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROP...

Q5116

Vendor:QUALCOMMPackage Cooled:PLCCD/C:08+

Interrupt. In the write-read mode, the interrupt output (INT) going low indicates that the internal count-down delay time, td(int), is complete and the data result is in the output latch. The delay time td(int) is typically 800 ns starting after the rising edge of WR (see operating characteristics and Figure 3). If RD goes low prior to the end of td(int), INT goes low at the end of td(RIL) and the convers...

Q51161-1N

Vendor:QUALCOMMPackage Cooled:PLCCD/C:99

Housed in SOIC−8 or PDIP−8 package, the NCP1201 enhances the previous NCP1200 series by offering a reduced optocoupler current with additional Brownout Detection Protection (BOK). Similarly, the circuit allows the implementation of complete off−line AC−DC adapters, battery chargers or Switchmode Power Supplies (SMPS) where standby power is a key parameter. The NCP1201 features e...

Q51161-1N

Vendor:QUALCOMMPackage Cooled:PLCCD/C:99

Housed in SOIC−8 or PDIP−8 package, the NCP1201 enhances the previous NCP1200 series by offering a reduced optocoupler current with additional Brownout Detection Protection (BOK). Similarly, the circuit allows the implementation of complete off−line AC−DC adapters, battery chargers or Switchmode Power Supplies (SMPS) where standby power is a key parameter. The NCP1201 features e...

Q5142

Vendor:N/APackage Cooled:DIPD/C:02+

Q5155J

Vendor:飞利蒲Package Cooled:N/AD/C:9+

3.3 Reference and Clock An internal bandgap circuit is used to generate all necessary reference voltages and currents. The on-chip crystal oscillator is used to generate 20MHz reference clocks for the internal circuits. For precision clock generation, a 20MHz-30 100ppm crystal should be used. And two 30pF load capacitors should be connected from X1 and X2 to ground, respectively. If an external clock source ...

Q516012S1

Q51601-2SI

Vendor:QUALCPackage Cooled:QFPD/C:08+09+

For more information on the PWP package, refer to TI technical brief, literature number SLMA002. Test board conditions: 1. 3 x 3, 4 layers, thickness: 0.062 2. 1.5 oz. copper traces located on the top of the PCB 3. 1.5 oz. copper ground plane on the bottom of the PCB 4. 0.5 oz. copper ground planes on the two internal layers 5. 12 thermal vias (see Recommended Land Pattern in applications section...

Q5160-2S1

Vendor:QUAICOMMPackage Cooled:QFPD/C:08+09+

The offset adder and the reverse-carry adder are in parallel and share common inputs. The only difference between them is that the carry propagates in opposite directions. Test logic determines which of the three summed results of the full adders is output.

Q5160I-2S1

The ISR functions normally with pin 1 open-circuit, providing a regulated output whenever a valid source voltage is applied to Vin, (pins 2, 3, & 4). When a low-level2 ground signal is applied to pin 1 the regulator output is disabled, and the input current to the ISR is reduced to about 100µA 3/.

Q51651-1S2

Vendor:QUALCPackage Cooled:QFPD/C:08+09+

CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase software code. After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time to erase the chip is tEC.

Q51651-1S2

Vendor:QUALCPackage Cooled:QFPD/C:08+09+

CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase software code. After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time to erase the chip is tEC.

Q51651-IS2

Vendor:TIPackage Cooled:QFPD/C:04+

System Reliability: Battery-backed SRAM is inherently vulnerable to shock and vibration. In addition, a negative voltage, even a momentary undershoot, on any pin of a battery-backed SRAM can cause data loss. The negative voltage causes current to be drawn directly from the battery, weakens the battery, and reduces its capacity over time. In general, there is no way to monitor the lost battery capacity. MRAM ...

Q51651-IS2

Vendor:TIPackage Cooled:QFPD/C:04+

System Reliability: Battery-backed SRAM is inherently vulnerable to shock and vibration. In addition, a negative voltage, even a momentary undershoot, on any pin of a battery-backed SRAM can cause data loss. The negative voltage causes current to be drawn directly from the battery, weakens the battery, and reduces its capacity over time. In general, there is no way to monitor the lost battery capacity. MRAM ...

Q5165I-152

Vendor:.Package Cooled:QFPD/C:03+

Q5165I-1S2

The CY7C133 (master) and CY7C143 (slave) consist of an array of 2K words of 16 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. The CY7C133 and CY7C143 have an automatic power-down f...

Q5165I-1S2-CD90-21580-1

Vendor:QUALCOMMD/C:05+

Adjustable regulator output (Regulator #1) C It is recommended to bypass to GND with at least 2.2µF. Size your output capacitor to meet the transient loading requirement. If you have a very dynamic load, a lower ESR capacitor will improve the response to these load steps.

Q5180C-1S1(CD90-14460-1)

Vendor:QUALCOMMPackage Cooled:QFPD/C:2000

Q5180C-1SI

integration. Output short-circuit protection and over-temperature shutdown enables these modules to survive any load fault. Two self- diagnosotic signals, Power Good (PWRGD*) and Over-Voltage Flag (OVF*) are provided. And a unique tracking feature allows the output to be synchronized to a master ramp voltage during power-up. Other features include a standby input, and a differential remote sense ...

Q5180C-ISI

Notes : 1. H : High ( inactive) L : Low ( active) D : H or L 2. tWCS >= 0ns Early write cycle twcs <=0ns Delayed write cycle 3. Mode is determined by the OR function of the /UCAS and /LCAS (mode is set by earliest of /UCAS and /LCAS active edge and reset by the latest of /UCAS and /LCAS inactive edge), However write operation and output High-Z control are done independently by each /UCAS, /...

Q5180C-ISI CD90-14460-1

Vendor:QVALCOMPackage Cooled:QFPD/C:01+

Q5180-ISI

1. Typical sensitivity data is based on a 10-3 bit error rate (BER), using DC-balanced data. There are two test methods commonly used to measure OOK/ASK receiver sensitivity, the 100% AM test method and the Pulse test method. Sensitivity data is given for both test meth- ods. See Appendix 3.8 in the ASH Transceiver Designers Guide for the details of each test method, and for sensitivity curves for a 2.2 to 3...

Q5181C-1S1

Vendor:QUALCOMMPackage Cooled:QFPD/C:1998

A simple sleep mode was incorporated in the module when no bus activity occurs for 2 seconds. When this condition is detected, the MCU lowers the enable line to the MC33399 which in turn lowers the inhibit signal to the LT1121 regulator. The regulator goes into its standby mode and powers down the MCU. A resumption of bus activity wakes the MC33399 and the regulator switches the MCU on. In order to facil...

Q5181C-1S1 (CD90-14815-1)

Vendor:QUALCOMMD/C:99+

Q5181C-1S1 CD90-14815-1

Q5182C-1S1

Vendor:QUALCOMMPackage Cooled:QFPD/C:2001

Aluminum front panel 15" high brightness TFT color panel display Built-in full/half-size SBC Provides Pentium 4 CPU, OSD function Provides Function Keys (optional) Built-in BS-669, HPCI-6S backplane, 250W PS/2 power supply CRT/Panel display controller (by SBC) 10/100 Based LAN (by SBC) Four COM, one parallel, two USB connectors Four PCI expansion slots Two 3.5" HDD/FDD and two 5.25&qu...

Q5182C-1S1-CD90-21855-1

Q5182C-1SI

sFEATURES qOperating Voltage2.8 to 5.5V qInput Composite Video Signal 0.3Vpp qOperating Current8.0mA typ. at Vcc=3.0V qOperating Current (Power Save Mode) 70uA typ.at Vcc=3.0V qInternal 75Ω Driver Circuit (2-system drive) qInternal Low Pass Filter qBipolar Technology qPackage OutlineTVSP8

Q5182C-ISI

Package Cooled:06+D/C:800

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Q5190C-ISI

Vendor:QUALCOMMPackage Cooled:QFP208D/C:08+

sector and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7 or I/O15. Once the end of a pro- gram cycle has been detected, a new access for a read or program can begin.

Q5192C-1S1

Vendor:QUALCOMMPackage Cooled:QFPD/C:1998

The total thermal resistance from junction to ambient can be as low as 45C/W. This requires a reasonable sized PC board with at least on layer of copper to spread the heat across the board and couple it into the surrounding air. Experiments have shown that the heat spreading copper layer does not need to be electrically connected to the tab of the device. The PC material can be very effective at transm...

Q5213I-2S2

Vendor:QUALCOMMPackage Cooled:QFP-80D/C:07+

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are...

Q5213I-3S2

Vendor:QUALCOMM

Q5213I-3S2

Vendor:QUALCOMM

Q5213I-3S21

Vendor:QUALCOMM

Q5213I-4S2

Vendor:QUALCOMMD/C:07+

s Digital Tuning of Crystal Frequency s PROM for Storing Frequency Correction Information s 12 or 24 Hour Timekeeping Option s Flashing Colon s Two Switches Control All Setting Functions s High Noise Immunity s Internal Power-Up Reset Circuitry

Q5213I-4S2

Vendor:QUALCOMMD/C:07+

s Digital Tuning of Crystal Frequency s PROM for Storing Frequency Correction Information s 12 or 24 Hour Timekeeping Option s Flashing Colon s Two Switches Control All Setting Functions s High Noise Immunity s Internal Power-Up Reset Circuitry

Q5250I-1S2

Vendor:.Package Cooled:QFPD/C:03+

Q5252I-1S2

Vendor:QUALCOMMPackage Cooled:TQFPD/C:97+

The ENABLE input is TTL compatible with a turn on threshold of about 1.6V with about 150mV of hysteresis. Below 0.8V the chip is disabled and the sink outputs are off. However ENABLE must be driven below 0.4 volts to insure the minimum sleep current from VDD and output off current.