RL204TR

RL205

Vendor:MICPackage Cooled:DO-15D/C:08+ROHS

NOTES: 1. Typical values are at VCC = 3.3V, TA = 25C. 2. Not more than one output should be used to test this high power condition. Duration is less than one second. 3. Guaranteed by design but not tested. 4. Output resistance represents the total output impedence of the logic device and includes added series termination resistance.

RL206

• Monolithic Pair Closely Matched Electrical Parameters • Low Capacitance 0.1 pF Maximum at 0 Volts • Low Noise Figure Typical 7.5 dB at 26 GHz • Rugged Construction 4 Grams Minimum Lead Pull • Platinum Tri-Metal System High Temperature Stability • Polyimide Scratch Protection • Silicon Nitride Passivation Stable, Reliable Performance

RL207

Vendor:HBPackage Cooled:DO-15D/C:07+

RL207-FG-WS

RL207-T

1. MTTF calculator available at http://www.freescale.com/rf. Select Tools/Software/Application Software/Calculators to access the MTTF calculators by product. 2. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.freescale.com/rf. Select Documentation/Application Notes - AN1955. 3. Part is internally matched both on input and output.

RL207-T-RL

RL20S222G

RL20S273G

RL20S474GR36

Vendor:ＶＩＳＨＡＹ

RL20S560G

The CD54AC161 and CD74AC161 devices are 4-bit binary counters. These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This m...

RL20S680G

technology to Dolby certified customers. A Dolby System License certi- fication can be obtained by faxing a written request to Dolby Licensing Corporation, at (415) 863-1373. This request should include a description of the intended application and should be marked "Request for Dolby License Application".

RL210

Vendor:IORPackage Cooled:TO223D/C:03+

RL210Y3

RL216A

RL2260CN

RL240G3

RL240Y3

RL244093.03RG

RL2510-200-110-120-PT4

RL25120R75R

Vendor:YAGEOPackage Cooled:2512-0.75R

RL2512FK-070R012

D/C:4000

RL2512FK-070R015

D/C:328000

6. Cleaning solvents compatibility Dip cleaning with an organic solvent is recommended for removal of solder flux, dust, etc. Select a cleaning solvent from the following table. If ultrasonic cleaning is used, the severity of factors such as frequency, output power and cleaning solvent selected may cause loose wires and other defects. Make sure these conditions are correct before use. For d...

RL2512FK-070R033

Vendor:PANASONICPackage Cooled:SMDD/C:07+

Writing a value to a DAC can either be a write to the DAC register only or a combined write to both the DAC Register and its nonvolatile register. They are identical with the one exception being the register write does not entail issuing a stop condition; whereas, the nonvolatile write operation is concluded with a stop. The sequence is to issue a start, followed by the device type and bus address, with the...

RL2512FK-070R05L

Vendor:YAGEOD/C:08+

RL2512FK-070R068

Vendor:YAGEOD/C:08+

RL2512FK-070R1L

Vendor:YAGEOPackage Cooled:05+D/C:4000/REEL

RL2512FK-070R22

Vendor:YAGEOD/C:08+

RL2512FK-070R33

D/C:07+

Test conditions unless otherwise noted. T = 25˚C, Vdd = 5.0 V, 50 Ω system. 1. Typical specifications reflect RL2512FK-070R33 measured with external matching circuits. 2. OIP3 measured with 2 tones at an output power of 8 dBm/tone balanced, 11 dBm/tone push-pull, separated by 10 MHz. The suppression on the largest IM3 product is used to calculate OIP3 using a 2:1 slope rule. 3. Balun loss affe...

RL2512FK-070R33

D/C:07+

Test conditions unless otherwise noted. T = 25˚C, Vdd = 5.0 V, 50 Ω system. 1. Typical specifications reflect RL2512FK-070R33 measured with external matching circuits. 2. OIP3 measured with 2 tones at an output power of 8 dBm/tone balanced, 11 dBm/tone push-pull, separated by 10 MHz. The suppression on the largest IM3 product is used to calculate OIP3 using a 2:1 slope rule. 3. Balun loss affe...

RL2512FK-070R39

D/C:4000

The OPA860 is a versatile monolithic component designed for wide-bandwidth systems, including high performance video, RF and IF circuitry. It includes a wideband, bipolar operational transconductance amplifier (OTA), and voltage buffer amplifier.

RL2512FK-070R47L

Vendor:YAGEOD/C:08+

RL2512FK-070R68L

Vendor:YAGEOD/C:08+

RL2512FK-07R825

D/C:07+

The ispGDXVA architecture is different from traditional PLD architectures, in keeping with its unique application focus. The block diagram is shown below. The program- mable interconnect consists of a single Global Routing Pool (GRP). Unlike ispLSI® devices, there are no pro- grammable logic arrays on the device. Control signals for OEs, Clocks/Clock Enables and MUX Controls must come from design...

RL2512GK-070.033R

Package Cooled:08+D/C:55000

RL2512JR-070R2

Vendor:YAGEO

RL253

Specification is not production tested but is supported by characterization data at initial product release. Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (VDD = 4 V). 3The RL253 can tolerate absolute analog input voltages down to GND − 200 mV but the leakage current will increase. 4FS[2:0] are the three bits used in the filter re...

RL255

RL256

Optimizing the controller and the synchronous FETs results in the highest conversion efficiency over a wide load range at the switching frequencies of interest (1 MHz or greater). It also minimizes the overshoot and gate ringing associated with drive current and gate charge mismatches.

RL257

Vendor:HBPackage Cooled:DO-15D/C:07+

Receiver Section The receiver section includes the Receiver Optical Subassembly (ROSA) and amplification/ quantization circuitry. The ROSA, containing a PIN photodiode and custom trans-impedance preamplifier, is located at the optical interface and mates with the LC optical connector. The ROSA is mated to a custom IC that provides post-amplification and quantization. Also included is a Los...

RL262-101J-RC

RL262-102J-RC

RL262-153J-RC

RL262-222J-RC

RL262-471J-RC

RL280CW1KB

RL280G3M

RL280Y3

RL28163

The TP3070 and TP3071 are second-generation combined PCM CODEC and Filter devices optimized for digital switch- ing applications on subscriber line and trunk cards. Using advanced switched capacitor techniques, COMBO II com- bines transmit bandpass and receive lowpass channel filters with a companding PCM encoder and decoder. The devices are A-law and µ-law selectable and employ a conventional s...

RL290R4

RL290TWRG4B-3C

RL29337

RL305

RL307

RL311HYDEJ

Vendor:osramPackage Cooled:osramD/C:dc00

RL321301G

RL32264

Vendor:NSPackage Cooled:CAN8D/C:07/08+

TC9208M includes a physical layer configuration / polling entity, which it is use to configure the phy functions and to monitor the physical layer transceivers speed, duplex mode, link status and full duplex flow control ability for each port. The chip provides four modes for phy configurations,

RL32266

Vendor:SGPackage Cooled:CAN8D/C:07/08+

NOTES: Typical values are at TA = +25C and VCC = 12 V. BOP = operate point (output turns ON); BRP = release point (output turns OFF); Bhys = hysteresis (BOP - BRP). *Complete part number includes a suffix to identify operating temperature range (E- or L-) and package type ( -LT, -U, or -UA).

RL-3264-6-R002-F

D/C:07+

The memory has a capacity of 2605056 bit. It is organized as 212 rows by 64 columns by 16 arrays by 12 bit and allows the storage of the active part of a complete 4:1:1-TV field using a 13.5 MHz sample rate. The memory is fabricated using the same CMOS technology used for 4-Mbit standard dynamic random access memories.

RL-3264-6-R002-F 2MR

Vendor:CYNTECD/C:3264

RL-3264-6-R005-F

Package Cooled:08+D/C:07+

2.2 Initialization procedure After VCC has stabilized, the device will be in the transmit-only mode. Nine clock cycles on the VCLK pin must be given to the device for it to perform internal synchronization. During this period, the SDA pin will be in a high impedance state. On the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the most significant bit of a...

RL-3264-6-R008-F

Package Cooled:08+D/C:07+

The MCP6295 has a Chip Select input (CS) for dual op amps in an 8-pin package. This device is manufactured by cascading the two op amps, with the output of op amp A being connected to the non-inverting input of op amp B. The CS input puts the device in a Low-power mode.

RL-3264-6-R008-F

D/C:07+

The MCP6295 has a Chip Select input (CS) for dual op amps in an 8-pin package. This device is manufactured by cascading the two op amps, with the output of op amp A being connected to the non-inverting input of op amp B. The CS input puts the device in a Low-power mode.

RL-3264-9-R001-J

Package Cooled:SMDD/C:04+

RL3264L-R012-F

Package Cooled:08+D/C:07+

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

RL-3264-R003-J

D/C:44000

Output Voltage Integral Color LEDs and Matching Color Filters on Sensors Sensor is a Monolithic Silicon IC Containing a Photodiode, Operational Amplifier, Feedback Components, and Color Filter High-Output LEDs and High-Sensitivity Sensors

RL32S331G

RL33.000

RL35614

4 3 1 Command Register 4 3 2 Data Configuration Register 4 3 3 Receive Control Register 4 3 4 Transmit Control Register 4 3 5 Interrupt Mask Register 4 3 6 Interrupt Status Register 4 3 7 Data Configuration Register 2 4 3 8 Transmit Registers 4 3 9 Receive Registers 4 3 10 CAM Registers 4 3 11 Tally Counters 4 3 12 General Purpose Timer 4 3 13 Silicon Revision Register

RL3720T-R018-G

D/C:07+

Acknowledge Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowled...

RL3720T-R022-G

Vendor:CYNTECPackage Cooled:3(0805)D/C:05+

Bidirectional 3-bit input/output port. Software instructions determine the CMOS output or Schmitt trigger input with a pull-high resistor (determined by pull-high options). The PB0 and PB1 are pin-shared with the BZ and BZ, respectively. Once the PB0 and PB1 are selected as buzzer driving outputs, the output signals come from an internal PFD generator (shared with a timer/event counter).

RL3720T-R022-G

Vendor:SUSUMUPackage Cooled:3(0805)D/C:05+

Bidirectional 3-bit input/output port. Software instructions determine the CMOS output or Schmitt trigger input with a pull-high resistor (determined by pull-high options). The PB0 and PB1 are pin-shared with the BZ and BZ, respectively. Once the PB0 and PB1 are selected as buzzer driving outputs, the output signals come from an internal PFD generator (shared with a timer/event counter).

RL3720T-R025-G

Vendor:CYNTECPackage Cooled:3(0805)D/C:08+

Note 9: This parameter is guaranteed by design but is not tested. The switch contributes no propagation delay other than the RC delay of the typical On Resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).

RL3720T-R050-G

Vendor:CYNTECD/C:08+

We constantly strive to improve the quality of all our products and documentation. To this end, we recently converted to a new publishing software package which we believe will enhance our entire documentation process and product. As in any conversion process, information may have accidently been altered or deleted. We have spent an excep- tional amount of time to ensure that these documents are correct. ...

RL3720WT-R010

RL3720WT-R015-J

D/C:07+

¡The circuit application examples in this publication are provided to explain representative applications of SHARP devices and are not intended to guarantee any circuit design or license any intellectual property rights. SHARP takes no responsibility for any problems related to any intellectual property right of a third party resulting from the use of SHARP's devices. ¡Contact SHARP in order...

RL3720WT-R016-F

Package Cooled:SMDD/C:SMD

RL3720WT-R018-F

Package Cooled:06+D/C:SMD

RL3720WT-R020-F

D/C:07+

8-A Rated Output Current Replaces PT6500 Series High Efficiency (91% for PT6511) Small Footprint (0.75 in², Suffix N) Output On/Off Standby Control Output Short-Circuit Protection Over-Temperature Protection Adjustable Output Voltage Soft Startup 16-pin Mount Option (Suffixes L & F)

RL3E801A

Vendor:ROHMPackage Cooled:QFPD/C:2000

Note 1. Commercial Product : TA=0 to 70C, unless otherwise specified Industrial Product : TA=-40 to 85C, unless otherwise specified 2. Overshoot : V CC+3.0V in case of pulse width30ns 3. Undershoot : -3.0V in case of pulse width30ns 4. Overshoot and undershoot are sampled, not 100% tested

RL3E802

Vendor:RICOHPackage Cooled:QFPD/C:O212

The Hyundai HYM71V63M801 X-Series are 8Mx64bits Synchronous DRAM Modules. The modules are composed of four 8Mx16bit CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package and 2Kbit EEPROM in 8pin TSSOP package on a 144pin glass-epoxy printed circuit board. Two 0.33uF and one 0.1uF decoupling capacitors per each SDRAM are mounted on the PCB.

RL3E803

The UCC3961 provides all the circuitry required on the primary side of a secondary-side controlled power supply. It features a free running 60-kHz to 360-kHz oscillator which is synchronizable to the secondary-side PWM signal and also has the ability to accept start/stop PWM commands from the isolating pulse-edge transformer (PET). The use of an extremely small and low-cost pulse transformer allows for h...

RL3E804

for reads or writes to any location in memory. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDTs CMOS high-performance technology, these devices typically operate on only 440mW of power. The IDT70V38 is packaged in a 100-pin Thin Quad Flatpack (TQFP).

RL3E851

Vendor:RIOPackage Cooled:00+D/C:500

The device offers stereo line level inputs along with two control input pins (FORMAT, IWL) to allow operation of the audio interface in three industry standard modes. An internal op-amp is integrated on the front end of the chip to accommodate analogue input signals greater than 1Vrms. The device also has a high pass filter to remove residual DC offsets.

RL3E860

Package Cooled:NEW PARTSD/C:2003

C industry standard asynchronous SCI serial inter- face (not on all products - see device summary below) C digital Watchdog C 16-bit Timer featuring an External clock input, 2 Input Captures, 2 Output Compares with Pulse Generator capabilities C fast I2C Multi Master interface (not on all prod- ucts - see device summary) C Low voltage (LVD) reset ensuring proper power- on or power-off of the ...

RL3E860

Package Cooled:NEW PARTSD/C:2003

C industry standard asynchronous SCI serial inter- face (not on all products - see device summary below) C digital Watchdog C 16-bit Timer featuring an External clock input, 2 Input Captures, 2 Output Compares with Pulse Generator capabilities C fast I2C Multi Master interface (not on all prod- ucts - see device summary) C Low voltage (LVD) reset ensuring proper power- on or power-off of the ...

RL3E861

Package Cooled:QFP

Number of channels : 8 Resolution : set 10-bit or 8-bit Conversion time : 6.13 µs (with 16-MHz machine clock, including sampling time) Continuous conversion of multiple linked channels possible (up to 8 channels can be set) One-shot conversion mode : converts selected channel only once Continuous conversion mode : converts selected channel continuously Stop conversion mode : converts selected c...

RL3E862

Package Cooled:TQFPD/C:0351+

The leading-edge 0.15 µm / 0.12 µm CMOS 8-layer metal process and the Virtex-II architecture are optimized for high speed with low power consumption. Combining a wide vari- ety of flexible features and a large range of densities up to 10 million system gates, the Virtex-II family enhances pro- grammable logic design capabilities and is a powerful alter- native to mask-programmed gates array...

RL3E862

Package Cooled:TQFPD/C:0351+

The leading-edge 0.15 µm / 0.12 µm CMOS 8-layer metal process and the Virtex-II architecture are optimized for high speed with low power consumption. Combining a wide vari- ety of flexible features and a large range of densities up to 10 million system gates, the Virtex-II family enhances pro- grammable logic design capabilities and is a powerful alter- native to mask-programmed gates array...

RL3TC51.K

RL3TC521.5K/-1

RL3TC5274R-1.0

RL3TC5-3.24K-1

RL3TC5-30.1K-0.1

RL3TC5B100K

RL4004

LOW COST SURFACE-MOUNT PLASTIC PACKAGE +33dBm TYPICAL OUTPUT POWER 14.0dB TYPICAL POWER GAIN AT 2GHz 0.4dB TYPICAL NOISE FIGURE AT 2GHz +40dBm TYPICAL OUTPUT 3rd ORDER INTERCEPT POINT AT 2GHz 0.4 X 2400 MICRON RECESSED MUSHROOM GATE Si3N4 PASSIVATION ADVANCED EPITAXIAL HETEROJUNCTION PROFILE PROVIDES EXTRA HIGH POWER EFFICIENCY AND HIGH RELIABILITY

RL40D

Vendor:FAIPackage Cooled:SOP8

This center tap Schottky rectifier has been optimized for ultra low forward voltage drop specifically for 1.5V output power supplies. The proprietary sub-micron technology allows for low power loss both in forward and reverse conduction.

RL412A1001GD

Vendor:sovcorPackage Cooled:sovcorD/C:dc73+

RL412A1003GD

Vendor:sovcorPackage Cooled:sovcorD/C:dc80+

• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others.

RL412A12R0GD

Vendor:sovcorPackage Cooled:sovcorD/C:dc80+

This 20-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVCH20T245 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. Th...