S150MND16AS

Vendor:JAPAN INTERNATIONAL

Melexis Inc. reserves the right to make changes without further notice to any products herein to improve reliability, function o r design. Melexis does not assume any liability arising from the use of any product or application of any product or circuit described herein.

S150MQK6

Vendor:OriginPackage Cooled:150A600VD/C:N/A

where ITH is the value of current set by the external RSET resistor. If fault signals are present at the input of A1 (which is held at virtual ground, +10V), one of the two current mirrors in the feedback path of A1 (Q4 and Q5) will become active, depending on which half-cycle the fault occurs. This action will raise the voltage at VS, switching I1 to a value equal to ITH, and reducing the discharge rat...

S150MQK6

Vendor:OriginPackage Cooled:150A600VD/C:N/A

where ITH is the value of current set by the external RSET resistor. If fault signals are present at the input of A1 (which is held at virtual ground, +10V), one of the two current mirrors in the feedback path of A1 (Q4 and Q5) will become active, depending on which half-cycle the fault occurs. This action will raise the voltage at VS, switching I1 to a value equal to ITH, and reducing the discharge rat...

S151M70P

Write Protect, active Low/Accelerate (VHH). W r it e Pr ot ect Funct ion: Placing t his pin at VI L disables pr ogr am and er ase operations in two of the eight 8 KByte boot sectors. The affected sectors are sectors S0 and S1 in a bottom-boot device, or S69 and S70 in a top-boot device. If the pin is placed at VIH, the protection state of those two sectors reverts to w het her t hey w ere last set t o be...

S1523BJ6.1760

• High Blocking Voltage • Epitaxial Silicon drift region - fast switching - small tail current - low switching losses • MOS gate turn-on for drive simplicity • Molding epoxies meet UL 94 V-0 flammability classification

S15-28

Vendor:NECPackage Cooled:MODULED/C:10

S15321-F-BC

Package Cooled:BGA0909D/C:05+

* On products compliant to MIL-PRF-38535, this parameter does not apply. † All typical values are at VCC = 5 V. ‡ This limit applies only to the SN74ABT162245. The parameters IOZH and IOZL include the input leakage current. ¶ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. # This is the increase in supply current for each ...

S15323R-16

Vendor:CAUTIONPackage Cooled:SOP16LD/C:2000

Test Conditions/Comments Sampling CLKIN/128, 3.579545 MHz/128 = 27.9 kSPS See the Channel 1 Sampling section 150 mV rms/60 Hz, range = 0.5 V, gain = 2 CLKIN = 3.579545 MHz See the Channel 2 Sampling section 150 mV rms/60 Hz, gain = 2 CLKIN = 3.579545 MHz

S15323R-19

Vendor:CAUTIONPackage Cooled:SOP16LD/C:2000

Light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characteristics of semiconductor devices when irradiated with light. Consequently, the users of the packages which may expose chips to external light such as COB, COG, TCP and COF must consider effective methods to block out light from reaching the IC on all parts of the surface area, the top,...

S15323R-24

Vendor:CAUTIONPackage Cooled:SOP16LD/C:2000

In Motion Video Decompression, the S15323R-24 transfers the code stream from system memory via the S15323R-24 Codec Front End to the S15323R-24R36060, using DMA. The S15323R-24R36060 decompresses the JPEG code and transfers the video to the video encoder to be displayed on a TV monitor. The S15323R-24R36060 video output is driven simultaneously to the Video Front End of the S15323R-24 to be processed, ...

S15-48-15D

S15-48-5

The devices feature logic level input control and very low output on-resistance, making them suitable for both ac and dc loads. Connection A, as shown in the Functional Diagram, allows the device to switch either ac or dc loads. Connection B, with the polarity and pin configuration as shown, allows the device to switch dc loads only. The advantage of Connection B is that the on-resistance i...

S154CDDT12

1. Externally detect a write to the low-power address. You select this address which can be any address in the 16 Mbyte addressing range of the MC68SEC000. A write to the low-power address can be detected by polling A23CA0, R/W, and FC2CFC0. When the low-power address is detected, R/W is a logic low, and the function codes have a five (101) on their output, the processor is writing to the low-power add...

S-154CDFP12

Vendor:TEMICPackage Cooled:01+D/C:3

1. This device series contains ESD protection and exceeds the following tests: Pins 1−3: Human Body Model 2000 V per MIL−STD−883, Method 3015. Machine Model Method 200 V. Pins 4 and 5 are the HV start−up and the drain of the LDMOS device, rated only to the max rating of the part , or 700 V. 2. This device contains Latch−up protection and exceeds $200 mA per JEDEC Standard ...

S-154CV012

Vendor:TEMICPackage Cooled:PLCC

Get the insight you need to solve your debugging challenges in a fraction of the time it used to take. Just press the Autoscale key to automatically adjust the sample rate to achieve the best waveform resolution. Then, as you change the horizontal scale to display more time and view your entire signal, MegaZoom adds more memory to give you the fastest sample rate and best resolution possible. Now you c...

S154DCDGN12

Vendor:TEMICPackage Cooled:PLCC44

Normally, capacitor values on the order of several hundred microfarads are used on the output of the regulators to ensure good transient response with heavy load current changes. Output capacitance can increase without limit and larger values of output capacitance further improve the

S-154DDFC16

Vendor:TEMICPackage Cooled:PLCC

The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enable inputs or WE. WE is latched at...

S-154DDQ-16

Vendor:TEMICPackage Cooled:PLCC

Notes: 1. The anode side of the device is denoted by a hole in the lead frame. Electrical insulation between the case and the board is requiredslug of device is not electrically neutral. Do not electrically connect either the anode or cathode to the slug. 2. All dimensions are in millimeters. 3. All dimensions without tolerances are for reference only.

S-154DEX12

Vendor:ICLPackage Cooled:PLCC

READ CYCLE TRCRead Cycle Time TAAAddress Access Time TACSChip Select Access Time TOEOutput Enable to Output Valid TBA/LB, /UB Access Time TCLZChip Select to Output in Low Z TOLZOutput Enable to Output in Low Z TBLZ/LB, /UB Enable to Output in Low Z TCHZChip Deselection to Output in High Z tOHZOut Disable to Output in High Z TBHZ/LB, /UB Disable to Output in High Z TOHOutput Hold from Address Change WRI...

S-154DFG-12

Vendor:TEMICPackage Cooled:PLCC

Asasecond-generationHOTLinkdevice,the CYP(V)15G0401DXB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility (data, command, and BIST) with other HOTLink devices. The transmit (TX) section of the CYP(V)15G0401DXB Quad HOTLink II consists of four byte-wide channels that can be operated independently or bonded to form wider buses. Each...

S1554EABK-155.52MHZ

S155P155MHZ

Vendor:N/APackage Cooled:STAND3/SAND/C:N/A

S156743

S15807R-10

Vendor:CAUTIONPackage Cooled:SOP16LD/C:2000

When using JEDEC numbers, B suffix signifies +/-5% tolerance on nominal zener voltage. The suffix A is used to identify +/-10% tolerance; no suffix indicates +/-20% tolerance: suffix C is used to identify +/- 2%; and suffix D is used to identify +/- 1% tolerance.

S158B35

S159844822

Vendor:ExpressPackage Cooled:07+D/C:QFP

S15A30

Vendor:MOSPECPackage Cooled:TO-220D/C:05+

VCC IOUT Short Circuit protected to ground. Maximum reliability is obtained if IOUT does not exceed: Common-Mode Input Voltage Maximum Junction Temperature Storage Temperature Range Lead Temperature (soldering 10 sec) ESD (human body model)

S15A35P

Vendor:mospecPackage Cooled:TO-D/C:07+

Maximum Recurrent Peak Reverse Voltage Maximum RMS Bridge Input Voltage Maximum DC Blocking Voltage Maximum Average Forward Rectified Current at TA = 75 Peak Forward Surge Current: 8.3 ms single half sine-wave Superimposed on rated load (JEDEC Method) Maximum Forward Voltage at 1.0A DC @TA = 25Maximum DC Reverse Current at Rated DC Blocking Voltage@TA = 125 Maximum Reverse Recovery Time (Note 1 ) Typical...

S15A35R

Vendor:mospecPackage Cooled:TO-D/C:07+

The power up bi-directional pins have a large value pull- down each (250KΩ), therefore, a selection 0 is the default. If the system uses a slow power supply (over 5mS settling time), then it is recommended to use an external Pull-Down (Rdn) in order to insure a Low selection. In this case, the designer may choose one of two configurations, see Fig.5A and B.

S15A3OP

Vendor:mospecPackage Cooled:6000D/C:07+

V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. Connect V2MON to VSS or VCC when not used. There is no hysteresis in the V2MON comparator circuits.

S15A3OR

Vendor:mospecPackage Cooled:6000D/C:07+

Two power-saving features are embodied in the HY29DS32x. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The host can also place the device into the standby mode. Power consump- tion is greatly reduced in both these modes.

S15A3OR

Vendor:mospecPackage Cooled:6000D/C:07+

Two power-saving features are embodied in the HY29DS32x. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The host can also place the device into the standby mode. Power consump- tion is greatly reduced in both these modes.

S15A40P

Vendor:mospecPackage Cooled:TO-D/C:07+

Case: JEDEC DO-214BA, molded plastic over glass body Terminals: Solder plated, solderable per MIL-STD-750, Method 2026 Polarity: Color band denotes cathode end Mounting Position: AnyWeight: 0.0048 oz, 0.12 g Packaging codes/options: 19/6.5K per 13 Reel (12mm Tape) 17/1.5K per 7 Reel (12mm Tape)

S15A40R

Vendor:mospecPackage Cooled:TO-D/C:07+

DESCRIPTION The L4962 is a monolithic power switching regula- tor delivering 1.5A at a voltage variable from 5V to 40V in step down configuration. Features of the device include current limiting, soft start, thermal protection and 0 to 100% duty cycle for continuous operating mode.

S15A45P

Vendor:mospecPackage Cooled:TO-D/C:07+

NOTES : 1. In case of 40MHz Frequency, CL1 can be supported. 2. Samsung shall not offer for sale or sell either directly or through and third-party proxy, and DRAM memory products that include "Multi-Die Plastic DRAM" for use as components in general and scientific computers such as, by way of example, mainframes, servers, work stations or desk top computers for the first three years of five yea...

S15A45P

Vendor:mospecPackage Cooled:TO-D/C:07+

NOTES : 1. In case of 40MHz Frequency, CL1 can be supported. 2. Samsung shall not offer for sale or sell either directly or through and third-party proxy, and DRAM memory products that include "Multi-Die Plastic DRAM" for use as components in general and scientific computers such as, by way of example, mainframes, servers, work stations or desk top computers for the first three years of five yea...

S15A45R

Vendor:mospecPackage Cooled:6000D/C:07+

Low skew: < 200ps Fast switching frequency >133 MHz Fast output rise/fall time < 1.5ns Low propagation delay < 2.5ns Low input capacitance < 6.0pF 5V I/O Tolerant input Rail-to-Rail CMOS outputs Industrial Temperature: C40C to +85C 3.3V 10% operation Packaging (Pb-free & Green Available): C 20-pin 300-mil wide SOIC (S) C 20-pin 150-mil wide QSOP (Q) C 20-pin 209-mil wide ...

S15A45R

Vendor:mospecPackage Cooled:TO-D/C:07+

Low skew: < 200ps Fast switching frequency >133 MHz Fast output rise/fall time < 1.5ns Low propagation delay < 2.5ns Low input capacitance < 6.0pF 5V I/O Tolerant input Rail-to-Rail CMOS outputs Industrial Temperature: C40C to +85C 3.3V 10% operation Packaging (Pb-free & Green Available): C 20-pin 300-mil wide SOIC (S) C 20-pin 150-mil wide QSOP (Q) C 20-pin 209-mil wide ...

S15A50P

Vendor:mospecPackage Cooled:TO-D/C:07+

This evaluation board is designed to have the maximum value of VG at 400MHz. By using the value of Test Circuit1, this board can be changed to have the maximum value of PG at 400MHz. If NF is not so good, Pin 5 may have a noisy signal. In such cases, it may be effective to connect a capacitor between Pin 5 and ground. However, if the ground has a large noisy signal, NF may become worse.

S15A50R

Vendor:mospecPackage Cooled:6000D/C:07+

The CDCLVP110 clock driver distributes one differential clock pair of either LVPECL or HSTL (selectable) input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP110 can accept two clock sources into an input multiplexer. The CLK0 input accepts either LVECL/LVPECL input signals, while CLK1 accepts an HSTL input signal when op...

S15A60P

Vendor:mospecPackage Cooled:6000D/C:07+

† Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.

S15A60R

Vendor:mospecPackage Cooled:6000D/C:07+

TypeDescription P3.3 volt input supply voltage. P5.0 volt reference for 5.0 volt signaling environments and 3.3 volt reference for 3.3 volt signaling environments. PGround Pin I/OThe PCI address and data lines are multiplexed on the same PCI pins. During the first clock cycle of a transaction, the 32 bits contain an address and during subsequent clock cycles, they contain data. Both read and write burs...

S15B-PH-K-S(LF)(SN)

Vendor:JSTPackage Cooled:2008D/C:5,000

S15C30

Vendor:MOSPECPackage Cooled:TO-220D/C:02+

MATERIAL: Units are encap- sulated in a low thermal resis- tance molding compound that has excellent chemical resis- tance, wide operating tem- perature range, and good electrical properties under high humidity environments. The encapsulant and outer shell of the unit have UL94V-0 ratings. Lead material is brass with a solder plated surface to allow ease of solderability.

S15C30C

Vendor:MOSPECPackage Cooled:TO-220D/C:02+

= 111, then all 4 bits are high. If TECH[2:0] = 001, then only bit 5 is high. After reset, software can change any of these bits from a 1 to a 0; but not from a 0 to a 1. Therefore, a technology permitted by the setting of the TECH pins can be disabled, but one not permitted cannot be enabled.

S15C35

Vendor:MOSPECPackage Cooled:TO-220D/C:02+

Power Diode Module DD30GB series are designed for various rectifier circuits. DD30GB has two diode chips connected in series and the mounting base is elctrically isolated from elements for simple heatsink construction. Wide voltage rating up to, 800V is avaiable for various input voltage.

S15C35C

Vendor:MOSPECPackage Cooled:TO-220D/C:02+

The SM561 is a very simple and versatile device to use. The frequency and spread% range is selected by programming S0 and S1 digital inputs. These inputs use three (3) logic states including High (H), Low (L), and Middle (M) to select one of the

S15C40

Vendor:MOSPECPackage Cooled:TO-220D/C:02+

The DI2CM is an I2C-compatible master-IP core from Digital Core Design. Please contact Digital Core Design for any questions relating to the DI2CM IP core. See the Component Suppliers section for contact information or email Digital Core Design at info@dcd.pl for more infor- mation.

S15C40

Vendor:MOSPECPackage Cooled:TO-220D/C:02+

The DI2CM is an I2C-compatible master-IP core from Digital Core Design. Please contact Digital Core Design for any questions relating to the DI2CM IP core. See the Component Suppliers section for contact information or email Digital Core Design at info@dcd.pl for more infor- mation.

S15C40C

Vendor:MOSPECPackage Cooled:TO-220D/C:02+

Vcc = 5.0V10%, TA = 0C to 70C, unless otherwise specified. -15 Parameter# Symbol Min Max READ CYCLE 1tRCRead Cycle Time15- 2tAAAddress Access Time-15 3tACSChip Select Access Time-15 4tOEOutput Enable to Output Valid-8 5tCLZChip Select to Output in Low Z3- 6tOLZOutput Enable to Output in Low Z3- 7tCHZChip Deselecting to Output in High Z08 8tOHZOut Disable to Output in High Z08 9tOHO...

S15C45

Vendor:MOSPECPackage Cooled:TO-220D/C:02+

Notes: 1. Operation of this device in excess of any of these limits may cause permanent damage. 2. Thermal resistance measured using 150C Liquid Crystal Measurement Technique. 3. Board (package belly) temperature, Tc, is 25C. Derate 2.3 mW/C for Tc > 120.8C.

S15C45C

Vendor:MOSPECPackage Cooled:TO-220D/C:02+

Functions To provide memory addresses. During sector erase A19-A11 address lines will select the sector. During block erase A19-A15 address lines will select the block. To output data during read cycles and receive input data during write cycles. Data is internally latched during a write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To gate the ...

S15C50

Vendor:MOSPECPackage Cooled:TO-220D/C:02+

10.1 All payments required under Section 4.0 or otherwise under this Agreement are exclusive of taxes and END USER agrees to bear and be responsible for the payment of all such taxes (except for taxes based upon DVSI's income) including, but not limited to, all sales, use, rental receipt, personal property or other taxes which may be levied or assessed in connection with this Agreement.

S15C50C

Vendor:MOSPECPackage Cooled:TO-220D/C:02+

to the load side, the effective resistance between the regulator and the load is gained up by the factor of (1+ R2/R1), or the effective resistance will be RP(eff)=RP3(1+ R2/R1). It is important to note that for high current appli- cations, this can represent a significant percentage of the overall load regulation and one must keep the path from the regulator to the load as short as possible to minimize this...

S15C60

Vendor:MOSPECPackage Cooled:TO-220D/C:02+

Figure 2 shows the recovered clock (RCLK), positive data (RPOS) and negative data (RNEG) signals timing. The data is valid on the rising edge of the clock. The minimum setup and hold times allow easy interface to framer circuits. These signals are CMOS-level outputs.

S15C60C

Vendor:MOSPECPackage Cooled:TO-220D/C:02+

Notes: 1. Within-Device skew is defined for identical transitions on similar paths through a device. 2. Setup, Hold, and Disable times are all relative to a falling edge on CLK or SCLK. 3. Minimum input swing for which AC parameters are guaranteed. Full DC LVDS output swings will be generated with only 50mV input swings. 4. The range in which the high level of the input swing must fall while meeting the V...

S15C60C

Vendor:MOSPECPackage Cooled:TO-220D/C:02+

Notes: 1. Within-Device skew is defined for identical transitions on similar paths through a device. 2. Setup, Hold, and Disable times are all relative to a falling edge on CLK or SCLK. 3. Minimum input swing for which AC parameters are guaranteed. Full DC LVDS output swings will be generated with only 50mV input swings. 4. The range in which the high level of the input swing must fall while meeting the V...

S15D30A

Vendor:mospecPackage Cooled:TO-D/C:07+

NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage rating...

S15D30A

Vendor:mospecPackage Cooled:TO-D/C:07+

NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage rating...

S15D30C

Vendor:mospecPackage Cooled:6000D/C:07+

where N is the number of cells, R2 is connected to the positive battery terminal, and R3 is connected to the negative battery terminal. The single-cell battery volt- age is monitored for the end-of-discharge voltage (EDV) and for maximum cell voltage (MCV). EDV threshold levels are used to determine when the battery has reached an empty state, and the MCV threshold is used for fault detection during charging.

S15D30D

Vendor:mospecPackage Cooled:TO-D/C:07+

Virtex-E FPGAs are SRAM-based, and are customized by loading configuration data into internal memory cells. Con- figuration data can be read from an external SPROM (mas- ter serial mode), or can be written into the FPGA (SelectMAP™, slave serial, and JTAG modes).

S15D30D

Vendor:mospecPackage Cooled:TO-D/C:07+

Virtex-E FPGAs are SRAM-based, and are customized by loading configuration data into internal memory cells. Con- figuration data can be read from an external SPROM (mas- ter serial mode), or can be written into the FPGA (SelectMAP™, slave serial, and JTAG modes).

S15D35A

Vendor:mospecPackage Cooled:TO-D/C:07+

*COMMENT Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliab...

S15D35C

Vendor:mospecPackage Cooled:TO-D/C:07+

A powerful program sequencer controls the flow of instruction execution, including instruction alignment and decoding. The sequencer supports conditional jumps and subroutine calls, as well as zero-overhead looping. A loop buffer stores instructions locally, eliminating instruction memory accesses for tightly looped code.

S15D35D

Vendor:mospecPackage Cooled:TO-D/C:07+

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. 318F−01, −02, −03 OBSOLETE. NEW STANDARD 318F−04.

S15D35D

Vendor:mospecPackage Cooled:TO-D/C:07+

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. 318F−01, −02, −03 OBSOLETE. NEW STANDARD 318F−04.

S15D40A

Vendor:mospecPackage Cooled:TO-D/C:07+

LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the corre- sponding buffer byte is enabled, and when HIGH, dis- abled. The outputs go to the HIGH Impedance State when LDQM/UDQM is HIGH. This function corresponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer. When L...

S15D40C

Vendor:mospecPackage Cooled:TO-D/C:07+

In AM mode the AM mixer, the AM RF-AGC and the 1st IF AM amplifier at pin 33 are activated. The input of the 2nd IF amplifier is connected to pin 28 and the output of the 2nd IF amplifier is fed to the AM demodulator. The output of the AM demodulator is available at MPX output pin 11.

S15D40C

Vendor:mospecPackage Cooled:TO-D/C:07+

In AM mode the AM mixer, the AM RF-AGC and the 1st IF AM amplifier at pin 33 are activated. The input of the 2nd IF amplifier is connected to pin 28 and the output of the 2nd IF amplifier is fed to the AM demodulator. The output of the AM demodulator is available at MPX output pin 11.

S15D40D

Vendor:mospecPackage Cooled:TO-D/C:07+

with mask-programmable ROM, 12 MHz for external memory, 12 MHz with mask-programmable ROM, 12 MHz ext. temperature C 40 to + 85 ˚C for external memory, 12 MHz ext. temperature C 40 to + 85 ˚C with mask-programmable ROM, 16 MHz for external memory, 16 MHz for external memory, 16 MHz ext. temperature C 40 to + 85 ˚C for external memory, 20 MHz for external memory, 12 MHz with mask-progra...

S15D45A

Vendor:mospecPackage Cooled:TO-D/C:07+

FAST data sheets carry several types of AC information. The AC Characteristics table contains the guaranteed limits when tested under the conditions set forth under the AC Test Circuits and Waveforms. In some cases, the test conditions are further defined by the AC Setup Conditions this is generally the case with counters and flip-flops where setup and hold times are involved. All of the AC Characteri...

S15D45C

Vendor:mospecPackage Cooled:TO-D/C:07+

This IC is 1 chip driv er IC f or spindle motor and 5 channel actuators. All of the motor and actuator of optical disk driv e sy stem (CD-ROM etc.) can be driv ed by only this IC. This IC has a direct PWM control sy stem f or Spindle and Slide channels driv e due to reducing IC power dissipation. This IC has three Voltage supply terminals (f or Spindle,Slide,Focus/Tracking and Loading), and three v oltage...

S15D45D

Vendor:mospecPackage Cooled:6000D/C:07+

Connect control terminal to VIN terminal The quiescent current can be reduced by using a resistance R. Instead, it increases the minimum operating voltage. For further information, please refer to Figure Output Voltage vs. Control Voltage.

S15D45D

Vendor:mospecPackage Cooled:TO-D/C:07+

Connect control terminal to VIN terminal The quiescent current can be reduced by using a resistance R. Instead, it increases the minimum operating voltage. For further information, please refer to Figure Output Voltage vs. Control Voltage.

S15D50A

Vendor:mospecPackage Cooled:6000D/C:07+

Recommended Application: ALI - Aladdin V™ - mobile style chipsets Output Features: • 3 - CPUs @ 2.5/3.3V, up to 100MHz. • 3 - AGPCLK @ 3.3V • 13 - SDRAM @ 3.3V • 6 - PCI @ 3.3V • 1 - 48MHz, @ 3.3V fixed. • 1 - REF @ 3.3V, 14.318MHz. Features: • Support power management: CPU, PCI, AGP stop and Power down Mode from I2C programming. • Spread spectrum for ...

S15D50A

Vendor:mospecPackage Cooled:TO-D/C:07+

Recommended Application: ALI - Aladdin V™ - mobile style chipsets Output Features: • 3 - CPUs @ 2.5/3.3V, up to 100MHz. • 3 - AGPCLK @ 3.3V • 13 - SDRAM @ 3.3V • 6 - PCI @ 3.3V • 1 - 48MHz, @ 3.3V fixed. • 1 - REF @ 3.3V, 14.318MHz. Features: • Support power management: CPU, PCI, AGP stop and Power down Mode from I2C programming. • Spread spectrum for ...

S15D50C

Vendor:mospecPackage Cooled:TO-D/C:07+

The three-terminal port of the DS1804 provides an increment/decrement interface which is activated via a chip-select input. This interface consists of the input signals CS , INC , and U/ D . These input signals control a 7-bit up/down counter. The output of the 7-bit up/down counter controls a 1 of 100 decoder to select wiper position. Additionally, this interface provides for a wiper storage operation using ...

S15D50D

Vendor:mospecPackage Cooled:TO-D/C:07+

Note 1: Not tested in production. Set by design and characterization. 2: When using the device in the daisy chain configuration, maximum clock frequency is determined by a combination of propagation delay time (tDO 80 ns), data input setup time (tSU 40 ns), SCK high time (tHI 40 ns), and SCK rise and fall times of 5 ns. Maximum fSCK is, therefore, 5.8 MHz.

S15D50D

Vendor:mospecPackage Cooled:6000D/C:07+

Note 1: Not tested in production. Set by design and characterization. 2: When using the device in the daisy chain configuration, maximum clock frequency is determined by a combination of propagation delay time (tDO 80 ns), data input setup time (tSU 40 ns), SCK high time (tHI 40 ns), and SCK rise and fall times of 5 ns. Maximum fSCK is, therefore, 5.8 MHz.

S15D60A

Vendor:mospecPackage Cooled:6000D/C:07+

Figure 2 shows the recovered clock (RCLK), positive data (RPOS) and negative data (RNEG) signals timing. The data is valid on the rising edge of the clock. The minimum setup and hold times allow easy interface to framer circuits. These signals are CMOS-level outputs.

S15D60C

Vendor:mospecPackage Cooled:TO-D/C:07+

DISP high disables the LED display. DISP tied to VCC allows PROGX to connect di- rectly to VCC or VSS instead of through a pull-up or pull-down resistor. DISP floating allows the LED display to be active during charge. DISP low activates the display. See Table 1.

S15D60C

Vendor:mospecPackage Cooled:TO-D/C:07+

DISP high disables the LED display. DISP tied to VCC allows PROGX to connect di- rectly to VCC or VSS instead of through a pull-up or pull-down resistor. DISP floating allows the LED display to be active during charge. DISP low activates the display. See Table 1.

S15D60D

Vendor:mospecPackage Cooled:TO-D/C:07+

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. This product is not compati...

S15L60C

Package Cooled:07+D/C:TO-220

The accuracy of all tests is predicated on the correct use of the Kelvin connections, as indicated in the instructions for the curve tracer. This is particularly important for power semiconductors, as inductive and resistive drops across sockets and wiring are significant.

S15SC3M

Vendor:mospecPackage Cooled:TO-D/C:07+

The HT6221/HT6222 remain in the halt mode during the standby state (at this time, the oscillator stops, and the standby current<1mA). The HT6221 consists of 32 ac- tive keys, and the HT6222 has 64 active keys. The key- board forms of the HT6221/ HT6222 are shown below.

S15SC3M

Vendor:mospecPackage Cooled:TO-D/C:07+

The HT6221/HT6222 remain in the halt mode during the standby state (at this time, the oscillator stops, and the standby current<1mA). The HT6221 consists of 32 ac- tive keys, and the HT6222 has 64 active keys. The key- board forms of the HT6221/ HT6222 are shown below.

S15SC4M

Vendor:mospecPackage Cooled:TO-D/C:07+

In addition, the input active horizontal and vertical starting and ending positions can be detected to ensure that the whole picture fits into the displayable region of the screen. Through an I2C interface, the S15SC4M is fully programmable to support various graphic resolutions.

S15SC4M

Vendor:mospecPackage Cooled:TO-D/C:07+

In addition, the input active horizontal and vertical starting and ending positions can be detected to ensure that the whole picture fits into the displayable region of the screen. Through an I2C interface, the S15SC4M is fully programmable to support various graphic resolutions.

S15SCA4M

Vendor:mospecPackage Cooled:TO-D/C:07+

The circuit in Figure 4 uses the MAX5160 (a 32-tap digital pot) with two fixed precision resistors to finely tune around a specific output voltage. The tuning resolution is increased and the range is decreased as the ratio of the total fixed resistance to the digital pot resistance is increased. Table 1 shows the resistor-value selection optimized to achieve 0.5% tuning accuracy. These resistor values can b...

S15VB40

Advanced features of UCC3961 allows implementation of initial startup with optional high-voltage disconnect after starting, and input voltage monitoring with turnoff for either undervoltage or overvoltage conditions. Other features include power-switch current protection, pulse-by-pulse current limiting, shutdown after a programmable delay and continuous input volt*second clamp. The UCC3961 also provides ...

S15VB60

Vendor:-Package Cooled:NEWD/C:04+

Loop Back Select. This input is used to select the input data stream source that the Receive PLL uses for clock and data recovery. When the LOOP input is HIGH, the Receive input data stream (RIN) is used for clock and data recovery. When LOOP is LOW, the Transmit input data stream (TSER) is used by the Receive PLL for clock and data recovery.

S15VTA60

The Programmable Interconnect Matrix (PIM) connects the eight logic blocks on the CY7C375i to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM.

S16004LK6TW-75AG

Vendor:SpectekPackage Cooled:04+D/C:761

The references for the four DACs are derived from one reference pin. The outputs of all DACs may be updated simultaneously using the software LDAC function. The parts incorporate a power-on reset circuit, which ensures that the DAC outputs power up to 0 V and remain there until a valid write takes place to the device. There is also a software clear function that resets all input and DAC registers to 0 V...

S16008LK9TK-75AG

S16020

S1602D

Signal Processors (DSPs) − TMS320C62x − 5-, 4-, 3.33-ns Instruction Cycle Time − 200-, 250-, 300-MHz Clock Rate − Eight 32-Bit Instructions/Cycle − 1600, 2000, 2400 MIPS C6202 and C6203B GLS Ball Grid Array (BGA) Packages are Pin-Compatible With the C6204 GLW BGA Package† C6202B and C6203B GNZ and GNY Packages are Pin-Compatible VelociTI Advanced Very-Lo...

S1610MH

Vendor:360

• High speed tAA = 10ns • Low active power for 10 ns speed 324 mW (max.) • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features

S1610NH

Vendor:6000Package Cooled:STD/C:TO-220

VBIAS (VCC, VBS 1,2,3) = 15V unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are applicable to all six channels (HS1,2,3 and LS1,2,3). The VO and IO parameters are referenced to COM and VS1,2,3 and are applicable to the respective output leads: HO1,2,3 and LO1,2,3.

S16128U

Package Cooled:2005D/C:800

The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.

S1612B-25.000