S02147A

Vendor:SMKD/C:95

Control DC input for removing the DC offset generated in the S1M8662A and system during CDMA and GPS Mode. The control DC is generated in the modem in PDM form, passes through the R-C filter and is converted to DC, which is sent to this input terminal.

S02159B

Vendor:SMKPackage Cooled:SOP-5.2-16PD/C:6+

The Fairchild Switch FST3125 provides four high-speed CMOS TTL-compatible bus switches. The low on resis- tance of the switch allows inputs to be connected to out- puts without adding propagation delay or generating additional ground bounce noise.

S02159B

Vendor:SMKPackage Cooled:SOP-5.2-16PD/C:6+

The Fairchild Switch FST3125 provides four high-speed CMOS TTL-compatible bus switches. The low on resis- tance of the switch allows inputs to be connected to out- puts without adding propagation delay or generating additional ground bounce noise.

S02175A

Vendor:SMKPackage Cooled:SOP-5.2-20PD/C:6+

Notes: 1. See thermal regulation specifications for changes in output voltage due to heating effects. Load and line regulation are measured at a constant junction temperature by low duty cycle pulse testing. 2. Line and load regulation are guaranteed up to the maximum power dissipation. Power dissipation is determined by input/ output differential and the output current. Guaranteed maximum output power ...

S0223SMDA

Wait or Transfer Acknowledge. When configured as wait, this signal is asserted low during a memory and peripheral device bus transaction to extend the bus cycle. When configured as transfer acknowledge, this signal is asserted low dur- ing a memory and peripheral device bus transaction to signal the completion of the transaction.

S02303

Vendor:SMKPackage Cooled:SOPD/C:N/A

Remote Thermal Diode cathode (THERM_DC) - Diode 1 should always be connected to the processor thermal diode. Diode 2 may be connected to an MMBT3904 or GPU thermal diode. A 100 pF capacitor should be connected between respective D- and D+ for noise filtering.

S02391

Vendor:SMKPackage Cooled:SMD-36

FEATURES High-Performance Member of Pin-Compatible TxDAC Product Family Excellent Spurious-Free Dynamic Range and Noise Performance Twos Complement or Straight Binary Data Format Differential Current Outputs: 2 mA to 20 mA Power Dissipation: 135 mW @ 3.3 V Power-Down Mode: 15 mW @ 3.3 V On-Chip 1.20 V Reference CMOS-Compatible Digital Interface Package: 32-Lead Leadframe Chip Scale Package (LFCS...

S02405D

Vendor:HITPackage Cooled:SOP5.2mmD/C:1996

Supports automatic programming, Embeded Algorithm TM*4 Write/Erase/Erase-Suspend/Erase-Resume commands A flag indicating completion of the algorithm Number of erase cycles : 10,000 times Data retention time : 10 years Boot block configuration Erase can be performed on each block Block protection by externally programmed voltage

S02405D

Vendor:HITPackage Cooled:SOP5.2mmD/C:1996

Supports automatic programming, Embeded Algorithm TM*4 Write/Erase/Erase-Suspend/Erase-Resume commands A flag indicating completion of the algorithm Number of erase cycles : 10,000 times Data retention time : 10 years Boot block configuration Erase can be performed on each block Block protection by externally programmed voltage

S02424C

Vendor:SMK

• Dual voltage monitoring V2Mon operates independent of VCC • Watchdog timer with selectable timeout intervals • Low VCC detection and reset assertion Four standard reset threshold voltages User programmable VTRIP threshold Reset signal valid to VCC=1V • Low power CMOS 20µA max standby current, watchdog on 1µA standby current, watchdog OFF • 64Kbits of EE...

S02424D

Vendor:SMKPackage Cooled:SOP20D/C:N/A

and D. MONO IN is the timing input for the on-chip monostable oscillator. Grounding of the MONO IN terminal through a resistor of 10KΩ or higher, disa- bles the one-shot circuit and connects the decoder directly to the DECODE OUT terminal. A resistor to VDD and a capacitor to ground from the MONO IN terminal enables the one-shot circuit and controls its pulse width. A fast test mode is enabled ...

S02424D

Vendor:SMKPackage Cooled:SOP20D/C:N/A

and D. MONO IN is the timing input for the on-chip monostable oscillator. Grounding of the MONO IN terminal through a resistor of 10KΩ or higher, disa- bles the one-shot circuit and connects the decoder directly to the DECODE OUT terminal. A resistor to VDD and a capacitor to ground from the MONO IN terminal enables the one-shot circuit and controls its pulse width. A fast test mode is enabled ...

S02458D

Vendor:SMKPackage Cooled:SOP-5.2-20PD/C:6+

Thermistor : Temperature dependant resistor. Basically there are 2 types. The types that increase their resistance with rising temperature are PTC ( positive thermal coefficient ) types. The ones that decrease their resistance with rising temperature we call NTC ( negative thermal coefficient ) types.

S0253B

Vendor:SIEMENSPackage Cooled:DIPD/C:03+

• Universal Asynchronous Receiver/Transmitter (UART) Module Flexible baud rate generator Based on MC68681 Dual Universal Asynchronous Receiver/Transmitter (DUART) programming model 5 Mbits/s maximum transfer rate at 16.67-MHz system clock Automatic interrupt generation with programmable level Modem control signals available (CTS,RTS)

S02570D

Vendor:SMKPackage Cooled:SOP-5.2-20PD/C:SOP-5.2-20P

Low-latency option Skew alignment support for multiple bytes of offset Synchronous LVTTL parallel input interface Synchronous LVTTL parallel output interface 200-to-1500 MBaud serial signaling rate Internal PLLs with no external PLL components Dual differential PECL-compatible serial inputs per channel Dual differential PECL-compatible serial outputs per channel Source matched for 50Ω transmission...

S02617D

Vendor:SMKPackage Cooled:02+D/C:SOP-5.2-20P

Dual outputs, each with independent over-current protection circuitry and indicator Supports standby mode in PCs so that a peripheral can ramp down safely to a current <100mA Up to 1.2A (VCC) / 200mA (VSBY) continuous current on each output Over-current limits at 1.2A / 200mA respectively 10msec min fault blanking delay on OC# outputs prevents false overcurrent alarms Prevents backdrive current when ho...

S02645D

Vendor:HITPackage Cooled:SOP5.2mmD/C:1997

/RCS0 -->/CS0 : SDRAMs D0-D17 RBA0-RBA1--> : BA0-BA1:SDRAMs D0-D17 RA0 -R A11 -->A0 - A11 : SDRAMs D0 - D17 /RRAS --> /RAS : SDRAMs D0 - D17 /RCAS --> /CAS : SDRAMs D0 - D17 RCKE0 --> CKE : SDRAMs D0 - D17 /RWE --> /WE : SDRAMs D0 - D17

S02648250055K

S02770T-EL

Vendor:SMKPackage Cooled:SOPD/C:03+

Any offset and/or gain calibration procedures should not be implemented until devices are fully warmed up. To avoid interaction, offset must be adjusted before gain. The ranges of adjustment for the circuit in Figure 2 are guaranteed to compensate for the ADS-944's initial accuracy errors and may not be able to compensate for additional system errors.

S028GT-8.4MM

Vendor:PRACTICALPackage Cooled:SMDD/C:06+

• Gain calibration, to compensate for gain errors (in Kv and Ki) introduced by normal variations in the values of different resistors, CT ratios and so on. • Phase calibration, to compensate for extraneous phase shifts introduced by the current measurement technique (from the CT, from the small but unwelcome inductance generated by a shunt and so on).

S028GTR-7.6MM

Package Cooled:92D/C:1000

Reset Command Reset Command is the command to safely abort the erase or program sequences. Following erase or program command in first write cycle, the operation is aborted safely by writing the two consecutive Reset Commands (FFH). Then the device enters read mode without altering memory contents.

S028XL

Input voltage range: 2.7V to 6.0V Dual, independent 150mA LDOs Error flags indicate fault condition Stable with ceramic output capacitor Ultra-low dropout: 135mV @ 150mA High output accuracy: 1.0% initial accuracy 2.0% over temperature Low quiescent current: 90µA each LDO Tight load and line regulation Thermal shutdown and current limit protection Zero off-mode current TTL logic-contro...

S028XL

Input voltage range: 2.7V to 6.0V Dual, independent 150mA LDOs Error flags indicate fault condition Stable with ceramic output capacitor Ultra-low dropout: 135mV @ 150mA High output accuracy: 1.0% initial accuracy 2.0% over temperature Low quiescent current: 90µA each LDO Tight load and line regulation Thermal shutdown and current limit protection Zero off-mode current TTL logic-contro...

S0290B1

Vendor:SIEMENSD/C:00+

S0290BI

The ispLSI 8000V Family of Register-Intensive, 3.3V SuperBIG In-System Programmable Logic Devices is based on Big Fast Megablocks of 120 registered macro- cells and a Global Routing Plane (GRP) structure interconnecting the Big Fast Megablocks. Each Big Fast Megablock contains 120 registered macrocells arranged in six groups of 20, a group of 20 being referred to as a Generic Logic Block, or GLB. Wit...

S0290BS1

Vendor:SIEMENSPackage Cooled:DIP/16

ICC reduced to 40 0 mA Ideal buffer for MOS microprocessor or memory Eight edge-triggered D flip-flops Buffered common clock Buffered asynchronous master reset TTL input and output level compatible TTL levels accept CMOS levels IOL e 48 mA (Com) 32 mA (Mil) NSC 54 74FCT273 is pin and functionally equivalent to IDT 54 74FCT273 Military product compliant to MIL-STD-883 and Standard Military Drawing 5962...

S02916F

Vendor:SMKPackage Cooled:SOP-5.2-20PD/C:6+

During the Acknowledge clock pulse, the master (up) put a resistive HIGH level on the SDA line. The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during the Acknowledge clock pulse so that the SDA line is in a stable LOW state during this clock pulse. Please refer to the diagram below.

S02916F

Vendor:SMKPackage Cooled:SOP-5.2-20PD/C:6+

During the Acknowledge clock pulse, the master (up) put a resistive HIGH level on the SDA line. The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during the Acknowledge clock pulse so that the SDA line is in a stable LOW state during this clock pulse. Please refer to the diagram below.

S02970F

Vendor:SMKPackage Cooled:SOP-5.2-20PD/C:6+

Device erasure occurs by executing the erase com- mand sequence. This initiates the Embedded Erase algorithman internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

S02970F

Vendor:SMKPackage Cooled:SOP-5.2-20PD/C:6+

Device erasure occurs by executing the erase com- mand sequence. This initiates the Embedded Erase algorithman internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

S02AL

The SY88713V operates from a single +3.3V or +5V power supply, over temperatures ranging from C40C to +85C. With its wide bandwidth and high gain, signals with data rates up to 622Mbps and as small as 5mVp-p can be amplified to drive devices with PECL inputs.

S0301L

S03033F

Vendor:SMKD/C:05+

In many applications the microcontroller provides an effective approach for the temperature compensation of the sensitivity and the zero g offset. Specific code set, reference designs, and applications notes are available from the factory. The following parameters must be considered in a digital interface:

S0303LS2

S0304F1

SET (Pin 3): Frequency-Setting Resistor Input. The value of the resistor connected between this pin and V+ deter- mines the oscillator frequency. The voltage on this pin is held by the LTC6900 to approximately 1.1V below the V+ voltage. For best performance, use a precision metal film resistor with a value between 10kΩ and 2MΩ and limit the capacitance on this pin to less than 10pF.

S0306FS21

S0306FS31

S0308(5828)

Vendor:MOTPackage Cooled:SOIC-8D/C:98

The bq2060 supports the smart bat- tery data (SBData) commands and charge-control functions. It communi- cates data using the system manage- ment bus (SMBus) 2-wire protocol or the Benchmarq 1-wire HDQ16 proto- col. The data available include the batterys remaining capacity, temper- ature, voltage, current, and remain- ing run-time predictions. The bq2060

S0308LS2

S03092F

Vendor:SMKPackage Cooled:SOP-5.2-20PD/C:6+

HVQFN package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be inco...

S0310F1

Valid combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

S0310FS31

S0310LS2

S0310LS3

S03134F

Vendor:SMK

Read cycles are initiated with ADSP(regardless of WEx and ADSC) using the new external address clocked into the on-chip address register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper- ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car- ried to the Dat...

S03134F-EL

Vendor:2233Package Cooled:HITD/C:SOP

The Default Disable command resets all conditions to the power on default states. The HT82K628A will re- spond with ACK, clears its output buffer, sets the default key types (scan code set 3 operation only) and typematic rate/delay, and clears the last typematic key. The HT82K628A then stops scanning and awaits further command.

S0315L

S0316R

The parallel I/O interface may be configured for numerous forms of clocking to provide the highest flexibility in system architecture. In additional to clocking the transmit path inter- faces from one or multiple sources, the receive interface may be configured to present data relative to a recovered clock (output) or to a local reference clock (input).

S03178F

Vendor:SMK

DESCRIPTION Frequency Range Small Signal Gain Small Signal Gain Flatness @5.7 ~ 5.9 GHz Small Signal Gain Flatness @5 ~ 6 GHz Output Power at 1 dB Gain Compression Output Power at 3 dB Gain Compression Third Order Intercept Point Input VSWR Supply Voltage Gate Voltage Current Supply Without RF Current Supply @ Pout=P-1 dB Power Added Efficiency

S031G

Vendor:IORPackage Cooled:SMD-8D/C:04+

S03200VCL-266

Vendor:NSCPackage Cooled:06+D/C:800

Hynix HYMD232M646(L)6-K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

S03200VCL-266

Vendor:NSCPackage Cooled:06+D/C:800

Hynix HYMD232M646(L)6-K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

S03246F

Vendor:910Package Cooled:2005D/C:SOP

Notes: 1. The luminous intensity, I v, is measured at the peak of the spatial radiation pattern which may not be aligned with the mechanical axis of the lamp package. 2. The dominant wavelength, ëd, is derived from the CIE Chromatically Diagram and represents the perceived color of the device. 3. 1/2 is the off-axis angle where the luminous intensity is 1/2 the peak intensity.

S0325R

S03292F

Vendor:SMKPackage Cooled:SOP-5.2-16PD/C:6+

Normally, capacitor values on the order of several hundred microfarads are used on the output of the regulators to ensure good transient response with heavy load current changes. Output capacitance can increase without limit and larger values of output capacitance further improve the

S03292F

Vendor:SMKPackage Cooled:SOP-5.2-16PD/C:6+

Normally, capacitor values on the order of several hundred microfarads are used on the output of the regulators to ensure good transient response with heavy load current changes. Output capacitance can increase without limit and larger values of output capacitance further improve the

S03337F

Vendor:SMK

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Currents are...

S0348103F48-48V

S034F06SLD

S03-5065-00

S035-20KONY737

S0368HC49U

S03B1960N2

Vendor:MOTOROLAD/C:06+

S03B1960N2

Vendor:MOTOROLAD/C:06+

S03B888N1

Vendor:N/APackage Cooled:N/AD/C:N/A

S03B888N2

Vendor:APackage Cooled:2005D/C:07+

This MOSFET is an enhancement-mode silicon-gate power field-effect transistor of the vertical DMOS (VDMOS) struc- ture. It is specially designed and processed to be radiation tolerant. The MOSFET is well suited for applications exposed to radiation environments such as switching regula- tion, switching converters, motor drives, relay drivers and drivers for high-power bipolar switching transistor...

S03B888N3

Vendor:ANARENPackage Cooled:SMDD/C:05+

standard for high-speed system bus running at half the CPU clock High-bandwidth memory controller for SDRAM, SRAM, and EPROM SDRAM support for standard SDRAMs up to 256 MBytes with auto refresh, up to 4 banks non-interleaved Support for PC100 type memories with up to two chip enables EPROM controller for boot code 8-bit, 16-bit, and 32-bit device width support

S040-05U24

Vendor:YCLPackage Cooled:0209+

S0402NH

Vendor:sgsPackage Cooled:sgsD/C:dc93

Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will acti- vate their respective outputs by loading a logic high.

S0402NH

Vendor:sgsPackage Cooled:sgsD/C:dc93

Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will acti- vate their respective outputs by loading a logic high.

S040601A

D/C:08+/09+

MTP805 includes all 8051 functions with the following exceptions: 1.1 PSEN, ALE, #RD and #WR pins are disabled. The external RAM access is restricted to XFRs within the MTP805. 1.2 Port0, port3.2, port3.3, port3.6 and port3.7 are not general-purpose I/O ports. They are dedicated to special application. 1.3 #INT0 and #INT1 input pin is not provided, it is connected to special interrupt sources. 1.4 UART a...

S0406MH

Peripheral Features Two Full-Duplex Serial Ports Programmable Watchdog Timer 13 Interrupt Sources (Six External) Five Levels of Interrupt Priority Power-Fail Reset Early Warning Power-Fail Interrupt Electromagnetic Interference (EMI) Reduction

S0407DH

S041C992

• NPT IGBT - low saturation voltage with positive temperature coefficient - low switching losses - wide safe operating area • HiPerFREDTM diode - fast reverse recovery - low operating forward voltage - low leakage current • ISOPLUS i4-PACTM package - isolated back surface - low coupling capacity between pins and heatsink - enlarged creepage towards heatsink - application...

S041E

Vendor:siePackage Cooled:sieD/C:dc85

The Am29F010 is a 1 Mbit, 5.0 Volt-only Flash memory organized as 131,072 bytes. The Am29F010 is offered in 32-pin PLCC, TSOP, and PDIP packages. The byte- wide data appears on DQ0-DQ7. The device is de- signed to be programmed in-system with the standard system 5.0 Volt VCC supply. A 12.0 volt VPP is not re- quired for program or erase operations. The device can also be programmed or erased in stand...

S0491HC49U

The S0491HC49U offers superior dynamic performance with a 130MHz small-signal bandwidth, 350V/µs slew rate and 4.6ns rise/fall times (2Vpp). The combination of low quiescent power, high output drive current, and high-speed performance make the S0491HC49U a great choice for many portable and battery- powered personal communication and computing systems.

S0498

The National Semiconductor® PC87431x family of mini- Baseboard Management Controllers (mBMC) is a light ver- sion of the IPMI v1.5 BMC. It is targeted for a wide range of remote-controlled platforms such as servers, workstations, hubs and printers.

S04FWM02N(7123-1640)

Vendor:0Package Cooled:07＋D/C:1034

S04G4

SUPPLY VOLTAGE C VCC = 3V to 3.6V for Program, Erase and Read Operations C VPP = 12V for Fast Program and Fast Erase (optional) TWO INTERFACES C Firmware Hub (FWH) Interface for embedded operation with PC Chipsets C Address/Address Multiplexed (A/A Mux) Interface for programming equipment compatibility FIRMWARE HUB (FWH) HARDWARE INTERFACE MODE C 5 Signal Communication Interface supporti...

S050-05U05

Vendor:YCLPackage Cooled:9536+

S0501L

S0503LS1

The MB3836 is a lithium-ion battery protection IC for three cells series lithium-ion battery pack in a notebook PCs. This IC supports charging at 12.6 V and detects an over-charge, over-discharge, and over-current to control charging and discharging.

S0506F43

Vendor:108Package Cooled:TECCORD/C:N/A

where VTH is the threshold voltage at which the com- parator switches its output from high to low as VIN rises above the trip point. VTL is the threshold volt- age at which the comparator switches its output from low to high as VIN drops below the trip point.

S0506FS21

Vendor:TECCORD/C:05+

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.

S0506FS22

Vendor:488Package Cooled:TECCORD/C:N/A

The IC must be equipped with external RC circuitry to limit the voltage in the event of power surges (see Figure 3 on page 3). This prevents the circuit from being damaged or destroyed, and provides a buffer in case of power fluctuations at VBatt. The RxD compar- ator is powered via pin VS, producing its reference voltage of 1/2 V S, while all other blocks are supplied via VCC.

S0506L

Vendor:LF(TEC)Package Cooled:TO-220D/C:07+

In order to increase the adjustment range of VCO3 with fixed external tank elements and/or for band switching, especially for US frequencies, VCO3 has programmable capacitors inside. These capacitors can be added by serial bus (FA3 [4:0]) between LO1 and LO2. There are 31 steps available, every step adding a capacitor of 0.5pF.

S0506L

Vendor:LF(TEC)D/C:07+

In order to increase the adjustment range of VCO3 with fixed external tank elements and/or for band switching, especially for US frequencies, VCO3 has programmable capacitors inside. These capacitors can be added by serial bus (FA3 [4:0]) between LO1 and LO2. There are 31 steps available, every step adding a capacitor of 0.5pF.

S0506LS2

Vendor:2500D/C:TO-220

INPUT LO: Direct output mode where CE/LD, HBEN, MBEN and LBEN act as inputs directly controlling byte outputs. If pulsed HI causes immediate entry into handshake mode (see Figure 13). If HI, enables CE/LD, HBEN, MBEN and LBEN as outputs. Handshake mode will be entered and data output as in Figures 11 and 12 at conversion completion.

S0506LS2

Vendor:2500Package Cooled:TECCORD/C:TO-220

INPUT LO: Direct output mode where CE/LD, HBEN, MBEN and LBEN act as inputs directly controlling byte outputs. If pulsed HI causes immediate entry into handshake mode (see Figure 13). If HI, enables CE/LD, HBEN, MBEN and LBEN as outputs. Handshake mode will be entered and data output as in Figures 11 and 12 at conversion completion.

S0506LS3

Vendor:1500Package Cooled:TECCORD/C:TO-220

The minimum recommended value for CT is 1000 pF. This value ensures that the blanking time is sufficient to avoid false trips of the comparator under normal operating conditions. For optimal regulation of the load current, the above value for CT is recommended and the value of RT can be sized to determine tOFF. For more information regarding load current regulation, see below.

S0508F1

Vendor:TECCORD/C:05+

Common Flash Memory Interface (CFI) The SST39VF160Q/VF160 also contain the CFI informa- tion to describe the characteristics of the device. In order to enter the CFI query mode, the system must write 3 byte sequence, same as product ID entry command with 98H (CFI query command) to address 5555H in the last byte sequence. Once the device enters the CFI query mode, the system can read CFI data at the ad...

S0508F2

Vendor:173Package Cooled:TECCORD/C:N/A

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. (2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate ...

S0508FS21

Vendor:TECCORD/C:05+

The gate drive ready pin (GDR) is used to indicate when the gate drive output (GATE) is greater than 90% of its final value. This can be useful in applications that require knowledge of the state of the gate drive for initialization purposes or as fault detection should something be load- ing the gate drive down.

S0508FS31

Vendor:TECCORD/C:05+

Operating voltage: fSYS=4MHz: 3.3V~5.5V fSYS=8MHz: 4.5V~5.5V 13 bidirectional I/O lines An interrupt input shared with an I/O line 8-bit programmable timer/event counter with overflow interrupt and 8-stage prescaler On-chip crystal and RC oscillator Watchdog timer 1024´14 program memory PROM 64´8 data memory RAM Buzzer driving pair and PFD supported

S0508LS2

Vendor:2500D/C:TO-220

D/A Converter Sampling Clock For Y Signal (PCK) Chroma Subcarrier (NTSC : 3.7595MHz, PAL : 4.4336MHz) Burst Flag Pulse Video Composite SYNC signal Line Atternate Pulse For PAL D/A Converter Sampling Clock for C Signal (4Fsc) Y Video Signal Output

S0508LS2

Vendor:2500D/C:TO-220

D/A Converter Sampling Clock For Y Signal (PCK) Chroma Subcarrier (NTSC : 3.7595MHz, PAL : 4.4336MHz) Burst Flag Pulse Video Composite SYNC signal Line Atternate Pulse For PAL D/A Converter Sampling Clock for C Signal (4Fsc) Y Video Signal Output

S0508LS3

Vendor:3500

The HYM75V32M636(L)T6 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 256M bytes memory. The HYM75V32M636(L)T6 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.

S0508LS3

Vendor:3500

The HYM75V32M636(L)T6 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 256M bytes memory. The HYM75V32M636(L)T6 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.

S0508R

Vendor:120Package Cooled:TECCORD/C:N/A

High-speed ADC Family Companion Chip Selectable 1:2 or 1:4 DMUX Ratio Power Consumption: 2.6W LVDS Compatible Differential Data and Clock Inputs (100Ω Terminated) LVDS Compatible Differential Data and Data Ready Outputs Staggered or Simultaneous Data Outputs C 11th Bit = Ports A, B, C and D Clock in Staggered Mode Selectable Active Edge for Input and Output Clocks: C Only Rising: CLK and DR Mode C...

S0510F1

Vendor:TECCORD/C:05+

The S0510F1 Ethernet Transceiver is a low power BiCMOS coax line transmitter/receiver. The device includes analog transmit and receive buffers, a 10 MHz on-board oscillator, timing logic for jabber and heartbeat functions, output drivers and bandgap reference, in addition to a current reference and collision detector.