STM M25P40-VMN6TP

STM M25P64-VMF6P

STM M29W320ET70N6E

STM M34C02-RDW6TP

STM M48T86MH1E

STM M93C46-WBN6P

STM M93C46-WMN6TP

STM MAT5813-8W001

STM MC3403DT

STM MC34063ECN

STM NE556N

STM P6KE300A

STM P6KE440A

STM ST13005

STM ST2042BDR

STM ST3232EBTR

STM ST7FLCD-EMU3

STM STA314

STM STA333ML

STM STA50513TR

STM STA515W

STM STB12NK80Z-S

STM STD40NF3LLT4

STM STF2HNK60Z

STM STF3NK80Z

STM STGF10NB60SD

STM STLV3243EBJR

STM STP10NK60Z

STM STP10NK70ZFP

STM STP10NK80ZFP

STM STP3NK60ZFP

STM STP4NK60ZFP

STM STP9NK70ZFP

STM STPR1620CT

STM STPS10150CT

STM STPS1045B-TR

STM STPS30150CT

STM STPS3045CT

STM STPS30H100CT

STM STPS30L45CT

STM STPS30L60CW

STM STPS3150U

STM STPS40H100CW

STM STPS40L45CT

STM STPS6045CW

STM STR91X-SK/IAR

STM STSR30D-TR

STM STTH1002CT

STM STTH8R06FP

STM STV0362

STM STV0672

STM STW12NK80Z

STM STW20NM60

STM STW21NM50N

STM STW45NM50

STM STW7NK90Z

STM TDA2822D

STM TDA7231A

STM TDA9105

STM TIP102

STM TIP117

STM TIP32C

STM TIP35C

STM TL072CN

STM TL074CN

STM TL082CDT

STM TS431AILT

STM TS482IST

STM TS613IDT

STM TS912IDT

STM TSM103WAIDT

STM TSM104WIDT

STM TSM111CN

STM TYN612MRG

STM UC3842BN

STM ULN2003D1013TR

STM ULN2803A

STM VIPER22ADIP-E

STM Z0405MF 1AA2

STM Z0409MF 1AA2

STM/4641

Vendor:?Package Cooled:LCC中D/C:——

STM1001MWX6F

Vendor:STPackage Cooled:3,000D/C:07+

STM1001RWX6F

Vendor:stPackage Cooled:07+D/C:6000

Low-power, high-speed CMOS EPROM technology Fully static design Wide-operating voltage range (2.7V to 6.0V) Commercial and Industrial Temperature Range Low power dissipation (typical) - < 3 mA @5V, 4 MHz operating mode - < 300 µA @3V (Sleep mode: clocks stopped with analog circuits active) - < 5 µA @3V (Hibernate mode: clocks stopped, analog inactive, and WDT disabled)

STM1001RWX6F

Vendor:stPackage Cooled:07+D/C:6000

Low-power, high-speed CMOS EPROM technology Fully static design Wide-operating voltage range (2.7V to 6.0V) Commercial and Industrial Temperature Range Low power dissipation (typical) - < 3 mA @5V, 4 MHz operating mode - < 300 µA @3V (Sleep mode: clocks stopped with analog circuits active) - < 5 µA @3V (Hibernate mode: clocks stopped, analog inactive, and WDT disabled)

STM1001TWX6F

Vendor:STPackage Cooled:SOT23-3D/C:07+

During a READ operation (mode 2 error detection) the data and check bits that were stored in memory now possibly in error are input through the data and check bit I O ports New check bits are internally generated from the data word These new check bits are then compared by an EXCLU- SIVE NOR operation with the original check bits that were stored in memory The EXCLUSIVE NOR of the original check bits ...

STM101C

Package Cooled:SOP

Differential gain: 0.5% typ Differential phase: 0.5 typ Programmable video controls: Peak-white/hue/brightness/saturation/contrast Integrated on-chip video timing generator Free run mode (generates stable video ouput with no I/P) VBI decode support for Close captioning, WSS, CGMS, EDTV, Gemstar® 1/2 Power-down mode 2-wire serial MPU interface (I2C® compatible) 3.3 V analog, 1.8 V digital co...

STM104IW

Vendor:SOP16Package Cooled:675D/C:ST

A built-in over-voltage protection (OVP) forces the lower MOSFET on to prevent the output from exceeding a set voltage. The PWM controller's overcurrent circuitry moni- tors the converter load by sensing the voltage drop across the lower MOSFET. The overcurrent threshold is set by an exter- nal resistor. If precision overcurrent protection is required, an optional external current-sense resistor may be...

STM1061N22WX6F

Vendor:STMD/C:07+

The SY89833L is a 3.3V, high-speed 2GHz differential Low Voltage Differential Swing (LVDS) 1:4 fanout buffer optimized for ultra-low skew applications. Within device skew is guaranteed to be less than 20ps over supply voltage and temperature.

STM1061N23WX6F

Vendor:STPackage Cooled:SOT23-3D/C:07+

Terminator technology supports on-chip differential termination for source-synchronous LVDS signalling. The differential termination resistors are adjacent to the differential input buffers on the device. This placement eliminates stub effects, improving the signal integrity of the serial link. Using on-chip differential termination resistors also saves board space. Figure 5 shows the differential termina...

STM1061N29WX6F

Vendor:STPackage Cooled:sgsD/C:07+

In the DDR-II RDIMM application, RST# is specified to be completely asynchronous with respect to CK and CK#. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active qui...

STM1240

Vendor:N/APackage Cooled:02+D/C:08+09+

Philips Semiconductors 51MX (Memory eXtension) core is an accelerated 80C51 architecture that executes instructions at twice the rate of standard 80C51 devices. The linear address range of the 51MX has been expanded to support up to 8 Mbytes of program memory and 8Mbytes of data memory. It retains full program code compatibility to enable design engineers to re-use 80C51 development tools, eliminating the nee...

STM1241

Package Cooled:MODULE

Preformed Leads (SOD64 Packages) Some types of automatic insertion machines have problems in bending the relatively thick leads of SOD64 Sinterglass Diodes. To overcome this, our diodes can be ordered with preformed leads as fol- lows. Preformed Sinterglass Diodes are shipped in bulk.

STM1241

Package Cooled:MODULE

Preformed Leads (SOD64 Packages) Some types of automatic insertion machines have problems in bending the relatively thick leads of SOD64 Sinterglass Diodes. To overcome this, our diodes can be ordered with preformed leads as fol- lows. Preformed Sinterglass Diodes are shipped in bulk.

STM13FW500

The DS1809 is available in standard 10 kΩ , 50 kΩ , and 100 kΩ resistor versions. The DS1809 is provided as an industrial temperature grade part only. Available packaging for the DS1809 include an 8- lead (300-mil) DIP an 8-lead (150-mil) SOIC, and an 8-lead (118-mil) µSOP.

STM1403ASOQ6F

These devices are ideal for cost-sensitive applications requiring significant control processing for file management, connectivity, data buffering, and user interface, as well as signal processing in a variety of key markets such as security, imaging, networking, gaming, and medical. This leading package of integration and high performance allows fast time to market through easy code reuse and extensive ...

STM1403ATOQ6F

Address Setup Time to Falling Edge of URD Address Hold Time from Rising Edge of URD URD Pulse Width URD Falling Edge to Output Data Valid Rising Edge of URD to Output Data Invalid RDRDY Delay from Rising Edge of URD UWR Pulse Width Input Data Valid before Rising Edge of UWR Input Data Hold after Rising Edge of UWR WRRDY Delay from Rising Edge of UWR

STM1403CSNQ6F

Three status indicators on the keyboard-Num Lock, Caps Lock, and Scroll Lock-are accessible by the host. The HT82K628A activates or deactivates these indica- tors when it receives a valid command-code sequence from the system. The command sequence begins with the command byte (hex ED). The HT82K628A responds to the command byte with ACK, discontinues scanning, assignments for this option byte are as follow:

STM1403CSOQ6F

Wait or Transfer Acknowledge. When configured as wait, this signal is asserted low during a memory and peripheral device bus transaction to extend the bus cycle. When configured as transfer acknowledge, this signal is asserted low dur- ing a memory and peripheral device bus transaction to signal the completion of the transaction.

STM1404ATOHQ6F

CDMA balanced input pin. This pin is internally DC-biased and should be DC-blocked if connected to a device with a DC level other than VCC present. A DC to connection to VCC is acceptable. For single-ended input operation, one pin is used as an input and the other CDMA input is AC-coupled to ground. The balanced input impedance is 1kΩ, while the single-ended input impedance is 500Ω.

STM1404CSNIQ6F

When READ is LOW, data can be read from the RAM array sequentially, independent of WRITE. In order for READ to be active, EF must be HIGH. When the FIFO is empty (EF-LOW), the internal READ operation is blocked. The three-state output buffer is controlled by the read signal and the external output control (OE).