STRF6234

Vendor:SKPackage Cooled:TO3P-5D/C:03+

CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5207 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid perfo...

STR-F6238

Vendor:SKPackage Cooled:TO-5D/C:08+

HITAG(1) is the name of one of the universal and powerful product lines of our 125 kHz family. The contactless proximity read and write system that works with passive transponders is suitable for various applications. Inductive coupling helps you to achieve reading ranges up to 200 mm and the use of cryptography guarantees highest data security.

STRF6254

D/C:08+/09+

Note 4: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. The data book specifica- tions should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading vari- ables. Fairchild does not recommend operation outside databook specifica- tions.

STRF6267 T

STRF6268

Vendor:380

Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of Electrical Characteristics specifies conditions of device operation. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed,

STR-F6268S

STRF6354

Vendor:SanKen

Note 6: Care must be taken to ensure TSTC and THTC are met so input data are sampling correctly. This SSCG parameter only shows the performance of tracking Spread Spectrum Clock applied to TxCLK IN pin, and reflects the result on TxCLKOUT+ and TxCLKOUT− pins.

STRF6424

Vendor:SanKenPackage Cooled:ZIP

An extra 64 bytes of MRAM are available to the user for Device ID. By raising A9 to VCC + 2.0V and by using address locations 00(Hex) to 3F(Hex) on address pins A7, A6, A14, A13, A12 and A0 (MSB to LSB) respectively, the additional Bytes may be accessed in the same manner as the regular memory array, with 140 ns access time. Dropping A9 from input high (VCC + 2.0V) to < VCC returns the device to normal o...

STRF6428

Vendor:120

C1=12pf, ATC "B" (100MIL) C2=6.2pf, ATC "B" (100MIL) C3=5.6pf, Dielectric Labs C4=20pf, ATC "B" (100MIL) C5,C6=.3-3.5pf, Johanson Piston Trimmer C7,C8=5.2pf, ATC "B" (100MIL) C9,C10=180pf, ATC "B" (100MIL) C11,C12,C13,C14=470pf, ATC "B" (100MIL) C15,C16=50mf, 50 WVDC Electrolytic

STR-F6454R(LF1351)

Load strobe input for a 12-bit address/data: A high level on the LD pin latches a 4-bit address (upper 4 bits: D11 to D8) of the internal 12-bit shift register into the internal address decoder, and writes 8-bit data (lower 8 bits: D7 to D0) of the shift register into an internal data latch selected by the latched address.

STRF6456

Vendor:STRPackage Cooled:DIPD/C:2000

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or inf...

STRF6467

Vendor:SANKENPackage Cooled:ZIP

3V TTL/CMOS-compatible Digital Output pins that provide the conversion results of the I and Q inputs. I0 and Q0 are the LSBs, I9 and Q9 are the MSBs. Valid data is present just after the rising edge of the CLK input in the Parallel mode. In the multiplex mode, I-channel data is valid on I0 through I9 when the I/Q output is high and the Q-channel data is valid on I0 through I9 when the I/Q output is low.

STRF6503

Vendor:SanKen

• High performance 1:10 clock driver for general purpose applications • Operates up to 200MHz at VDD = 3.3V • Pin-to-pin skew < 50ps • VDD range: 2.3V to 3.6V • Output enable glitch suppression • Distributes one clock input to two banks of five outputs • 25Ω on-chip series dampening resistorsΩ • Available in TSSOP and VFQFPN packages

STRF6503

Vendor:SanKen

• High performance 1:10 clock driver for general purpose applications • Operates up to 200MHz at VDD = 3.3V • Pin-to-pin skew < 50ps • VDD range: 2.3V to 3.6V • Output enable glitch suppression • Distributes one clock input to two banks of five outputs • 25Ω on-chip series dampening resistorsΩ • Available in TSSOP and VFQFPN packages

STRF6512

Vendor:SANKEN

data, address and control registers. There are no registers in the data output path (flow-through architecture). Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V67703/7903 can provide four cycles of data for a single addre...

STRF6512

Vendor:SANKEN

data, address and control registers. There are no registers in the data output path (flow-through architecture). Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V67703/7903 can provide four cycles of data for a single addre...

STRF6513

Vendor:SKPackage Cooled:ZIP5D/C:99

POWER DISSIPATION Power dissipation is a major concern when designing a suc- cessful amplifier, whether the amplifier is bridged or single- ended. A direct consequence of the increased power deliv- ered to the load by a bridge amplifier is an increase in internal power dissipation. Equation 1 states the maximum power dissipation point for a bridge amplifier operating at a given supply voltage and driv...

STRF6514

Vendor:SKPackage Cooled:ZIP5D/C:99

Integrated Downconverter Integrated Dual Synthesizer 256 QAM Compatibility Single +5 V Power Supply Operation Low Power Consumption: <0.6 W Low Noise Figure: 8 dB High Conversion Gain: 10 dB Low Distortion: -53 dBc Two-Wire Interface Small Size -40 C to +85 C

STRF6514

Vendor:SKPackage Cooled:ZIPD/C:99

Integrated Downconverter Integrated Dual Synthesizer 256 QAM Compatibility Single +5 V Power Supply Operation Low Power Consumption: <0.6 W Low Noise Figure: 8 dB High Conversion Gain: 10 dB Low Distortion: -53 dBc Two-Wire Interface Small Size -40 C to +85 C

STR-F6514

Vendor:SanKenPackage Cooled:TO220D/C:1998

The PWM pin controls the switching of the external MOSFETs. The driver logic operates in a noninverting configuration. The PWM input stage should be driven by a signal with fast transition times, like those provided by a PWM controller or logic gate, (<200 ns). The PWM input functions as a logic input and is not intended for applications where a slow changing input voltage is used to generate a swit...

STR-F6514

Vendor:SanKenPackage Cooled:TO220D/C:1998

The PWM pin controls the switching of the external MOSFETs. The driver logic operates in a noninverting configuration. The PWM input stage should be driven by a signal with fast transition times, like those provided by a PWM controller or logic gate, (<200 ns). The PWM input functions as a logic input and is not intended for applications where a slow changing input voltage is used to generate a swit...

STRF6515

Vendor:SanKenPackage Cooled:ZIP

2W per Channel Output Power Into 3-Ω Load Internal Gain Control, Which Eliminates External Gain-Setting Components Input MUX Select Terminal PC-Beep Input Depop Circuitry Integrated Two Input Modes Allowable with Single-Ended or Fully Differential Input Low Supply Current and Shutdown Current Thermal Shutdown Protection TSSOP-24 with Thermal Pad

STRF6515

Vendor:SanKenPackage Cooled:ZIP

2W per Channel Output Power Into 3-Ω Load Internal Gain Control, Which Eliminates External Gain-Setting Components Input MUX Select Terminal PC-Beep Input Depop Circuitry Integrated Two Input Modes Allowable with Single-Ended or Fully Differential Input Low Supply Current and Shutdown Current Thermal Shutdown Protection TSSOP-24 with Thermal Pad

STRF6516

Vendor:SKPackage Cooled:ZIP5D/C:99

The DDR SIO operation is possible by supporting DDR read and write operations through separate data output and input ports. Memory bandwidth is higher than DDR sram without separate input output as separate read and write ports eliminate bus turn around cycle.

STRF6516

Vendor:SKD/C:99

The DDR SIO operation is possible by supporting DDR read and write operations through separate data output and input ports. Memory bandwidth is higher than DDR sram without separate input output as separate read and write ports eliminate bus turn around cycle.

STRF6517

Vendor:SKPackage Cooled:ZIPD/C:97+

Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, JA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX − TA)/JA or the number given in the Absolute Maximum Ratings, whichever is lower. In most cases, the maximum derated power dissipation will be reached only during fault conditions. For these...

STRF6519

Vendor:SKPackage Cooled:ZIP5D/C:99

SERIAL INTERFACE TIMING The IDT72V8985 master clock (C4i) is 4.096 MHz signal allowing serial data link configuration at 2.048 Mb/s to be implemented. The IDT72V8985 can automatically detect the presence of an input frame pulse, identify the type of backplane present on the serial interface, and format the synchronization pulse according to ST-BUS® or GCI interface specifications (active HIGH in GCI or...

STRF6519

Vendor:20Package Cooled:ZIP5D/C:99

SERIAL INTERFACE TIMING The IDT72V8985 master clock (C4i) is 4.096 MHz signal allowing serial data link configuration at 2.048 Mb/s to be implemented. The IDT72V8985 can automatically detect the presence of an input frame pulse, identify the type of backplane present on the serial interface, and format the synchronization pulse according to ST-BUS® or GCI interface specifications (active HIGH in GCI or...

STR-F6523

Vendor:SanKenPackage Cooled:64D/C:07+

!Features 1) Four channels of power MOS-H bridges are contained. 2) Available for PWM input. 3) Applicable for stepping-motor drive. 4) Separating VM into CH1, CH2 and CH3 / 4. 5) Low on-resistance 1.3Ω (typ.) 6) Low power consumption. 7) SSOP-B24 package.

STRF6523 T

STRF6524

Vendor:SANKENPackage Cooled:SIPD/C:02+

NOTES: 1. Dimension are in inches. 2. Metric equivalents are given for general information only. 3. Beyond r (radius) maximum, TH shall be held for a minimum length of .011 (0.28 mm). 4. Dimension TL measured from maximum HD. 5. Body contour optional within zone defined by HD, CD, and Q. 6. Leads at gauge plane .054 +.001 -.000 inch (1.37 +0.03 -0.00 mm) below seating plane shall be within .007 i...

STRF6526

Vendor:SanKenPackage Cooled:SIP-5P

The Hynix HYM71V16M655AT8 Series are 16Mx64bits Synchronous DRAM Modules. The modules are composed of eight 16Mx8bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 144pin glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on the PCB.

STRF6535

Vendor:SANKENPackage Cooled:ZIPD/C:n/a

4. Setting possible during non-induction It is possible to set a time period for which detection is ignored, as for example when voltage drops due to temporary heavy loads. 5. Ripple absorption pins It is possible to check fluctuations in detection through continuous rippling. 6. Built-in hysteresis voltage

STRF6535

Vendor:SANKENPackage Cooled:ZSIP5D/C:n/a

4. Setting possible during non-induction It is possible to set a time period for which detection is ignored, as for example when voltage drops due to temporary heavy loads. 5. Ripple absorption pins It is possible to check fluctuations in detection through continuous rippling. 6. Built-in hysteresis voltage

STR-F6552

Vendor:SanKenPackage Cooled:TO220D/C:2001

The boost-converter operating frequency can be set at 16, 24, or 32 times the backplane clock. This flexibility allows a high DC-DC converter frequency to be used with LCD backplane clock rates ranging from 20kHz to 72kHz. The MAX1664 is supplied in a 1.1mm-high TSSOP package.

STRF6553

Vendor:1600

Conceptually, the port clocks CKA and CKB are free- running, periodic clock waveforms, used to control other signals which are edge-sensitive. However, there actually is not any absolute requirement that these clock wave- forms must be periodic. An asynchronous mode of operation is possible, in one or both directions, inde- pendently, if the appropriate enable and request inputs are continuously asse...

STRF6601

STRF6612

Vendor:SANKEND/C:800

IF input frequency at IFInP, IFInM is 130 MHz. IF differential input voltage, Vif-in, 480 mVp-p across a matched 470Ω differential impedance (240 mVp-p at IFInP and IFInM, with a single ended impedance of 235Ω). This input level is calculated from a 50Ω power source delivering C12 dBm to a 9.4:1 impedance transforming network. The test circuit for this input is represented by components C...

STRF6614

D/C:08+/09+

Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 6. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Tra...

STRF6616

Vendor:SANKEND/C:800

Total Harmonic Distortion + Noise, Av = 2dB RL=32Ω, Po=10 mW, 20Hz < F < 20kHz, Single Ended RL=16Ω, Po=15 mW, 20Hz < F < 20kHz, Single Ended RL=32Ω, Po=10 mW, 20Hz < F < 20kHz, Phantom Ground RL=16Ω, Po=15 mW, 20Hz < F < 20kHz, Phantom Ground

STR-F6626

Port 2: Is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 2 pins that are being pulled low externally will be a source of current (IIL, see section "Electrical Characteristic") because of the internal pull-ups. Port 2 emits the high-order address byt...

STRF6629

Vendor:SANKEN

Wideband SFDR: 1 C 20 MHz Analog Out 20 C 40 MHz Analog Out 40 C 60 MHz Analog Out 60 C 80 MHz Analog Out 80 C 100 MHz Analog Out 100 C 120 MHz Analog Out 120 C 140 MHz Analog Out 140 C 160 MHz Analog Out Narrow Band SFDR 10 MHz Analog Out (1 MHz) 10 MHz Analog Out (250 kHz) 10 MHz Analog Out ( 50 kHz) 10 MHz Analog Out ( 10 kHz) 65 MHz Analog Out ( 1 MHz) 65 MHz Analog Out ( 250 kHz) ...

STRF6629B

Vendor:SKPackage Cooled:ZIP5D/C:99

Hynix HYMD216726A(L)6-M/K/H/L series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 16Mx72 high-speed memory arrays. Hynix HYMD216726A(L)6-M/K/ H/L series consists of eighteen 16Mx16 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD216726A(L)6-M/K/H/L series provide a high performance 8-byte interface in 5.25...

STRF6629B T

STRF6632

Vendor:SKPackage Cooled:ZIP5D/C:99

• AN1831/D Using MC68HC908 On-Chip Programming Routines • AN2093/D Creating Efficient C Code for the MC68HC08 • AN1219/D M68HC08 Integer Math Routines • AN1218/D HC05 to HC08 Optimization • AN1837/D Non-Volatile Memory Technology Review • AN1752/D Data Structures for 8-bit MCUs • AN1705/D Noise Reduction Techniques for MCU-Based Systems

STR-F6652

Vendor:SanKenPackage Cooled:TO220D/C:2001

• The use of twin crossbar contacts en- sures high contact reliability. AgPd contact is used because of its good sulfide resistance. Adopting low-gas molding material. Coil assembly molding technology which avoids generating vola- tile gas from coil. • Increased packaging density

STRF6653 T

STRF6654LF57

STR-F6656

Vendor:SANKEND/C:06+

associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola andare registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/

STRF6656 T

STRF6658

Vendor:SKPackage Cooled:ZIPD/C:99

To summarize, the general approach is to: Determine the tone(s) you want to detect. Calculate the required coefficients to generate the tone(s) using the Excel spreadsheet from the CML website (web location provided above). Load those coefficients into the CMX866 Programming Register.

STRF6658

Vendor:SKPackage Cooled:ZIPD/C:99

To summarize, the general approach is to: Determine the tone(s) you want to detect. Calculate the required coefficients to generate the tone(s) using the Excel spreadsheet from the CML website (web location provided above). Load those coefficients into the CMX866 Programming Register.

STRF6658 T

STRF6658B

Vendor:600Package Cooled:TO3P-5

PA0~PA7 constitute an 8-bit bidirectional input/output port with Schmitt trig- ger input capability. Each bit on port can be configured as wake-up input by options. PA0~PA3 can be configured as CMOS output or NMOS input/out-Wake-up I/O Pull-high or None put with or without pull-high resistor by options. PA4~PA7 are always CMOS or NMOS pull-high NMOS input/output. Of the eight bits, PA0~PA1 can be set...

STRF6658B

Vendor:600Package Cooled:TO3P-5

PA0~PA7 constitute an 8-bit bidirectional input/output port with Schmitt trig- ger input capability. Each bit on port can be configured as wake-up input by options. PA0~PA3 can be configured as CMOS output or NMOS input/out-Wake-up I/O Pull-high or None put with or without pull-high resistor by options. PA4~PA7 are always CMOS or NMOS pull-high NMOS input/output. Of the eight bits, PA0~PA1 can be set...

STR-F6658B

1. VCC and GND This IC has two VCC terminals and three GND terminals. Pattern layout should be designed carefully to reduce the common impedance. VCC VCC (pin 17): Preamplifier stage and power amplifier stage. GVN VCC (pin 16): Motor governor stage. GND PRE GND (pin 1): Preamplifier stage and power amplifier stage except the power drive stage. PW GND (pin 11): Power drive stage of power amplifier...

STRF6667B

Vendor:SKPackage Cooled:ZIP5D/C:99

This specification describes the Bt8110 and Bt8110B multichannel ADPCM processor CMOS integrated circuits that implement Adaptive Differential Pulse-Code Modulation (ADPCM) encoding and decoding. The fixed-rate coding algorithms include those specified in ANSI Standard T1.303-1989. These algorithms are identical to those in ITU-T Recommendations G.726 and G.727. These circuits also implement the variable-rat...

STRF6668

Vendor:400

• JPEG Codec : max. 5M Pixel • MPEG4 Codec - Support ISO 14496-2 MPEG4 SOP @ L3 - Real Time Video Codec : QVGA @ 30fps - Variable Picture Size : Programmable by 16pixel - Large Motion Search Range : Half-Pel Accuracy X = [-64, +64], Y= [-32, +32] - Bit Rate Control : VBR/CBR - Programmable I frame Insertion - Motion Detection & Scene Change Detection - Color Format : 4:2:2 ...

STRF6668B

Vendor:1600

STRF6668B

Vendor:1600

STR-F6672

Package Cooled:TO220

n Internal Start-up Bias Regulator n 3A Compound Main Gate Driver n Programmable Line Under-Voltage Lockout (UVLO) with Adjustable Hysteresis n Voltage Mode Control with Feed-Forward n Adjustable Dual Mode Over-Current Protection n Programmable Overlap or Deadtime between the Main and Active Clamp Outputs n Volt x Second Clamp n Programmable Soft-start n Leading Edge Blanking n Single Resistor...

STRF6672 T

STRF6706A

D/C:08+/09+

Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult the EVM Users Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.

STRF6706A

D/C:08+/09+

Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult the EVM Users Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.

STRF6707

Vendor:SANKENPackage Cooled:ZIP5

The FAN4174 is designed on a CMOS process and provides 3.7MHz of bandwidth and 3V/µs of slew rate at a supply voltage of +5V. The combination of low power, rail-to-rail performance, low voltage operation, and tiny package options make the FAN4174 well suited for use in many gen- eral purpose and battery powered applications.

STRF6707A

Vendor:SANKENPackage Cooled:DIPD/C:02+

NOTES: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may overshoot VSS to -2.0 V for periods of up to 20ns. Maximum DC voltage on output and I/O pins is VCC + 0.5V. During voltage trans...

STRF6709A

Package Cooled:2000

STRG5551

Vendor:SKPackage Cooled:ZIP5D/C:99

In addition to the three required external power supplies, a +3.3V supply is required for the PCM1742. The +3.3V supply is typically derived from VCC using an onboard linear regulator, the REG1117-3.3 (U051). A jumper must be installed at CN057 to connect the regulator output to the PCM1742.

STRG5623A

Vendor:300

The OPA860 is a versatile monolithic component designed for wide-bandwidth systems, including high performance video, RF and IF circuitry. It includes a wideband, bipolar operational transconductance amplifier (OTA), and voltage buffer amplifier.

STR-G5623A

Vendor:SKPackage Cooled:TO-220/5D/C:04+

STRG5624

Vendor:340Package Cooled:STRD/C:N/A

RESERVED: RES pins are reserved for future device enhancements or functionality. These pins may be left floating or may be driven. If the pins are driven, the voltage levels should comply with VIH and VIL requirements. These pins are used as the RDY/BSY and I/O[7:4] pins in the A/A Mux interface.

STRG5624

Vendor:340Package Cooled:STRD/C:N/A

RESERVED: RES pins are reserved for future device enhancements or functionality. These pins may be left floating or may be driven. If the pins are driven, the voltage levels should comply with VIH and VIL requirements. These pins are used as the RDY/BSY and I/O[7:4] pins in the A/A Mux interface.

STR-G5624

Vendor:SKPackage Cooled:TO-220/5PD/C:02+

Data flow in each direction is controlled by the output-enable (OEAB and OEBA) and clock (CLKAB and CLKBA) inputs. The clock-enable (CEAB and CEBA) inputs enable or disable the clock for all 18 bits at a time. However, OEAB and OEBA are designed to control each 9-bit transceiver independently, which makes the device more versatile.

STR-G5624A

Vendor:SANKENPackage Cooled:TO220F-5

slew-rate control structure with four configurable options for each individual output driver: fast, medium fast, me- dium slow, and slow. Slew-rate control can alleviate ground-bounce problems when multiple outputs switch simultaneously, and it can reduce or eliminate crosstalk and transmission-line effects on printed circuit boards.

STRG5643

Vendor:100Package Cooled:ZIPD/C:04+

Series W. Series W are rugged, ceramic, cylindrically shaped elements for use in the temperature range from -50 to 600C (-58 to 1112F). Elements have .015" gold palladium alloy leads approximately 0.4" long, which are strain relieved in the stress free ceramic body. Elements are available in both single and dual configurations with resistances at 0C (32F) of 100, 200, 400, 500, 1000 ...

STRG5643D

Vendor:SKD/C:99

RTN - is the power return connection from the module to the bus. All ground returns connect to this point from internal to the module in a star fashion. All external ground connections to this point should also be made in a similar fashion. The V+ capacitors should be returned to this pin as close as possible. Wire sizing to this pin connection should be made according to the required current.

STR-G5643D

Vendor:SANKENPackage Cooled:TO220-5LD/C:06+

(VDD = 2.7V to 3.6V (STR-G5643D/STR-G5643D), VDD = 4.5V to 5.5V (STR-G5643D/STR-G5643D), VREF = 2.048V (STR-G5643D/STR-G5643D), VREF = 4.096V (STR-G5643D/STR-G5643D), CREF = 0.1µF, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C. See Tables 1C5 for programming notation.)

STRG6151

Vendor:SKPackage Cooled:ZIP5D/C:99

STRG6152

Vendor:300

If a 1Cwire device is present on the I/O line it pulls I/O low after time T (15 µs T 60 µs) from the previous rising edge. The 1Cwire device(s) holds the I/O line low for 4T and then releases it, allowing the I/O line to return high. This is the presence detect pulse. The I/O line must remain high (in its idle state) for at least 3T before the 1Cwire device(s) is ready for further communi...

STRG6152

Vendor:300

If a 1Cwire device is present on the I/O line it pulls I/O low after time T (15 µs T 60 µs) from the previous rising edge. The 1Cwire device(s) holds the I/O line low for 4T and then releases it, allowing the I/O line to return high. This is the presence detect pulse. The I/O line must remain high (in its idle state) for at least 3T before the 1Cwire device(s) is ready for further communi...

STRG6153

Vendor:340Package Cooled:STRD/C:N/A

Die Attach The die attach process mechanically attaches the die to the circuit substrate. In addition, it electrically connects the ground to the trace on which the chip is mounted, and establishes the thermal path by which heat can leave the chip.

STRG6153 T

STRG6351

Vendor:340Package Cooled:TO220-5D/C:N/A

Note 4: Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 110oC), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (JA), as given by the following equation: TA-MAX = TJ-MAX-OP - (JA x PD-MAX). The ambient temperature operating rating is pro...

STRG6352

Vendor:340Package Cooled:STRD/C:N/A

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.

STR-G6352

Vendor:SANKEN

National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no Banned Substances as defined in CSP-9-111S2.

STRG6353

Vendor:SANKENPackage Cooled:ZIPD/C:02+

Output Current (each output) Power Off Leakage, VCC = 0, C10 V p VO p +10 V High Impedance Mode, VCC = 5.25 V, C10 V p VO p +10 V Short Circuit Current (Note 2.) High Output Shorted to Pin 5 (TA = 25C) High Output Shorted to Pin 5 (C40C t TA t+85C) Low Output Shorted to +6.0 V (TA = 25C) Low Output Shorted to +6.0 V (C40C t TA t +85C)

STR-G6353

Vendor:SANKENPackage Cooled:TO220F-5

Any input can be modulated by a pulse train of variable duty cycle (ä). By turning ON and OFF DAC inputs A or B, the current can be continuously modulated to any average value between 1 to 19mA. For a maximum range of LED current, both A&B can be modulated at the same time.

STRG6551

Vendor:348Package Cooled:STRD/C:N/A

Reset input. Active Low Schmitt-Trigger input. The Schmitt-Trigger input allows a slowly-rising input to reset the chip reliably. The RESET signal must be asserted Low during power up. Deassert High for normal operation. This input is 5V tolerant.

STR-G6551

Vendor:SANKENPackage Cooled:TO220FD/C:05+

• 2.7VC3.6V operation • CMOS for optimum speed/power • Low active power (70 ns, LL version) 54 mW (max.) (15 mA) • Low standby power (70 ns, LL version) 54 µW (max.) (15 µA) • Automatic power-down when deselected Power down either with CE or BHE and BLE HIGH • Independent control of Upper and Lower Bytes • Available in 44-pin TSOP II (forward) and...

STRG6614

Vendor:340Package Cooled:STRD/C:N/A

Receiver Section The receiver section includes the Receiver Optical Subassembly (ROSA) and amplification/ quantization circuitry. The ROSA, containing a PIN photodiode and custom trans-impedance preamplifier, is located at the optical interface and mates with the LC optical connector. The ROSA is mated to a custom IC that provides post-amplification and quantization. Also included is a Los...

STRG6624

Vendor:340Package Cooled:TO220-5D/C:N/A

Typical specifications represent average readings at 25C and VDD = 5 V. Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3VAB = VDD, Wiper (VW) = no connect. 4INL and DNL a...

STR-G6624

Vendor:SanKenPackage Cooled:TO220-5D/C:2004

Each channel is identical, featuring symmetrical propagation delays for better high speed performance. Input common mode rejection is excellent and threshold voltage is stable, independent of supply voltage. Data outputs are TTL and CMOS compatible.

STR-G6624

Vendor:SanKenPackage Cooled:TO220-5D/C:2004

Each channel is identical, featuring symmetrical propagation delays for better high speed performance. Input common mode rejection is excellent and threshold voltage is stable, independent of supply voltage. Data outputs are TTL and CMOS compatible.

STRG6632

Vendor:SKPackage Cooled:TO220-5D/C:01+

Mono-BTL Output Power (RL = 8Ω, VDD = 3.0V, THD+N = 1%)410mW (typ) Single Ended Output Power Per Channel (RL = 16Ω, VDD = 3.0V, THD+N = 1%)40mW (typ) Micropower shutdown current0.1µA (typ) Supply voltage operating range1.5V < VDD < 3.6V PSRR 100Hz, VDD = 3V, BTL70dB (typ)

STRG6642

Package Cooled:TO-220-5

STR-G6653

Vendor:450Package Cooled:TO-220/5P

Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, plac- ing it in the active power mode. Prior to the start of any operation after power up, a HIGH to LOW transition on CS is required. Watchdog Input. A HIGH to LOW transition on the WDI p...

STR-G6653(LF1133)

Hynix HYMD264G726(L)8-K/H/L series is registered 184-pin double data rate Synchronous DRAM Dual In-Line Mem- ory Modules (DIMMs) which are organized as 64Mx72 high-speed memory arrays. Hynix HYMD264G726(L)8-K/H/L series consists of eighteen 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD264G726(L)8-K/H/L series provide a high performance 8-byte interface in 5.25"...

STRG7401

Vendor:340Package Cooled:STRD/C:N/A

To operate a port as a 1394b bilingual port, the speed/mode selections terminals (S5_LKON, S4, S3, S2_PC0, S1_PC1, and S0_PC2) need to be pulled to VCC or ground through a 1-kΩ resistor. The port must be operated in the 1394b bilingual mode whenever a 1394b bilingual or a 1394b beta-only connector is connected to the port. To operate the port as a 1394a-only port, the speed/mode selection terminals ...

STRG8050

Vendor:340Package Cooled:STRD/C:N/A

For proper operation, input and output pins must be constrained to the range GND < (VIN or VOUT) < VCC. Unused inputs must always be tied to an appropriate logic level (either VCC or GND). Each set of VCC and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2 µF must be connected between VCC and GND. For the most effective decoupling...

STRG8626

Vendor:200Package Cooled:ZIPD/C:99

The SML-311 series are low power con- sumption, chip LEDs equipped with an AlGalnP chip. These LEDs are compact and leadless to allow a higher mounting density, and low power consumption makes them an ideal light source for battery driven products.