TE28F800CVB60

Vendor:INTELPackage Cooled:SOP48D/C:04+

TE28F800CVB70

Vendor:10800Package Cooled:INTEL

C Correlated Double Sampling (CDS) C Programmable Black Level Clamping Programmable Gain Amplifier (PGA) C6-dB to 42-dB Gain Ranging 12-Bit Digital Data Output: C Up to 28-MHz Conversion Rate C No Missing Codes 77-dB Signal-To-Noise Ratio Portable Operation: C Low Voltage: 2.7 V to 3.6 V C Low Power: 94 mW (Typ) at 3 V C Stand-By Mode: 6 mW

TE28F800CVB70

Vendor:10800Package Cooled:INTEL

C Correlated Double Sampling (CDS) C Programmable Black Level Clamping Programmable Gain Amplifier (PGA) C6-dB to 42-dB Gain Ranging 12-Bit Digital Data Output: C Up to 28-MHz Conversion Rate C No Missing Codes 77-dB Signal-To-Noise Ratio Portable Operation: C Low Voltage: 2.7 V to 3.6 V C Low Power: 94 mW (Typ) at 3 V C Stand-By Mode: 6 mW

TE28F800CVB80

Vendor:INTELPackage Cooled:TSOPD/C:2005+

This controller is a full featured floppy disk controller that is software compatible with the mPD765A but also includes many additional hardware and software enhancements These enhancements include additional logic specifically re- quired for an IBM PC PC-XT PC-AT or PS 2 design This controller incorporates a precision analog data separa- tor that includes a self trimming delay line and VCO Up to thre...

TE28F800CVB-90

Vendor:INTELPackage Cooled:TSOPD/C:N/A

The transceiver provides an internal loopback capability for self-test purposes. Serial data from the serializer is passed directly to the deserializer, allowing the protocol device a functional self-check of the physical interface.

TE28F800CVT

Vendor:INTELD/C:TSSOP-48

TE28F800CVT120

Vendor:10800Package Cooled:INTEL

TE28F800CVT70

Vendor:10800Package Cooled:684

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage va...

TE28F800CVT70

Vendor:10800Package Cooled:684

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage va...

TE28F800CVT-70

Vendor:INTELPackage Cooled:SSMD

* On products compliant to MIL-PRF-38535, this parameter is not production tested. † All typical values are at VCC = 3.3 V, TA = 25C. ‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

TE28F800CVT80

Vendor:10800Package Cooled:INTEL

Oscillators VCO Crystal oscillator PLL FM signal channel DAA FM I/Q mixer FM keyed AGC FM IF amplifiers FM demodulator FM MPX soft mute Ultrasonic noise detector AM signal channel AM tuner AM RF AGC and IF2 AGC AM AF or IF2 switch AM soft mute AM noise blanker FM and AM level detector Input for external mute Buffer output for weather band flag Test mode

TE28F800CVT90

The RS-232 port in most portable systems transmits and receives for only a small percentage of the time that power is applied; for the rest of the time it may waste power needlessly. An ideal RS-232 transceiver, therefore, should shut itself down when not transmitting or receiving.

TE28F800CV-T90

Vendor:INTELPackage Cooled:TSSOP-48D/C:N/A

Each red, green and blue current output should have a load resistor connected to AVDD. The resistors are typically 75 Ω and should be kept in the 72 Ω to 85 Ω range. The outputs should drive a high impedance load such as a voltage follower.

TE28F800CVT-90

Vendor:INTELPackage Cooled:TSOPD/C:1137

The A1425 ac-coupled Hall-effect sensor is a monolithic integrated circuit that switches in response to changing differential magnetic fields created by rotating ring magnets or, when coupled with a magnet, by ferrous targets. The device is a true zero-crossing detector: the output switches precisely when the difference in magnetic field strength between the two Hall elements is zero. A unique ...

TE28F800CVT-90

Vendor:INTELPackage Cooled:TSOPD/C:1137

The A1425 ac-coupled Hall-effect sensor is a monolithic integrated circuit that switches in response to changing differential magnetic fields created by rotating ring magnets or, when coupled with a magnet, by ferrous targets. The device is a true zero-crossing detector: the output switches precisely when the difference in magnetic field strength between the two Hall elements is zero. A unique ...

TE28F800F3B120

Vendor:10800Package Cooled:INTEL

TE28F800F3B95

Vendor:10800Package Cooled:INTEL

The 283 high speed 4-bit binary full adders with internal carry lookahead accept two 4-bit binary words (A0CA3 B0C B3) and a Carry input (C0) They generate the binary Sum outputs (S0CS3) and the Carry output (C4) from the most significant bit They operate with either active HIGH or ac- tive LOW operands (positive or negative logic)

TE28F800F3T120

Vendor:10800Package Cooled:INTEL

The device offers a highly integrated solution for a satellite tuner incorporating a low phase noise PLL frequency synthesizer, the quadrature down converter, a fully integrated local oscillator, and programmable baseband channel filters. A minimal number of additional peripheral components are required. The crystal reference source can be also used as the reference for the demodulator.

TE28F800F3T95

Vendor:10800Package Cooled:INTEL

mode with little power consumption. It can also operate with high speed system clock rate of 3.58MHz in normal mode for high performance operation. To ensure smooth dialer function and to avoid MCU shut-down in extreme low voltage situation, the dialer I/O circuit is built-in to generate hardware dialer signals such as on-hook, hold-line and hand-free. Built-in real time clock and programmable frequency divi...

TE28T800

Vendor:INTELPackage Cooled:705D/C:07+

TE28WG800-10T

Vendor:10800Package Cooled:INTEL

TE330

initial offset and gain errors can be reduced to zero using the adjustment circuitry shown in Figures 3 and 4. For operation without adjustment, tie pin 17 to analog ground. When using this circuitry, or any similar offset and gain- calibration hardware, make adjustments following warmup. To avoid interaction, always adjust offset before gain.

TE381-7

D/C:07+/08+

If the STBY* input (pin 8) is left open-circuit the regulator operates normally, providing a regulated output when a valid supply voltage is applied to Vin (pins 10-12) with respect to GND (pins 14-18). Connecting pin 8 to ground1 places the regulator in standby mode 2, and reduces the input current to typically 20mA (30mA max). Applying a ground signal to pin 8 prior to power-up, will disable the outp...

TE4100B

Vendor:TELPackage Cooled:QFPD/C:08+09+

RESET: An active high signal on this pin will put the chip into an inactive state. All Control Register bits (CR0, CR1, tone) will be reset. The output of the CLK pin will be set to the crystal frequency. An internal pull-down resistor permits power-on-reset using a capacitor to VDD.

TE4300

Vendor:TELPackage Cooled:04+D/C:QFP

Note 1) The specified condition Tj=25˚C means that the test should be carried out with the test time so short (within 10ms) that the drift in characteristic value due to the rise in chip junction temperature can be ignored. Note 2) When not specified, VI=10V, IO=100mA, CI=0.33µF, CO=0.1µF, Tj=0 to 125˚C

TE4300

Vendor:TELPackage Cooled:04+D/C:QFP

Note 1) The specified condition Tj=25˚C means that the test should be carried out with the test time so short (within 10ms) that the drift in characteristic value due to the rise in chip junction temperature can be ignored. Note 2) When not specified, VI=10V, IO=100mA, CI=0.33µF, CO=0.1µF, Tj=0 to 125˚C

TE4300PF

Vendor:TELPackage Cooled:TELD/C:06+

The MAXQ3120 microcontroller is a high-performance, 16-bit microcontroller that incorporates dual, true-differen- tial, 16-bit sigma-delta analog-to-digital converters (ADCs), a liquid-crystal display (LCD) interface that can drive up to 112 segments, and a real-time clock (RTC) module with a dedicated battery-backup supply. The MAXQ3120 is uniquely suited for the single-phase elec- tricity metering market, ...

TE505S16-25LC

Package Cooled:QFP

The power supply of the device must start its ramp from 0.0 V. Functional operating conditions are provided with the DC electrical specifications in Table 5. Absolute maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. Caution: All inputs that tolerate 5 V cannot be ...

TE505S16-25LC

The power supply of the device must start its ramp from 0.0 V. Functional operating conditions are provided with the DC electrical specifications in Table 5. Absolute maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. Caution: All inputs that tolerate 5 V cannot be ...

TE505S1640LC

TE505S16-40LC

Vendor:TRISCENDPackage Cooled:QFPD/C:08+09+

functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

TE50R128134

Vendor:TEXASINSTR

TE512S32-40LC

Vendor:TRISCENDPackage Cooled:TQFPD/C:111

ON Semiconductors e2 PowerEdge family of low VCE(sat) transistors are miniature surface mount devices featuring ultra low saturation voltage (VCE(sat)) and high current gain capability. These are designed for use in low voltage, high speed switching applications where affordable efficient energy control is important. Typical application are DC−DC converters and power management in portable and ba...

TE53N50

Vendor:MOTOROLAD/C:1000

(AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, AGND = 0, DGND = 0, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)

TE53N50

Vendor:MOTOROLAD/C:1000

(AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, AGND = 0, DGND = 0, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)

TE607-3(REG607003)

Vendor:PULSED/C:400

Addresses and data needed for the programming and erase operations are internally latched during write cycles, and the host system can detect completion of a program or erase operation by observing the RY/BY# pin, or by reading the DQ[7] (Data# Polling) and DQ[6] (toggle) status bits. Reading data from the device is similar to reading from SRAM or EPROM devices. Hardware data protection measures in...

TE612

Package Cooled:QFND/C:06+

TE6136

The blocks in the memory are asymmetrically ar- ranged, see Tables 3A and 3B, Block Addresses. The first or last 64 Kbytes have been divided into four additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the ap- plication m...

TE6137

Vendor:TELPackage Cooled:TQFPD/C:2001

Drain- Source Voltage Continuous Drain Current, VGS @ -10V Continuous Drain Current, VGS @ -10V Pulsed Drain Current  Power Dissipation ƒ Power Dissipation ƒ Linear Derating Factor Gate-to-Source Voltage Junction and Storage Temperature Range

TE623

TE6311LA

Vendor:TELPackage Cooled:500D/C:97

Input Resistor Matching Input Resistor Temp. Coefficient REFERENCE INPUTS REFIN(+) to REFIN(C) Voltage1, 9 NOREF Trigger Voltage REFIN(+), REFIN(C) Common-Mode Voltage1 Reference Input DC Current10 SYSTEM CALIBRATION1, 11 Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span

TE6321P

Package Cooled:QFPD/C:07+

TE6331B

Vendor:PHILIPSPackage Cooled:QFPD/C:NULL

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or writ...

TE6341B

576 x 16-bit high-performance CMOS Dynamic Random Access Memories. These devices offer an accelerated cycle access called EDO Page Mode. EDO Page Mode allows 1,024 random accesses within a single row with access cycle time as short as 20 ns per 16-bit word. The Byte Write control, of upper and lower byte, makes the 16100 series ideal for use in 16-, 32-bit wide data bus systems.

TE6350

Package Cooled:QFPD/C:07+

TE6350B

Vendor:TELPackage Cooled:QFPD/C:9802+

Specifications with standard typeface are for TJ = 25˚C, and those with boldface type apply over full Operating Junction Temperature range. VIN = 48V, VCC = 10V, RT = 31.3kΩ, RSET = 27.4kΩ) unless otherwise stated (Note 3)

TE6350C

Package Cooled:632

3V to 3.6V operating voltage 50MHz to 160MHz output frequency range Input from fundamental crystal oscillator or external source Internal PLL feedback (loading feedback output relative to other outputs, adjusts propagation delay between REF inputs and outputs) Select inputs (S[1:0]) for FB divide selection (multiply ratio of 2, 3, 4, 4.25, 5, 6, 6.25, and 8) Low jitter PLL bypass for testing and pow...

TE63V471QA

TE6510

Vendor:TERPackage Cooled:DIP

ANALOG I/O 8-Channel, 400kSPS High Accuracy, 12-Bit ADC On-Chip, 20 ppm/ o C Voltage Reference DMA Controller, High-Speed ADC-to-RAM capture Two 12-Bit Voltage Output DACs Dual Output PWM-SD DACs On-Chip Temperature Monitor Function 8051 Based Core 8051-Compatible Instruction Set (16.7 MHz Max) High performance Single Cycle Core* 32kHz Ext Crystal,On-Chip Programmable-PLL 12 Interrupt Sources...

TE6510

Vendor:TERPackage Cooled:DIP

ANALOG I/O 8-Channel, 400kSPS High Accuracy, 12-Bit ADC On-Chip, 20 ppm/ o C Voltage Reference DMA Controller, High-Speed ADC-to-RAM capture Two 12-Bit Voltage Output DACs Dual Output PWM-SD DACs On-Chip Temperature Monitor Function 8051 Based Core 8051-Compatible Instruction Set (16.7 MHz Max) High performance Single Cycle Core* 32kHz Ext Crystal,On-Chip Programmable-PLL 12 Interrupt Sources...

TE7000 AO SMT0119L128

TE7533A

All signals are TTL levels, including programming sig- nals. Bit locations may be programmed singly, in blocks, or at random. The Am27C256 supports AMDs Flashrite programming algorithm (100 µs pulses) resulting in typi- cal programming time of 4 seconds.

TE7635A

Vendor:TELPackage Cooled:DIP-40D/C:00+

True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed access C Commercial: 10/12/15ns (max.) C Industrial: 12ns (max.) Dual chip enables allow for depth expansion without external logic IDT70V631 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master, M/S...

TE7730

Analog output from the sample and hold phase comparator for use as a fine error signal. Voltage increases as fv (the output from the M counter) phase lead increases; voltage decreases as fr (the output from the reference counter) phase lead increases. Output is linear over only a narrow phase window, determined by gain (programmed by RB). In a type 2 loop, this pin is at (VDD2VSS)/2 when the system is in lo...

TE7730

Analog output from the sample and hold phase comparator for use as a fine error signal. Voltage increases as fv (the output from the M counter) phase lead increases; voltage decreases as fr (the output from the reference counter) phase lead increases. Output is linear over only a narrow phase window, determined by gain (programmed by RB). In a type 2 loop, this pin is at (VDD2VSS)/2 when the system is in lo...

TE7750

Package Cooled:QFPD/C:00+

The addition of a bias circuit in conjunction with this process results in extremely stable parameters with both time and temperature. This means that a precision device remains a precision device even with changes in temperature and over years of use.

TE7752

DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU. ‡ PLLVDD and PLLVSS are isolated PLL supply pins that should be externally connected to CVDD and VSS, respectively.

TE7754

Vendor:TELPackage Cooled:QFPD/C:02+

Pb−Free Packages are Available Trimmed Oscillator for Precise Frequency Control Oscillator Frequency Guaranteed at 250 kHz Current Mode Operation to 500 kHz Output Switching Frequency Output Deadtime Adjustable from 50% to 70% Automatic Feed Forward Compensation Latching PWM for Cycle−By−Cycle Current Limiting Internally Trimmed Reference with Undervoltage Lockout High Current Totem ...

TE7782PF

Vendor:TQFP144Package Cooled:600D/C:TEL

During the turnCon and turnCoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG C VGSP)] td(off) = RG Ciss In (VGG/VGSP)

TE7782PF

Vendor:TQFP144Package Cooled:600D/C:TEL

During the turnCon and turnCoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG C VGSP)] td(off) = RG Ciss In (VGG/VGSP)

TE7814H

Vendor:TELPackage Cooled:100D/C:98+

IDT70261 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port TTL-compatible, single 5V (10%) power supp...

TE7856

Vendor:IN STOCKPackage Cooled:QFPD/C:FUJITSU

The PSD3XX family architecture (Figure 1) can efficiently interface with, and enhance, almost any 8- or 16-bit microcontroller system. This solution provides microcontrollers the following: • Chip-select logic, control logic, and latched address signals that are otherwise implemented discretely • Port expansion (reconstructs lost microcontroller I/O) • Expanded microcontroller addre...

TE8200PF

Package Cooled:QFPD/C:03+

TE842016

Vendor:TEPackage Cooled:TED/C:02+

The ADSP-21262 continues SHARCs industry leading stan- dards of integration for DSPs, combining a high performance 32-bit DSP core with integrated, on-chip system features. These features include 2 Mbits dual-ported SRAM memory, 4 Mbits dual-ported ROM, an I/O processor that supports 22 DMA channels, six serial ports, an SPI interface, external parallel bus, and Digital Audio Interface (DAI).

TE98880

Vendor:TOKYOPackage Cooled:4000D/C:新

1.1 END USER shall mean the person and/or organization to whom the AMBE- 2000™ Vocoder Chip was delivered or provided to as specified in the purchase order or other documentation. In the event that the END USER transfers his rights under this license to a third party as specified in section 2.2, then this third party shall become an END USER. 1.2 Digital Voice Systems, Inc. (DVSI) has developed a v...

TEA0652

Package Cooled:07+D/C:2080

The 64Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE

TEA0652/V1

Vendor:SigneticsPackage Cooled:DIPD/C:1987

• 0.5 MICRON CMOS Technology • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4µ W typ. static)µ • Rail-to-Rail output swing for increased noise margin • All inputs, outputs, and I/Os are 5V tolerant • S...

TEA0652/V1

Vendor:SigneticsPackage Cooled:DIPD/C:1987

• 0.5 MICRON CMOS Technology • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4µ W typ. static)µ • Rail-to-Rail output swing for increased noise margin • All inputs, outputs, and I/Os are 5V tolerant • S...

TEA0652S

Vendor:PHILIPSPackage Cooled:DIPD/C:03+

TEA0652V1

Vendor:phPackage Cooled:phD/C:dc90

The VC-710 is a voltage controlled crystal oscillator that operates at the fundamental frequency of the internal HFF crystal. The HFF crystal is a high-Q quartz device that enables the circuit to achieve low phase jitter performance over a wide operating temperature range. The oscillator is housed in an industry standard hermetically sealed leadless surface mount package and is available on tape and reel.

TEA0653T/V1

Package Cooled:90D/C:1000

Average Beam Current Limiter Analog RGB Insertion Fast Blank Monitor Half Contrast Control IO Port Expander Synchronization and Deflection Deflection Processing Angle & Bow Correction Horizontal Phase Adjustment Vertical and East/West Deflection EHT Compensation Protection Circuitry Reset and Power On Serial Interface I2C-Bus Interface Control and Status Registers Scaler Adjustment ...

TEA0655

Vendor:phPackage Cooled:8D/C:dc92

The small signal gain is larger than 15dB up to 2GHz at the nominal bias of 3V. The corresponding gain/DC-power figure of merit is 2.9dB/mW. Compared to other L-band LNAs, this design shows low power consumption and a competitive noise figure as seen from Fig. 4.

TEA0665

Vendor:13Package Cooled:N/AD/C:N/A

Transceivers through Standard MII Ports Dual ARM7TDMI® RISC Processor Architecture Inter-networking ARM7TDMI (INWARM) with 16 Kbytes Program and Data Cache Controls the Ethernet MAC Units and Provides the Bridging Functions between Ethernet and Wireless Interfaces WLAN ARM7TDMI (WLANARM) with a Dedicated 32 Kbytes Program Memory Coordinates the 802.11b MAC Functionality 802.11b MAC Unit with 512-byte Tra...

TEA0665

Vendor:13Package Cooled:N/AD/C:N/A

Transceivers through Standard MII Ports Dual ARM7TDMI® RISC Processor Architecture Inter-networking ARM7TDMI (INWARM) with 16 Kbytes Program and Data Cache Controls the Ethernet MAC Units and Provides the Bridging Functions between Ethernet and Wireless Interfaces WLAN ARM7TDMI (WLANARM) with a Dedicated 32 Kbytes Program Memory Coordinates the 802.11b MAC Functionality 802.11b MAC Unit with 512-byte Tra...

TEA0665T

Vendor:sigD/C:dc91

See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout), other memory locations can be changed by the regular programming method.

TEA0675T

Vendor:PHIPackage Cooled:SOP-24PD/C:05+

After application of the VCC supply, an initial pause of 200 µs is required followed by a minimum of eight initial- ization cycles (any combination of cycles containing a RAS signal). During power-on, it is recommended that RAS track with VCC or be held at a valid VIH to avoid current surges.

TEA0675T/V2

Vendor:PHIPackage Cooled:PHILIPSD/C:9843

Equivalent input rise time bandwidth assumes a first-order input response and is calculated by the following formula: BWEQ = 0.22/ (trCOMP2 C trIN2), where trIN is the 20/80 input transition time applied to the comparator and trCOMP is the effective transition time as digitized by the comparator input.

TEA0675T/V2/N

Vendor:ＮＸＰ

TEA0675TV2

Vendor:phPackage Cooled:phD/C:dc0426

Recommended Application: ALI - Aladdin V™ - mobile style chipsets Output Features: • 3 - CPUs @ 2.5/3.3V, up to 100MHz. • 3 - AGPCLK @ 3.3V • 13 - SDRAM @ 3.3V • 6 - PCI @ 3.3V • 1 - 48MHz, @ 3.3V fixed. • 1 - REF @ 3.3V, 14.318MHz. Features: • Support power management: CPU, PCI, AGP stop and Power down Mode from I2C programming. • Spread spectrum for ...

TEA0676

Package Cooled:SOPD/C:03+

The EP7311 uses its powerful 32-bit RISC processing engine to implement audio decompression algorithms in software. The nature of the on-board RISC processor, and the availability of efficient C-compilers and other software development tools, ensures that a wide range of audio decompression algorithms can easily be ported to and run on the EP7311

TEA0676T/V1/S1

Vendor:ＮＸＰ

TEA0679T

Vendor:PHILIPSPackage Cooled:SOP-7.2-32PD/C:2007+

retain data. During power-up, when VCC rises above approximately 3.0V, the power switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.75V for the DS1258AB and 4.5V for the DS1258Y.

TEA0679T/V1/S1

Vendor:PHIPackage Cooled:SOP/32D/C:00+

2. The inhibit control input is Not compatible with TTL devices. An open-collector device, preferably a discrete bipolar transistor (or MOSFET) is recommended. To ensure the regulator output is disabled, the control pin must be pulled to less than 0.6Vdc with a low-level 0.5mA sink to ground.

TEA0679TV1

Vendor:PHIPackage Cooled:952D/C:00+

TEA1000T

Vendor:PHILIPD/C:05+

Outputs from the GLBs in a Big Fast Megablock can drive both the Big Fast Megablock Routing Pool within the Big Fast Megablock and the Global Routing Plane between the Big Fast Megablocks. Switching resources are pro- vided to allow signals in the Global Routing Plane to drive any or all the Big Fast Megablocks in the device. This mechanism allows fast, efficient connections, both within the Big Fast...

TEA1002

Package Cooled:DIP

(*) CPD is defined as the value of the ICs internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD •VCC •fIN + ICC

TEA1002

Vendor:STPackage Cooled:DIP

(*) CPD is defined as the value of the ICs internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD •VCC •fIN + ICC

TEA1007

Vendor:TFKPackage Cooled:DIPD/C:02+

VFB (Pin 7): Error Amplifier Inverting Input. The noninvert- ing input of the error amplifier is connected to an internal 1.231V reference. The VFB pin is connected to a resistor divider from the converter output. Values for the resistor connected from VOUT to VFB (RFB1) and the resistor con- nected from VFB to ground (RFB2) can be calculated to pro- gram converter output voltage (VOUT) via the following rel...

TEA1010

Vendor:PHILIPS

The KM732V589A/L is a synchronous SRAM designed to support the burst address accessing sequence of the P6 and Power PC based microprocessor. All inputs (with the exception of OE and ZZ) are sampled on rising clock edges. The start and duration of the burst access is controlled by CS1, ADSC, ADSP and ADV. The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted...

TEA1011

Vendor:PHILIPSPackage Cooled:DIPD/C:03+

The CY7B993V/994V have a flexible REF and FB input scheme. These inputs allow the use of either differential LVPECL or single-ended LVTTL inputs. To configure as single-ended LVTTL inputs, the complementary pin must be left open (internally pulled to 1.5V). The other input pin can then be used as an LVTTL input. The REF inputs are also tolerant to hot insertion.

TEA1011P

Vendor:PHIPackage Cooled:98+D/C:07+

The MAX4821 features a 4-bit (A0, A1, A2, LVL) paral- lel-input interface. The first three bits (A0, A1, A2) deter- mine the output address, and the fourth bit (LVL) determines whether the selected output is switched on or off. Data is latched to the outputs when CS transi- tions from low to high. Both devices feature separate set and reset functions that allow the user to turn on or turn off all outputs sim...

TEA1011P

Vendor:STPackage Cooled:DIPD/C:07+

The MAX4821 features a 4-bit (A0, A1, A2, LVL) paral- lel-input interface. The first three bits (A0, A1, A2) deter- mine the output address, and the fourth bit (LVL) determines whether the selected output is switched on or off. Data is latched to the outputs when CS transi- tions from low to high. Both devices feature separate set and reset functions that allow the user to turn on or turn off all outputs sim...

TEA1015A

TEA1017

Vendor:PHILIPSPackage Cooled:DIP

The 18TQ Schottky rectifier series has been optimized for low reverse leakage at high temperature. The proprietary barrier technology allows for reliable operation up to 175C junction temperature. Typical applications are in switching power supplies, converters, free-wheeling diodes, and re- verse battery protection.

TEA1019

Vendor:PHID/C:2005

The MAX6501CMAX6504 low-cost, fully integrated tem- perature switches assert a logic signal when their die temperature crosses a factory-programmed threshold. Operating from a +2.7V to +5.5V supply, these devices feature two on-chip, temperature-dependent voltage references and a comparator. They are available with factory-trimmed temperature trip thresholds from -45C to +115C in 10C increments, and are accu...

TEA1020HP

Vendor:PHIPackage Cooled:QFP44D/C:01+

Note 1) All voltage are relative to VSS =0V reference. Note 2) The LSI must be used inside of the Absolute maximum ratings. Otherwise, a stress may cause permanent damage to the LSI. Note 3) De-coupling capacitors for VDD(Pin 1)-VSS(Pin 14), VDDO(Pin 7)-VSS(Pin 5) and VDDO(Pin 8)-VSS(Pin 10) should be connected for stable operation.

TEA1021A

TEA1022TS

Vendor:PHILIPS

The DS600 can also be used as a thermostat with either an active-high (TO) or active-low (TO) output. To function as a thermostat, a precise voltage reference equal to the desired threshold must be applied to the VTH pin. When the temperature with the equivalent voltage value is reached (voltage on VOUT = voltage on VTH), thermostat outputs TO and TO become active. Figure 3 shows an example thermostat applic...

TEA1024B

Vendor:tfkPackage Cooled:tfkD/C:dc96

• 3.3V operation • Three 8-bit pipelined processors for concurrent processing of application code and network traffic • Hardware UART/SPI interface • Eleven-pin I/O port programmable in 38 modes for fast application program development. I/O port is 5V input tolerant • Two 16-bit timer/counters for measuring and gener- ating I/O device waveforms • Five-pin commun...

TEA1024T

Vendor:PHILIPSPackage Cooled:3000D/C:2002

The MSK 610 is a high voltage very wideband amplifier designed to provide large voltage swings at high slew rates in wideband systems. The true inverting op-amp topology employed in the MSK 610 provides excellent D.C. specifications such as input offset voltage and input bias current. These attributes are important in amplifiers that will be used in high gain configurations since the input error voltages w...