TP-104-1-02

Vendor:C CORP

TP105

Vendor:n/aPackage Cooled:380D/C:99+

In operation, the output transistor is OFF until the strength of the mag- netic field perpendicular to the surface of the chip exceeds the threshold or operate point (BOP). When the field strength exceeds BOP, the output transis- tor switches ON and is capable of sinking 25 mA of current.

TP105

Vendor:n/aPackage Cooled:380D/C:99+

In operation, the output transistor is OFF until the strength of the mag- netic field perpendicular to the surface of the chip exceeds the threshold or operate point (BOP). When the field strength exceeds BOP, the output transis- tor switches ON and is capable of sinking 25 mA of current.

TP-105

Vendor:M/A-COM

Active low RESET. Pulled up to VDD with internal resister. Bottom voltage reference level output. An external capacitor (0.1uF20%) should be connected between this pin and VSSA. Top voltage reference level output. An external capacitor (0.1uF20%) should be connected between this pin and VSSA. Ground for the analog part. 0 volts.

TP105-01-02

TP105-32-02RED

TP108A

Package Cooled:06+D/C:800

The next four bytes of the EPROM STATUS memory contain the page address redirection bytes. Bits in the EPROM status bytes can indicate to the host what page is substituted for the page by the appropriate redirection byte. The hardware of the bq2022 makes no decisions based on the contents of the page address redirection bytes. This feature allows the users software to make a data patch to the EPROM by ind...

TP110

Vendor:TOPICPackage Cooled:STKD/C:0611+

Specified Performance High Speed Mode: SCL = 3.4MHz Fast Mode: SCL = 400kHz Standard Mode, SCL = 100kHz High Speed Mode: SCL = 3.4MHz Fast Mode: SCL = 400kHz Standard Mode, SCL = 100kHz High Speed Mode: SCL = 3.4MHz Fast Mode: SCL = 400kHz Standard Mode, SCL = 100kHz SCL Pulled HIGH, SDA Pulled HIGH

TP1-100

Vendor:COPERD/C:08+

The bq2014 measures the voltage differential between the SR and VSS pins. VOS (the offset voltage at the SR pin) is greatly affected by PC board layout. For optimal results, the PC board layout should follow the strict rule of a single-point ground return. Sharing high-current ground with small signal ground causes undesirable noise on the small signal nodes. Additionally:

TP11362AN

Package Cooled:NSD/C:08+/09+

Note All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication however this data sheet cannot be a controlled document Current revisions if any to these specifications are maintained at the factory and are available upon your request We recommend checking the revision level before finalization of your design documentation

TP11368V/NOPB

Vendor:NS 06+

inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V systems and it is ideal for portable applications like personal digital assistant, camcorder and all battery-powered equipment. All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess...

TP115

TP118

D/C:1320

Note) *1: Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25C. *2: When used within the range not exceeding the absolute maximum ratings and the power dissipation. *3: The power dissipation shown is for the independent IC without a heat sink at Ta = 70C.

TP11CGRAO

TP11SH8ABE

Vendor:ITTD/C:07/08+

The MX98715A controller is an IEEE802.3u compliant single chip 32-bit full duplex, 10/100Mbps highly inte- grated Fast Ethernet combo solution, designed to ad- dress high performance local area networking (LAN) system application requirements.

TP11SH8ABE

Vendor:ITTD/C:07/08+

The MX98715A controller is an IEEE802.3u compliant single chip 32-bit full duplex, 10/100Mbps highly inte- grated Fast Ethernet combo solution, designed to ad- dress high performance local area networking (LAN) system application requirements.

TP11SH8AGE

A six byte command (bypass unlock) sequence to remove th e req uirement of ente ring the three byte prog ra m sequence is offered to further improve programming time. After entering the six byte code, only single pulses on the write control lines are required for writing into the device. This mode (single pulse byte/word program) is exited by powering down the device, or by pulsing the RESET pin low f...

TP11SH9ABE

Vendor:ITTD/C:07/08+

• Second Generation SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC DEVICE 3.3V Power Supply User Selectable 3.3V/2.5V I/O 6000 PLD Gates / 128 Macrocells 96 I/O Pins Available 128 Registers High-Speed Global Interconnect SuperWIDE Generic Logic Block (32 Macrocells) for Optimum Performance SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Dec...

TP11SHABE

The internal decoupling capacitors help prevent high frequency instability however normal high frequency layout precautions are still necessary. Coupling capacitors should be physically small and be connected with short leads. It is most important that the ground connections are made with short leads to a continuous ground plane.

TP120H

Vendor:ST8Package Cooled:SOPD/C:06+

pulse one period) on the application of each new trigger pulse. For operation in the non-triggerable mode, Q is connected to CTR when leading-edge triggering (+ TR) is used or Q is connected to + TR when trailing-edge triggering (C TR) is used. The time period (T) for this multivibrator can be approximated by TX = 1/2 RX CX for CX 0.01 µF. Time periods as a function of RX for values of CX and V...

TP1220L

Vendor:silPackage Cooled:silD/C:dc95

Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The contr...

TP1230

Vendor:TOSHIBAPackage Cooled:n/aD/C:08+

TP1241

Package Cooled:SMDD/C:09+

Please read the General Operating Considerations section, which covers stability, supplies, heat-sinking, mounting, cur- rent limit, SOA interpretation, and specification interpretation. Additional information can be found in the application notes. For information on the package outline, heatsink, and mount- ing hardware, consult the Accessories Information and Pack- aging mechanical data section of t...

TP1268MA2

Vendor:TOPROPackage Cooled:SOPD/C:01+

The IS41C4100 and IS41LV4100 is a CMOS DRAM optimized for high-speed bandwidth, low power applica- tions. During READ or WRITE cycles, each bit is uniquely addressed through the 19 address bits. The first ten address bits (A0-A9) are entered as row address and latter nine bits nine address bits (A0-A8) are entered as column address. The row address is latched by the Row Address Strobe (RAS). The colu...

TP127

D/C:90

Fully operational to +1200V Tolerant to negative transient voltage dV/dt immune Gate drive supply range from 12 to 20V Undervoltage lockout for both channels 3.3V logic compatible Separate logic supply range from 3.3V to 20V Logic and power ground 5V offset CMOS Schmitt-triggered inputs with pull-down Cycle by cycle edge-triggered shutdown logic Matched propagation delay for both channels Outputs in...

TP12SH8AQE

Vendor:ITTD/C:07/08+

Programmable 28-bit serial number Programmable 64-bit encryption key Each transmission is unique 66-bit transmission code length 32-bit hopping code 34-bit fixed code (28-bit serial number, 4-bit function code, 2-bit status) • Encryption keys are read protected

TP13054ADW

Vendor:TIPackage Cooled:03+D/C:800

1. Hitachi neither warrants nor grants licenses of any rights of Hitachis or any third partys patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Pr...

TP13054ADW

Vendor:TIPackage Cooled:03+D/C:800

1. Hitachi neither warrants nor grants licenses of any rights of Hitachis or any third partys patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Pr...

TP13054AN

Vendor:TIPackage Cooled:DIP/16

The ISD1000A Series eliminates the need for dig- ital conversion, digital compression, and voice synthesis techniques which often compromise voice quality and are more complicated to use. The ISD1000A Series includes signal conditioning circuits and control functions which enable a com- plete, high-quality Recording and Playback sys- tem in a single device. The ISD1000A is available in two versions, which s...

TP13054AN

Vendor:TI

The ISD1000A Series eliminates the need for dig- ital conversion, digital compression, and voice synthesis techniques which often compromise voice quality and are more complicated to use. The ISD1000A Series includes signal conditioning circuits and control functions which enable a com- plete, high-quality Recording and Playback sys- tem in a single device. The ISD1000A is available in two versions, which s...

TP13054B

Package Cooled:德州

Sets the oscillator frequency and maximum duty cycle Frequency modulation Current sense. Burst level Soft start and hiccup timing, latched disable input. Current comparator for current mode control. Burst mode status Slope compensation Power ground Totem pole output to direct drive a power MOSFET. Supply input voltage. +5V Voltage reference External resistor for internal constant current Latch...

TP13054BDW

Vendor:TIPackage Cooled:SOP16D/C:08+

s 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package. s 8 kB to 40 kB of on-chip static RAM and 32 kB to 512 kB of on-chip flash memory. 128-bit wide interface/accelerator enables high-speed 60 MHz operation. s In-System Programming/In-Application Programming (ISP/IAP) via on-chip boot loader software. Single flash sector or full chip erase in 400 ms and programming of 256 by...

TP13054BDWR

Vendor:TIPackage Cooled:TID/C:06+

During switching, a MOSFETs source voltage must remain fixed, as any variation will modulate the gate and thus adversely affect performance. Figure1 shows this degradation by comparing n-channel and p-channel MOSFET high-side switching.

TP13054BN

Vendor:TIPackage Cooled:DIPD/C:1995

Three of the preamplifiers, A, C and D are capable of delivering typically 30 µA of peak current drive while the fourth pre- amplifier B has 6 dB more current drive capability, allowing a 6 dB greater output into the same load impedance, or the same output level into one half the load impedance.

TP13056BN

TP13057A

Package Cooled:SOP16D/C:2007+

RJC Thermal Resistance (Output Switches)1.5C/W RJC Thermal Resistance (Regulator)9C/W TST Storage Temperature Range-65C to +150C TLD Lead Temperature Range+300C (10 Seconds) TC Case Operating Temperature-55C to +125C TJ Junction Temperature+150C

TP13057A

Package Cooled:SOP16D/C:2007+

RJC Thermal Resistance (Output Switches)1.5C/W RJC Thermal Resistance (Regulator)9C/W TST Storage Temperature Range-65C to +150C TLD Lead Temperature Range+300C (10 Seconds) TC Case Operating Temperature-55C to +125C TJ Junction Temperature+150C

TP13057AB

Package Cooled:SOP16

The third overtone mode is not necessarily at exactly three times the fundamental frequency. The mechanical properties of the quartz element dictate the position of the overtones relative to the fundamental, and in a VCXO circuit, the third overtone is not typically exactly three times the fundamental, or the oscillator circuit may excite both the fundamental and overtone modes simultaneously. This w...

TP13057ADWR

Vendor:TIPackage Cooled:SOP

The Hynix HYM76V4M655HG(L)T6 Series are 4Mx64bits Synchronous DRAM Modules. The modules are composed of four 4Mx16bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin glass-epoxy printed circuit board. Two 0.33uF and one 0.1uF decoupling capacitors per each SDRAM are mounted on the PCB.

TP13057AN

Vendor:TI

The Am29PDL640G is a 64 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device orga- nized as 4 Mwords. The device is offered in 63- or 80-ball Fine-pitch BGA packages. The word-wide data (x16) ap- pears on DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V VPP is not required for write or erase operations.

TP13057BB

Vendor:TIPackage Cooled:SOP16D/C:N/A

Glueless Interface Between the Peripheral Component Interconnect (PCI) Bus and the TI380C2x† and TI380C3x† Generation of Processors Compliant With PCI Specification, Revision 2.0‡ Allows Use of Existing TI2000 Drivers Includes TI2000 Interface Configuration Register Supports Bus Master Operations for High Performance Provides 32-Bit Address-Data Path Implements Address / Data Parity Ch...

TP13057BDW

Vendor:TIPackage Cooled:SOP16

A doubled buffered serial data interface offers high-speed, 3-wire, SPI and microcontroller compat- ible inputs using serial data in (SDI), clock (CLK), and a chip-select (CS). In addition, a serial data out pin (SDO) allows for daisy-chaining when multiple pack- ages are used. A common level-sensitive load DAC strobe (LDAC) input allows simultaneous update of all DAC outputs from previously loaded i...

TP13057BDWR

Vendor:TIPackage Cooled:SOPD/C:98+

Signals are processed in the 4:1:1 format. The vertical-decimation line memory now operates with 208 (formerly 216) pixels per line to adapt the 1/9th picture format to the new picture memory with TV-SAMs. Gray frame generation is similarly affected by this change in pixel value.

TP13057BDWR

Vendor:TIPackage Cooled:SOPD/C:98+

Signals are processed in the 4:1:1 format. The vertical-decimation line memory now operates with 208 (formerly 216) pixels per line to adapt the 1/9th picture format to the new picture memory with TV-SAMs. Gray frame generation is similarly affected by this change in pixel value.

TP13058AN

TP13064ADW

TP13064B

Vendor:NSD/C:05+

Good high frequency PC layout techniques are a must. Traces wide enough for the current delivered, and placement of the big capacitors close to the MSK 4301 are very important. The path for the RSENSE connection through any sense resistor back to the GND pins must be as short as possible. This path is the gate drive current path for all the FETs on the lower half of each phase. A short, low inductance p...

TP13067BN

Vendor:TIPackage Cooled:PDIPD/C:600

TP1319

Vendor:10D/C:N/A

The CY7B993V and CY7B994V High-speed Multi-phase PLL Clock Buffers offer user-selectable control over system clock functions. This multiple-output clock driver provides the system integrator with functions necessary to optimize the timing of high-performance computer and communication systems.

TP1319-01

Vendor:TELEDYEND/C:08+

TP1321

Vendor:TELEDYENE

The PT4474 Excalibur™ DC/DC converter module combines state-of-the- art power conversion technology with un-paralleled flexibility. Incorporating high efficiency and ultra-fast transient response, these modules provide up to 20A of output current over the program- mable voltage range of 4.6V to 5.7V. The modules include a number of inbuilt features to facilitate system integration. These i...

TP132101

Vendor:TELEDYENE

+DUGZDUH GDWD SURWHFWLRQ PHDVXUHV LQFOXGH D ORZ 9&& GHWHFWRU WKDW DXWRPDWLFDOO\ LQKLELWV ZULWH RSHUDWLRQV GXULQJ SRZHU WUDQVLWLRQV 7KH GHYLFH DOVR RIIHUV WZR W\SHV RI GDWD SURWHFWLRQ DW WKH VHFWRU OHYHO :KHQ DW 9,/ :3 ORFNV WKH IRXU RXWHUPRVW ERRW VHFWRUV

TP132101

Vendor:TELEDYENE

+DUGZDUH GDWD SURWHFWLRQ PHDVXUHV LQFOXGH D ORZ 9&& GHWHFWRU WKDW DXWRPDWLFDOO\ LQKLELWV ZULWH RSHUDWLRQV GXULQJ SRZHU WUDQVLWLRQV 7KH GHYLFH DOVR RIIHUV WZR W\SHV RI GDWD SURWHFWLRQ DW WKH VHFWRU OHYHO :KHQ DW 9,/ :3 ORFNV WKH IRXU RXWHUPRVW ERRW VHFWRUV

TP132201

Vendor:120Package Cooled:TCD/C:N/A

The page read operation of the device is controlled by CE and OE inputs. The page size is four words. The first word access of the page read is the same as the asynchronous read. The first word is read at an asynchronous speed of 70 ns. Once the first word is read, toggling A0 and A1 will result in subsequent reads within the page being output at a speed of 20 ns. The Page Read Cycle Waveform is shown on ...

TP132201

Vendor:120D/C:N/A

The page read operation of the device is controlled by CE and OE inputs. The page size is four words. The first word access of the page read is the same as the asynchronous read. The first word is read at an asynchronous speed of 70 ns. Once the first word is read, toggling A0 and A1 will result in subsequent reads within the page being output at a speed of 20 ns. The Page Read Cycle Waveform is shown on ...

TP1322-01

Package Cooled:CAN

TP1322H

TP1323

Vendor:300Package Cooled:CAN8

Stresses in excess of the absolute ratings may cause permanent damage. Functional operation is not implied under these conditions. Exposure to absolute ratings for extended periods of time may adversely affect reliability. Notes: 1. Pins 2, 4, 5 and 7 should be AC-coupled. No external DC bias should be applied. 2. Pin 6 should be AC-grounded and/or pulled to ground through a resistor for current control. ...

TP1332

Package Cooled:CAN8D/C:300

Note 12: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH).

TP1339

Vendor:TELEDYEND/C:06+

TTL/CMOS Compatible Synchronous Enable: When EN goes LOW, Q outputs will go LOW and /Q outputs will go HIGH on the next LOW transition at IN inputs. Input threshold is VCC/2V. A 25kΩ pull-up resistor is included. The default state is HIGH when left floating. The internal latch is clocked on the falling edge of the input signal (IN, /IN).

TP1340

Vendor:MALAYPackage Cooled:CAN8D/C:685

TP1344

Vendor:TELEDYENED/C:08+

Port 3 Port 3 is an 8-bit bidirectional I O port with internal pullups The Port 3 output buffers can drive LS TTL inputs Port 3 pins that have 1s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 3 pins that are externally pulled low will source current (IIL on the data sheet) because of the pullups

TP1346

Vendor:TELEDYNEPackage Cooled:CAN-8D/C:08+

Loading With the rising edge of the Clock, a low level on Load (pin 9) loads the data from the Preset Data input pins (P0, P1, P2, P3) into the internal flipCflops and onto the output pins, Q0 through Q3. The count function is disabled as long as Load is low.

TP1421

Vendor:11D/C:N/A

available. The data applied to the data inputs are transferred to the Q outputs of latches when the strobe input is held high. When the strobe input is taken low, the information data applied to the data input at a time is retained at the output of the latches. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

TP1421

Vendor:11D/C:N/A

available. The data applied to the data inputs are transferred to the Q outputs of latches when the strobe input is held high. When the strobe input is taken low, the information data applied to the data input at a time is retained at the output of the latches. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

TP1424

Vendor:n/aPackage Cooled:TO8D/C:06+

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

TP1426

Vendor:TELEDYENED/C:08+

The ON Semiconductor 74FST3244 is an 8−bit, high performance switch. The device is CMOS TTL compatible when operating between 4 and 5.5 Volts. The device exhibits extremely low RON and adds nearly zero propagation delay. The device adds no noise or ground bounce to the system. The device consists of two 4−bit switches with separate Output/Enable (OE) pins. Port A is connected to Port B whe...

TP1437-83

Vendor:TELEDYNEPackage Cooled:CAN-8Pin 铁帽D/C:8917

Each LIU is composed of transmit and receive interfaces and a jitter attenuator. The transmit interface is responsible for generating the necessary waveshapes for driving the network and providing the correct source impedance depending on the type of media used. T1 waveform generation includes DSX-1 line build-outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. E1 waveform generation ...

TP1-470

Vendor:.D/C:.

Intended applications for these devices include transmission of clock signals from a central clock module, as well as translation and buffering of data or control signals for transmission through a controlled impedance backplane or cable.

TP1501AP

Vendor:TOPROPackage Cooled:4008D/C:64+

THERMAL CONSIDERATIONS Thermal shutdown protection circuitry protects the integrated circuit from thermal overload caused from a rise in junction temperature during excessive power dissipation conditions. This means of protection is intended for fault protection only and not as a means of current or power limiting during normal application usage. Proper thermal evaluation should be done to ensure th...

TP1517

Package Cooled:SOP

Supports 8-bit and 16-bit operation modes Eight 8-bit reload counters Eight 8-bit reload registers for L pulse width Eight 8-bit reload registers for H pulse width A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter 4 output pins Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz (fsy...

TP15914

TP16128T

Vendor:n/aPackage Cooled:QFPD/C:96

A separate 6-bit control register (WCR) independently controls the wiper tap position for each DPP. Associated with each wiper control register are four 6-bit non- volatile memory data registers (DR) used for storing up to four wiper settings. Writing to the wiper control register or any of the non-volatile data registers is via a 2-wire serial bus (I2C-like). On power-up, the contents of the

TP1C6C595

Vendor:TIPackage Cooled:SOP16SD/C:2007+

TP2-.002-5

TP2000

Vendor:TenpinD/C:07+

• Global 3-bit analog control applies to all LED outputs. PWM timing of the 10 port outputs may be optionally staggered, consecutively phased in 45 increments. This spreads the PWM load currents over time in eight steps, helping to even out the power-supply current and reduce the RMS current. The TP2000/TP2000 can be configured to awake from shutdown on receipt of a minimum 3ms pulse on the CS input. ...

TP2000

Vendor:TenpinD/C:07+

• Global 3-bit analog control applies to all LED outputs. PWM timing of the 10 port outputs may be optionally staggered, consecutively phased in 45 increments. This spreads the PWM load currents over time in eight steps, helping to even out the power-supply current and reduce the RMS current. The TP2000/TP2000 can be configured to awake from shutdown on receipt of a minimum 3ms pulse on the CS input. ...

TP2003

Package Cooled:CAN12

The LT®3468/TP2003-1 are highly integrated ICs designed to charge photoflash capacitors in digital and film cam- eras. A new control technique* allows for the use of extremely small transformers. Each device contains an on-chip high voltage NPN power switch. Output voltage detection* is completely contained within the device, eliminating the need for any discrete zener diodes or resistors. The output vol...

TP2003

Package Cooled:CAN12

The LT®3468/TP2003-1 are highly integrated ICs designed to charge photoflash capacitors in digital and film cam- eras. A new control technique* allows for the use of extremely small transformers. Each device contains an on-chip high voltage NPN power switch. Output voltage detection* is completely contained within the device, eliminating the need for any discrete zener diodes or resistors. The output vol...

TP2020L

Vendor:SIPackage Cooled:TO-92D/C:99+

Figure 4 shows the sensor output signal relative to pres- sure input. Typical minimum and maximum output curves are shown for operation over a temperature range of 0 to 85C using the decoupling circuit shown in Figure 3. The output will saturate outside of the specified pressure range. A gel die coat isolates the die surface and wire bonds from the environment, while allowing the pressure signal

TP2020L-TR1

Vendor:SILICONIXD/C:圆轮TO92

TP2032

Vendor:MOT

TP2033

Vendor:MOTOROLA

Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed speci- fications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance character- istics may degrade when the device is not operated under the listed test condit...

TP2037

Vendor:MOT

Digital data output pins that make up the 12-bit conversion results of their respective converters. DA0 and DB0 are the LSBs, while DA11 and DB11 are the MSBs of the output word. Output levels are TTL/CMOS compatible. Optimum loading is < 10pF.

TP2050

Vendor:TRIPATHPackage Cooled:N/AD/C:2000

TP205013TR-1C

Vendor:STPackage Cooled:STD/C:00+

See the functional block diagram and Figure 1 for this discussion. Using the Spreetat sensor to measure the refractive index of a liquid requires the proper application of signals to the pins. See Figure 1 for a diagram of the measurement cycle. A pulse is applied to the START pin. On the subsequent positive edge of the CLOCK, the start pulse is clocked into the internal shift register initiating a reset ...

TP205013TR-1C

Vendor:STPackage Cooled:STD/C:00+

See the functional block diagram and Figure 1 for this discussion. Using the Spreetat sensor to measure the refractive index of a liquid requires the proper application of signals to the pins. See Figure 1 for a diagram of the measurement cycle. A pulse is applied to the START pin. On the subsequent positive edge of the CLOCK, the start pulse is clocked into the internal shift register initiating a reset ...

TP2050TR

Vendor:SSOPPackage Cooled:453D/C:00+

HY57V561620A is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro- nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

TP2104K1

Vendor:SOT-23Package Cooled:SOT-23D/C:1100

All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. The data was taken at CL = 15 pF, RL = 2 kΩ (see Figure 1). The data was taken at CL = 30 pF, RL = 500 Ω (see Figure 1).

TP2104K1-G

TP2104K1-T1-E3

Vendor:VISHAYPackage Cooled:SOT-23D/C:07+（ROHS）

TP2105K1/P1LB

Vendor:SUPERTEXD/C:08+

Test mode (open or VSS) Test mode (LSB) (open or VSS) Internal digital use Digital use Test input VSS) Test input VSS) Test input open or VSS) Digital I/O (3.3 V) use DRAM test input (open or VSS) DRAM test input (open or VSS) Digital use DRAM (5 Mbits) use DRAM test input (open or VSS) Digital use Internal digital use 27-MHz clock for Rec 656 input (VSS when not used) Digital use Digi...

TP21SHZBE

TON (line voltage control): TON serves three functions. When CT is discharging (off time), the current through TON is routed to VCC. When CT is charging (on time), the current through TON is split 80% to set the CT charge time and 20% to sense minimum line voltage which oc- curs for a TON current of 220µA. For a minimum line volt- age of 80V, RON is 330kΩ.

TP2212WM

TP2249AL

Vendor:DIPPackage Cooled:DIPD/C:NS

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

TP2252

Package Cooled:5028D/C:DIP

TP2268P8

D/C:99

FEATURES High breakdown voltage (BVCEO 50V) High-current driving (Io(max) = C500mA) With output clamping diodes Driving available with CMOS IC output of 6-16V or with TTL output Wide operating temperature range (Ta = C20 to +75C) Output current-sourcing type

TP2272-L4

Vendor:STPackage Cooled:DIPD/C:1993

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

TP2300

Vendor:MOT

• Industry Standard Size • Industry Standard Pinout 15.24 mm (0.6 in.) DIP Leads on 2.54 mm (0.1 in.) Centers • Choice of Colors AlGaAs Red, High Efficiency Red, Yellow, Green • Excellent Appearance Evenly Lighted Segments Mitered Corners on Segments Gray Package Gives Optimum Contrast 50 Viewing Angle • Design Flexibility Common Anode or Common Cathod...

TP2307

Vendor:MOT