UPB584GE1

Vendor:NECPackage Cooled:2029D/C:01+

The Philips microcontrollers described in this data sheet are high-performance static 80C51 designs. They are manufactured in an advanced CMOS process and contain a non-volatile Flash program memory that is programmable in parallel (via a parallel programmer) or In-System Programmable (ISP) via boot loader. They support both 12-clock and 6-clock operation.

UPB585

Vendor:NECPackage Cooled:SOP8

32KB EEPROM memory Durable, stainless-steel iButton package Built-in multi-drop controller ensures compatibility with other Dallas Semiconductor 1-Wire net products Unique factory lasered 64-bit registration number assures error free device selection and absolute part identity Supports Overdrive mode Operating range: 2.8V to 5.25V, -40 to +85C

UPB585G

Vendor:NECPackage Cooled:N/AD/C:1993

Two-level OCP with 96mS delay time Peak-current-mode operation with cycle-by-cycle current limiting PWM frequency continuously decreasing w/ burst mode at light loads Low start-up current (8uA) Low operating current (3.7mA) VDD over-voltage protection (OVP) AC input brownout protection with hysteresis Programmable over-temperature protection (OTP) Constant power limit over universal AC input ra...

UPB585G

Vendor:NECPackage Cooled:N/AD/C:1993

Two-level OCP with 96mS delay time Peak-current-mode operation with cycle-by-cycle current limiting PWM frequency continuously decreasing w/ burst mode at light loads Low start-up current (8uA) Low operating current (3.7mA) VDD over-voltage protection (OVP) AC input brownout protection with hysteresis Programmable over-temperature protection (OTP) Constant power limit over universal AC input ra...

UPB585G-E1

Vendor:NECPackage Cooled:N/AD/C:1998

Read. A low on this input informs the 73K322L that data or status information is being read by the processor. The falling edge of the RD signal will initiate a read from the addressed register. The RD signal must continue for eight falling edges of EXCLK in order to read all eight bits of the referenced register. Read data is provided LSB first. Data will not be output unless the RD signal is active.

UPB585G-E2

Vendor:-Package Cooled:SOPD/C:-

Calibration Delay, Dual Edge Sampling and Serial Interface Chip Select. With a logic high or low on pin 14, this pin functions as Calibration Delay and sets the number of input clock cycles after power up before calibration begins (See Section 1.1.1). With pin 14 floating, this pin acts as the enable pin for the serial interface input and the CalDly value becomes "0" (short delay with no prov...

UPB585G-T1

Package Cooled:SOP

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Due to the low dissipated pow...

UPB586G-E1

Vendor:NECPackage Cooled:326D/C:01+

3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.

UPB587

Vendor:NECPackage Cooled:SOP/8D/C:354

UPB587C

Vendor:NECPackage Cooled:1800

UPB587G

Vendor:NECD/C:08+

Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing and are measured at VCC = 12 V unless otherwise noted.

UPB597CX

Pin 8 is the drive control input. This pin accepts a DC voltage to control overall gain. Pin 8 is internally decoupled to ground with a 0.1uF capacitor. With 0V at pin 8, the gain is minimum (-6dB). With 4V at pin 8, the gain is maximum (0dB). Drive control is approximated by the following formula:

UPB601B-A

Vendor:NECD/C:07+

QtyDescription Resistors 610KΩ, 5% 1/4W, leaded 11KΩ, 5% 1/4W, leaded 2135Ω, 5% 1/4W, leaded 230KΩ, 5% 1/4W, leaded Capacitors 51µF, 16V, electrolytic, leaded 11µF, 50V, ceramic, leaded 20.22µF, 16V, ceramic, leaded 22.2nF, 16V, ceramic, leaded 110µF, 50V, electrolytic, leaded 41µF, 50V, ceramic, leaded 2100pF, 50V, ceramic, leaded Semiconductors ...

UPB601B-S X

UPB603B-S

Vendor:NEC

INTERFACE COMMUNICATION: The IC pin determines which interface is operational. If the IC pin is held high, then the A/A Mux interface is enabled, and if the IC pin is held low, then the FWH/LPC interface is enabled. The IC pin must be set at power-up or before returning from a reset condition and cannot be changed during device operation. The IC pin is internally pulled-down with a resistor valued between...

UPB606B

A resistor can be added from the RESET pin to ground to ensure the RESET output remains low with VCC down to 0V. A 100kΩ resistor connected from RESET to ground is recommended. The size of the resistor should be large enough to not load the RESET output and small enough to pull-down any stray leakage currents.

UPB606B-S

Vendor:NECD/C:07+

• Low leakage, low zener impedance and maximum power dissipation of 400 mW are ideally suited for stabilized power supply, etc. • Wide spectrum from 1.88 V through 38.52 V of zener voltage provide flexible application. • Suitable for 5mm-pitch high speed automatic insertion.

UPB6101C-002

Vendor:NECPackage Cooled:97+D/C:97+

Cycle-by-cycle current limiting, soft start, under-voltage lock-out with hysteresis, over-voltage protection, and thermal shutdown protect the devices during all normal and overload conditions. Over-voltage protection, thermal shutdown, or an external fault signal are latched. The dual requirements of dielectric isolation and low transient thermal impedance and steady-state thermal resistance are satisf...

UPB6101C036

Vendor:NECPackage Cooled:90+D/C:DIP

FB is an input terminal used for the adjustable-output option and must be connected to the output terminal either directly, in order to generate the minimum output voltage of 1.22 V, or through an external feedback resistor divider for other output voltages. The FB connection should be as short as possible. It is essential to route it in such a way to minimize/avoid noise pickup. Adding RC networks betwee...

UPB6101C102

Vendor:NECPackage Cooled:DIP-16D/C:9328

The ISP1109 is a Universal Serial Bus (USB) transceiver device that supports CEA−936−A, Mini-USB Analog Carkit Interface. It is fully compliant with Universal Serial Bus Specification Rev. 2.0. The ISP1109 can transmit and receive serial data at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) data rates.

UPB6101C-108

Vendor:NECPackage Cooled:DIP/20D/C:100

The ISSI IS62LV5128LL is a low voltage, 524,288 words by 8 bits, CMOS SRAM. It is fabricated using ISSIs low voltage, six transistor (6T), CMOS technology. The device is targeted to satisfy the demands of the state-of-the-art technologies such as cell phones and pagers.

UPB6101C-108

Vendor:NECPackage Cooled:95+D/C:95+

The ISSI IS62LV5128LL is a low voltage, 524,288 words by 8 bits, CMOS SRAM. It is fabricated using ISSIs low voltage, six transistor (6T), CMOS technology. The device is targeted to satisfy the demands of the state-of-the-art technologies such as cell phones and pagers.

UPB6101C120

Vendor:NECD/C:92/93+

The OPA725 and OPA726 series op amps use a state-of-the-art 12V analog CMOS process, and combine outstanding ac performance with low bias current and excellent CMRR, PSRR, and AOL. The 20MHz Gain-Bandwidth (GBW) Product is achieved by using a proprietary and patent-pending output stage design. These characteristics allow excellent 16-bit settling times for driving 16-bit Analog-to-Digital converters ...

UPB6102C063

D/C:86

The purpose of this paper is to define the terms relating to aperture effects, to develop a mathematical framework to represent these effects, and to predict the errors that will be introduced into the sampled signal as a result of aperture effects.

UPB6102C066

Vendor:NSECD/C:87

The MCU provides the following features: 40K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 2K byte SRAM, 32 general purpose working registers, 18 general purpose I/O lines, 11 high-voltage I/O lines, a JTAG Interface for On-chip Debugging support and programming, two flexible Timer/Counters with PWM and compare modes, one Wake-up Timer, an SM-Bus compliant TWI...

UPB6102C066

Vendor:NSECD/C:87

The MCU provides the following features: 40K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 2K byte SRAM, 32 general purpose working registers, 18 general purpose I/O lines, 11 high-voltage I/O lines, a JTAG Interface for On-chip Debugging support and programming, two flexible Timer/Counters with PWM and compare modes, one Wake-up Timer, an SM-Bus compliant TWI...

UPB6102C-146

Vendor:NECPackage Cooled:DIPD/C:1997

Te xas Instrume nts and its subsidiarie s (TI) re se rve the right to make change s to the ir products or to discontinue any product or se rvice without notice , and advise custome rs to obtain the late st ve rsion of re le vant information to ve rify, be fore placing orde rs, that information be ing re lie d on is curre nt and comple te . All products are sold subje ct to the te rms and conditions of sal...

UPB6103C-012

Vendor:NECPackage Cooled:DIPD/C:91

The FOD2741 Optically Isolated Amplifier consists of the popular KA431 precision programmable shunt reference and an optocoupler. The optocoupler is a gallium arsenide (GaAs) light emitting diode optically coupled to a silicon phototransistor. It comes in 3 grades of reference voltage tolerance = 2%, 1%, and 0.5%.

UPB63020E45

Vendor:NECPackage Cooled:06+D/C:3000

UPB63020RK-E07-93

Vendor:NECPackage Cooled:PGAD/C:08+

The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum All unused digital inputs of the device must be held at V+ or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

UPB63020SK-E48-83

Vendor:NECPackage Cooled:FPGA D/C:2001

n Software selectable I/O options (TRI-STATE ® Output,Push-Pull Output, Weak Pull-Up Input, and High Impedance Input) n Schmitt trigger inputs on ports G and L n Eight high current outputs n Packages: 28 SO with 24 I/O pins, 40 DIP with 36 I/O pins, 44 PLCC, PQFP and CSP with 40 I/O pins

UPB6302B-044

Vendor:NECPackage Cooled:QFPD/C:08+

• Comparators, counters, latches, and drivers minimize logic requirements for a variety of multiplexed and non-multiplexed buses • Directly drives VMEbus address and data signals • 8-bit comparator for slave address decoding • Flexible interface optimized for VMEbus applications • Companion device to Cypress VMEbus family of com- ponents • Replaces multiple SSI/MSI co...

UPB6302B-066

The IRU1050 is a low dropout three-terminal adjustable regulator with minimum of 5A output current capability. This product is specifically designed to provide well regu- lated supply for low voltage IC applications such as Pentium™ P54C™ ,P55C™ as well as GTL+ termination for Pentium Pro™ and Klamath™ processor applications. The IRU1050 is also well suited for other processors ...

UPB6302B074

Vendor:NSECD/C:88

custom reference designator identifying the intended frequency and duty cycle of operation. The programmed delay accuracy of the device is guaranteed, therefore, only for the user specified input characteristics. Small input pulse width variation about the selected pulse width will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering ...

UPB6302B-078

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Maximum po...

UPB6311R-050

Vendor:NECPackage Cooled:8929D/C:8929

Now we can examine the value of < f, ( C ä) >. < f, ä > is by definition f(t0) and the other terms of the expansion do not contribute to the result. Since Ø has been normalized, < f(t0), > is f(t0): the ideal result of the sampling event. If we consider the next term: f'(t0) (t-t0) this is a constant

UPB6311R-050

Vendor:NECD/C:8929

Now we can examine the value of < f, ( C ä) >. < f, ä > is by definition f(t0) and the other terms of the expansion do not contribute to the result. Since Ø has been normalized, < f(t0), > is f(t0): the ideal result of the sampling event. If we consider the next term: f'(t0) (t-t0) this is a constant

UPB638

Vendor:NSECD/C:95

The NL17SZ07 is a high performance single inverter with open drain outputs operating from a 1.65 to 5.5 V supply. The Output stage is open drain with Over Voltage Tolerance. This allows the NL17SZ07 to be used to interface 5.0 V circuits to circuits of any voltage between 0 and +7.0 V.

UPB63802BS-020-KAL

Vendor:NECPackage Cooled:QFP/金D/C:2001+

UPB638B-A

Vendor:NECD/C:07+

The KBE00S009M is a Multi Chip Package Memory which combines 2Gbit Nand Flash Memory(organized with two pieces of 1G bit Nand Flash Memory) and 512Mbit synchronous high data rate Dynamic RAM.(organized with two pieces of 256Mbit Mobile SDRAM) 2Gbit NAND Flash memory is organized as 256M x8 bits and 512Mbit SDRAM is organized as 4M x32 bits x4 banks. In 2Gbit NAND Flash, its NAND cell provides the most cost-ef...

UPB661B

Vendor:NECD/C:1129

The THNCFxxxMBA/BAI series CompactFlash™ card is a flash technology based with ATA interface flash memory card. It is constructed with flash disk controller chip and NAND-type Toshiba flash memory device. The CompactFlash™ card operates in both 5-Volt and 3.3-Volt power supplies. It comes in capacity of 8, 16, 32, 48, 64, 96, 128, 160, 192, 256, 320, 384 and up to 512 MB unformatted for type-I c...

UPB685

Vendor:NSECD/C:94

Setting the transceiver to SIR/MIR Mode (9.6 kb/s to 1.152 Mbit/s) 1. Set SD/Mode input to logic HIGH 2. TXD input should remain at logic LOW 3. After waiting for tS 25 ns, set SD/Mode to logic LOW, the HIGH to LOW negative edge transition will determine the receiver bandwidth 4. Ensure that TXD input remains low for tH 100 ns, the receiver is now in SIR/MIR mode 5. SD input pulse w...

UPB687B

Vendor:NECPackage Cooled:2000D/C:8713+

The Fairchild Switch FST16211 provides 24-bits of high- speed CMOS TTL-compatible bus switching. The low On Resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise.

UPB6920BA

Vendor:NECPackage Cooled:QFPD/C:1999+

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

UPB6920BA

Vendor:NECPackage Cooled:QFPD/C:1999+

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

UPB6920BA04

Vendor:NECPackage Cooled:QFPD/C:1999+

The UPB6920BA04s wide ranging capabilities make it the ideal choice for application areas such as stand-alone hub boxes ( self or bus powered ) with value added functions such as Ir multi-media wireless remote and game-pad controllers, USB monitor-hubs with extended Ir capabilities, USB keyboard hubs etc. The UPB6920BA04 uses 3.3 volt process technology which lowers power consumption and reduces electric...

UPB6920BA04

Vendor:NECPackage Cooled:QFPD/C:1999+

The UPB6920BA04s wide ranging capabilities make it the ideal choice for application areas such as stand-alone hub boxes ( self or bus powered ) with value added functions such as Ir multi-media wireless remote and game-pad controllers, USB monitor-hubs with extended Ir capabilities, USB keyboard hubs etc. The UPB6920BA04 uses 3.3 volt process technology which lowers power consumption and reduces electric...

UPB7400C

Vendor:NECPackage Cooled:N/AD/C:82+

Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, tw...

UPB7400C

Vendor:NECPackage Cooled:N/AD/C:82+

Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, tw...

UPB7404C

Vendor:NEC

All instructions (Table 1), addresses and data are transferred MSB first. Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off.

UPB74147C

UPB74154C

UPB7420

The HIP6601 and HIP6603 are high frequency, dual MOSFET drivers specifically designed to drive two power N-Channel MOSFETs in a synchronous-rectified buck converter topology. These drivers combined with a HIP630x Multi-Phase Buck PWM controller and Intersil UltraFETs™ form a complete core-voltage regulator solution for advanced microprocessors.

UPB7460C

30ms Pulse, Vin-Vo=3V, Io=1.5A f=120Hz, Co=25µF Tantalum, Io=0.75A, Vin-Vo=3V Io=10mA, Vin-Vo=1.5V, Tj=25!C, Io=10mA, Vin-Vo=1.5V Io=10mA, Vin-Vo=1.5V, Tj=25!C Vin=3.3V, Vadj=0V, Io=10mA Tj=125!C, 1000Hrs Tj=25!C, 10Hz<f<10KHz

UPB74HC20C

Vendor:N/APackage Cooled:DIPD/C:06+

A burst write access to an active row is initiated with the WRITE command. BA0, BA1 inputs selects the bank, and the starting column location is provided by inputs A0-A7. Whether or not AUTO-PRECHARGE is used is deter- mined by A10. The row being accessed will be precharged at the end of the WRITE burst, if AUTO PRECHARGE is selected. If AUTO PRECHARGE is not selected, the row will remain open for ...

UPB74HC20C

Vendor:N/APackage Cooled:DIPD/C:06+

A burst write access to an active row is initiated with the WRITE command. BA0, BA1 inputs selects the bank, and the starting column location is provided by inputs A0-A7. Whether or not AUTO-PRECHARGE is used is deter- mined by A10. The row being accessed will be precharged at the end of the WRITE burst, if AUTO PRECHARGE is selected. If AUTO PRECHARGE is not selected, the row will remain open for ...

UPB74HC4078GS

Vendor:NECPackage Cooled:SOP

The MC10/100EP451 is a 6−bit fully differential register with common clock and single−ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have a 75 kW pulldown resistor internally. Differential inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differe...

UPB74HC640C

Vendor:NECPackage Cooled:180

3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +85C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table capability in Program Memory Data Storage in Program Memory: User selectable size Data RAM: 128 bytes Data EEPROM: 128 bytes User Programmable Options 20 I/O pins, fully programmable as: C Input with pull-up resistor C Input wi...

UPB74LS00B

Vendor:NECPackage Cooled:DIPD/C:98

Note 6: All limits are guaranteed. All electrical characteristics having room temperature limits are tested during production with TA = 25˚C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

UPB74LS02C

Vendor:NECPackage Cooled:880

7. Series resistance of the resonator (ceramic resonator or crystal) should be minimized to the extent possible. In cases where the resonator series resistance is too great, the oscillator may oscillate at a diminished peak-to-peak level, or may fail to oscillate entirely. Micrel recommends that series resistances for ceramic resonators and crystals not exceed 50Ω and 100Ω, respectively.

UPB74LS02C

Vendor:NECPackage Cooled:880

7. Series resistance of the resonator (ceramic resonator or crystal) should be minimized to the extent possible. In cases where the resonator series resistance is too great, the oscillator may oscillate at a diminished peak-to-peak level, or may fail to oscillate entirely. Micrel recommends that series resistances for ceramic resonators and crystals not exceed 50Ω and 100Ω, respectively.

UPB74LS02D-T

Vendor:NECPackage Cooled:DIPD/C:98

The UPB74LS02D-T on the other hand, employs the KEELOQ code hopping technology coupled with a transmission length of 66 bits to virtually eliminate the use of code grabbing or code scanning. The high security level of the UPB74LS02D-T is based on the patented KEELOQ technol- ogy. A block cipher based on a block length of 32 bits and a key length of 64 bits is used. The algorithm obscures the informat...

UPB74LS02N

Vendor:NECPackage Cooled:DIP14

UPB74LS03C

Vendor:NECPackage Cooled:1400D/C:01+

n Fully integrated 10 Mbps Ethernet transceiver Comprehensive Auto-Negotiation implementation IEEE 802.3u-compliant MII Full-duplex operation supported on the MII port with independent Transmit (TX) and Receive (RX) channels Optimized for 10BASE-T applications n Compliant with HomePNA specification 1.1 n General Purpose Serial Interface (GPSI)/Serial Peripheral Interface (SPI) n Extensi...

UPB74LS04C

Vendor:NECPackage Cooled:DIP14

• Register FileEach Compute Block has a multiported 32- word, fully orthogonal register file used for transferring data between the computation units and data buses and for storing intermediate results. Instructions can access the registers in the register file individually (word-aligned), in sets of two (dual-aligned), or in sets of four (quad-aligned).

UPB74LS04D

Vendor:NECPackage Cooled:NECD/C:95+

Writing a value to a DAC can either be a write to the DAC register only or a combined write to both the DAC Register and its nonvolatile register. They are identical with the one exception being the register write does not entail issuing a stop condition; whereas, the nonvolatile write operation is concluded with a stop. The sequence is to issue a start, followed by the device type and bus address, with the...

UPB74LS05C

Vendor:NECPackage Cooled:DIP14D/C:2200

Note 1 These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO Specd tC1R tC1F and CKI duty cycle limits are not tested but are guaranteed functional by design Keep in mind that when SLOW mode is selected fC (Operating Frequency) will be the external frequency divided by 4 and that value should be used in all formulas relating to the...

UPB74LS05D

Vendor:NECPackage Cooled:DIP/14/磁D/C:90+

* The products contained herein may also be controlled under the U.S. Export Administration Regulations and/or subject to the approval of the U.S. Department of Commerce or U.S. Department of State prior to export. Any export or re-export, directly or indirectly in contravention of any of the applicable export laws and regulations, is hereby prohibited.

UPB74LS08D-T

Vendor:NECPackage Cooled:DIPD/C:1987

Between sensitivity and overload, all AC specifications are met. Guaranteed by design and characterization. The deterministic jitter caused by the filter is not included in the DJ generation specification. Random jitter was measured without using a filter at the input. The supply current measurement excludes the CML output currents by connecting the CML outputs to a separate VCC. (See Figure 1.) Hysteresis ...

UPB74LS107C

Vendor:DIPPackage Cooled:888D/C:NEC

Lead Temperature 1.6mm (1/16 inch) from Case for 10s260C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended peri...

UPB74LS10C

Vendor:NECPackage Cooled:DIP14D/C:1200

1. Solder the copper pad on the backside of the device package to the ground plane. 2. Use a large ground pad area with many plated through-holes as shown. 3. We recommend 1 or 2 ounce copper. Measurement for this data sheet were made on a 31 mil thick FR-4 board with 1 ounce copper on both sides.

UPB74LS10D

Vendor:NECPackage Cooled:CDIP/14D/C:87/88/

The fourth, transient power due to switching current, is caused by the fact that whenever a CMOS device goes through a transition, with VCC 2 VT, there is a time when both N-channel and P-channel devices are both conducting. An expression for this current is derived in Application Note AN-77. The expression is:

UPB74LS10D-T

Vendor:NECPackage Cooled:全新/陶瓷/DIPD/C:90+

Addresses and data needed for the programming and erase operations are internally latched during write cycles, and the host system can detect completion of a program or erase operation by observing the RY/BY# pin, or by reading the DQ[7] (Data# Polling) and DQ[6] (toggle) status bits. Reading data from the device is similar to reading from SRAM or EPROM devices. Hardware data protection measures in...

UPB74LS10D-T

Vendor:NECPackage Cooled:全新/陶瓷/DIP

Addresses and data needed for the programming and erase operations are internally latched during write cycles, and the host system can detect completion of a program or erase operation by observing the RY/BY# pin, or by reading the DQ[7] (Data# Polling) and DQ[6] (toggle) status bits. Reading data from the device is similar to reading from SRAM or EPROM devices. Hardware data protection measures in...

UPB74LS113C

Vendor:NECPackage Cooled:281D/C:01+

The CS8920A has a direct ISA-bus interface with full 24 mA drive capability. The CS8920A operates in either 24-bit memory space, 16-bit I/O space, or with external DMA controllers (three 16-bit channels), providing maximum de- sign flexibility.

UPB74LS11C

Vendor:NECPackage Cooled:82+D/C:DIP

The SOA curves combine the effect of all limits for this Power Op Amp. For a given application, the direction and magnitude of the output current should be calculated or measured and checked against the SOA curves. This is simple for resistive loads but more complex for reactive and EMF generating loads. The following guidelines may save extensive analytical efforts.

UPB74LS11D

Vendor:NECPackage Cooled:DIP/14D/C:1988

Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) This parameter is sampled but not 100% tested. (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.

UPB74LS123D

Vendor:N/APackage Cooled:N/AD/C:08+09+

Stop Condition. STOPis identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition termi- nates communication between the ST24/25E64 and the bus master. A STOP condition at the end of a Read command forces the standby state. A

UPB74LS123D

Vendor:N/APackage Cooled:N/AD/C:08+09+

Stop Condition. STOPis identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition termi- nates communication between the ST24/25E64 and the bus master. A STOP condition at the end of a Read command forces the standby state. A

UPB74LS125C

Vendor:NECPackage Cooled:400D/C:01+

Zener Voltage Range − 3.3 V to 200 V ESD Rating of Class 3 (>16 kV) per Human Body Model Surge Rating of up to 180 W @ 8.3 ms Maximum Limits Guaranteed on up to Six Electrical Parameters These devices are manufactured with a Pb−Free external lead finish only*

UPB74LS125C

Vendor:NECPackage Cooled:400

Zener Voltage Range − 3.3 V to 200 V ESD Rating of Class 3 (>16 kV) per Human Body Model Surge Rating of up to 180 W @ 8.3 ms Maximum Limits Guaranteed on up to Six Electrical Parameters These devices are manufactured with a Pb−Free external lead finish only*

UPB74LS126C

Vendor:NECPackage Cooled:1150

Recordings are stored into on-chip nonvolatile memory cells, providing zero-power message storage. This unique, single-chip solution is made possible through Winbonds patented multilevel storage technology. Voice and audio signals are stored directly into solid-state memory in their natural, uncompressed form, providing superior quality voice and music reproduction.

UPB74LS132C

Vendor:NECPackage Cooled:DIP

Description The HSDL-3612 is a low-profile infrared transceiver module that provides interface between logic and IR signals for through-air, serial, half-duplex IR data link. The module is compliant to IrDA Data Physical Layer Specifications 1.4 and IEC825-Class 1 Eye Safe.

UPB74LS139C

Vendor:NECPackage Cooled:838

The MPC860 Quad Integrated Communications Controller (PowerQUICC™) is a versatile one-chip integrated microprocessor and peripheral combination designed for a variety of controller applications. It particularly excels in both communications and networking systems. The PowerQUICC unit is referred to as the MPC860 in this manual.

UPB74LS14C

Vendor:NECPackage Cooled:DIP14D/C:2007+

UPB74LS151D-T

Vendor:NECPackage Cooled:全新/陶瓷/DIPD/C:88+

In the above figure, the transmitter should be set so that the output V out can be 40mV PP . However, the PD49PI to be used here should be of the short-circuit current I SC = 2.6 µ A at E V = 100 lx. (E V is an illuminance by CIE standard light source A ( tungsten lamp ) . )

UPB74LS153C

Vendor:NECPackage Cooled:DIP16D/C:2007+

Caution: A low DC resistance ground may not be a good ground. Lightning contains a broad spectrum of frequencies up to 1 MHz. A low impedance path to ground at the transient frequencies is necessary. A ground strap is recommended or a #6 AWG stranded wire. For wire lengths over 1.5 meters, there may be some excessive line to earth potential under severe thunderstorm conditions.

UPB74LS153DT

Vendor:NECPackage Cooled:350

UPB74LS153N

Vendor:NECPackage Cooled:.D/C:10

where R15 should be greater than 33 kΩ. Smaller values for C13 will reduce the sensitivity to RF input pulses. The MOSFET turns ON within approxi- mately 1.5 µs (shunting the RF signal to ground) after a noise pulse is detected and then turns OFF over a 15 µs period after the end of the RF gate time. The ON resistance of the MOSFET is about 30 Ω. The slow turn-OFF prevents any add...

UPB74LS153N

Vendor:NECPackage Cooled:.D/C:10

where R15 should be greater than 33 kΩ. Smaller values for C13 will reduce the sensitivity to RF input pulses. The MOSFET turns ON within approxi- mately 1.5 µs (shunting the RF signal to ground) after a noise pulse is detected and then turns OFF over a 15 µs period after the end of the RF gate time. The ON resistance of the MOSFET is about 30 Ω. The slow turn-OFF prevents any add...

UPB74LS157C

D/C:84

REGISTERED In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMCs D-type flip-flop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an in- dividual product-term for each OLMC, and can therefore be defi...

UPB74LS157C

Package Cooled:DIPD/C:84

REGISTERED In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMCs D-type flip-flop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an in- dividual product-term for each OLMC, and can therefore be defi...

UPB74LS157D

Edition 03.98 Published by Siemens AG, HL SP, Balanstraße 73, 81541 Mnchen © Siemens AG 1998. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall no...

UPB74LS158C

Vendor:NECPackage Cooled:274D/C:01+

♦ 72dB ACLR at fOUT = 61.44MHz (Single-Carrier WCDMA) ♦ Meets 3G UMTS, cdma2000®, GSM Spectral Masks (fOUT = 122MHz) ♦ Noise Spectral Density = -151dBFS/Hz at fOUT = 16MHz ♦ 90dBc SFDR at Low-IF Frequency (10MHz) ♦ 86dBc SFDR at High-IF Frequency (50MHz)

UPB74LS15C

Vendor:NECPackage Cooled:DIPD/C:07/08+

3.1 POWER SUPPLY & VOLTAGE REFERENCE The internal regulator circuit (shown in Figure 2) consists of a start-up circuit, an internal voltage Prereg- ulator, the Bandgap voltage reference and the Bias block that provides current to all the blocks.

UPB74LS161C

Vendor:NEC

External Load Capacitance Output Current (At IO < IO, min, the modules may exceed output ripple specifications, but operation is guaran- teed. For A, and G codes, the output voltage may exceed specifications when IO < IO, min.) Output Current-limit Inception (VO = 90% VO, set) Output Short-circuit Current (VO = 0.25 V at 25 C)

UPB74LS163C

Package Cooled:DIPD/C:800

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to desi...

UPB74LS163C

Package Cooled:87D/C:800

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to desi...

UPB74LS164D

Vendor:NECPackage Cooled:350

• Low-power CMOS technology: - Maximum write current 3 mA at 5.5V - Maximum read current 400 µA at 5.5V - Standby current 100 nA typical at 5.5V • 2-wire serial interface bus, I2C™ compatible • Cascadable for up to eight devices • Self-timed erase/write cycle • 64-byte Page Write mode available • 5 ms max write cycle time • Hardware write-prot...

UPB74LS174C

Vendor:NECPackage Cooled:DIPD/C:60

When used as a decimating post-filter with a double speed oversampling analog-digital converter, the device greatly reduces the cost and complexity of the associated analog anti-aliasing pre-filter. In a similar fashion, when used as an interpolating pre-filter with a double speed oversampling digital- analog converter, the GF9102A simplifies the analog reconstruction post-filter. The GF9102A also exceeds the...