UPC1013C

- 23-bit program memory space and 23-bit data memory space - linear program and data address range expanded to sup- port up to 8 Mbytes each - Program counter expanded to 23 bits - Stack pointer extended to 16 bits enabling stack space beyond the 80C51 limitation - New 23-bit extended data pointer and two 24-bit universal pointers greatly improve C compiler code efficiency in using pointers to acc...

UPC10182

Vendor:NECPackage Cooled:DIPD/C:2500

Each of the off-chip memory spaces of the ADSP-21991 has a separate control register, so applications can configure unique access parameters for each space. The access parameters include read and write wait counts, wait state completion mode, I/O clock divide ratio, write hold time extension, strobe polarity, and data bus width. The core clock and peripheral clock ratios influence the external memory ac...

UPC1020

This module generates a slow System Clock (32.768 kHz) from an optional external crystal network. The Slow Clock is used for operating the device in power-save mode. The 32.768 kHz external crystal network is optional, because the low speed System Clock can be derived from the high- speed clock by a prescaler. Also, two independent clocks di- vided down from the high speed clock are available on out- ...

UPC1021C

Vendor:NEC

No word address occurs for a read operation, though the 3-bit page select is latched internally. Reads always use the lower 8-bits that are held internally in the address latch. That is, reads always begin at the address following the previous access. A random read address can be loaded by doing a write operation as explained below.

UPC1023H

Vendor:NECPackage Cooled:ZIP-7D/C:91+

Description Level shift-gate driver Internal regulator voltage Power VCC PMOS Gat driver Power Ground Low side driver output (N MOSFET) Chip supply voltage Charge pump pin Soft start, a capacitor to ground sets the slow start time/set low for shutdown function. Feedback input Sets the converter over-current trip point Signal Ground Input from the phase node between the MOSFETs Reference voltage

UPC1024

Vendor:NECD/C:03+

• Bidirectional data strobe(DQS) • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • Programmable Read latency 2, 2.5 (clock) • Programmable Burst length (2, 4, 8) • Programmable Burst type (sequential & interleave) • Edge aligned data output, center aligned data input • Auto & Self refresh, 7.8us refresh inter...

UPC1026

Vendor:NECPackage Cooled:DIP

This IC is for protecting a lithium ion battery from overcharging, excess discharging, and overcurrent. If abnormalities occur during charging and excess voltage is applied, it has a function that turns off the external FET switch when voltage is applied to each battery beyond a specified time (overcharging detection). It also has a function that turns off the external FET switch when the voltage for each ba...

UPC1026

Vendor:NECPackage Cooled:DIP

This IC is for protecting a lithium ion battery from overcharging, excess discharging, and overcurrent. If abnormalities occur during charging and excess voltage is applied, it has a function that turns off the external FET switch when voltage is applied to each battery beyond a specified time (overcharging detection). It also has a function that turns off the external FET switch when the voltage for each ba...

UPC1028

Vendor:NECPackage Cooled:ZIPD/C:03+

(1) All typical values are at TA = +25C. (2) Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range of the transfer curve for VIN+ = −250mV to +250mV, expressed either as the number of LSBs or as a percent of measured input range (500mV). (3) Ensured by design. (4) Maximum values, including temperature drift, are ensured over the f...

UPC1031C

Vendor:NEC JAPANPackage Cooled:ZIP10

Transmit synchronizing signal input. The PCM output signal from the PCMOUT pin is output in synchronization with this transmit synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. This synchronizing signal must be synchronized in phase with BCLK. The frequency should be 8 kHz 50 ppm to guarantee the AC characteristics which are mainly ...

UPC1031CS

Vendor:HECPackage Cooled:SIP-10D/C:03+

Selected and Unselected refers to the state of the STA111 Selection Controller. A selected STA111 has been properly addressed and is ready to receive Level 2 protocol. Unselected STA111s monitor the system test backplane, but do not accept Level 2 protocol (except for the GOTOWAIT instruction). The data registers and LSPs of unselected STA111s are not accessible from the system test master.

UPC1032

Leads are Readily Solderable Lead and Mounting Surface Temperature for Soldering Purposes: 260C Max. for 10 Seconds Shipped in 12 mm Tape and Reel, 5000 units per reel Polarity: Polarity Band Indicates Cathode Lead ESD Protection: Human Body Model > 4000 V (Class 3) ESD Protection: Machine Model > 400 V (Class C) Marking: U4A, U4B

UPC1032

Vendor:NEC

Leads are Readily Solderable Lead and Mounting Surface Temperature for Soldering Purposes: 260C Max. for 10 Seconds Shipped in 12 mm Tape and Reel, 5000 units per reel Polarity: Polarity Band Indicates Cathode Lead ESD Protection: Human Body Model > 4000 V (Class 3) ESD Protection: Machine Model > 400 V (Class C) Marking: U4A, U4B

UPC1035

Vendor:NECPackage Cooled:DIPD/C:94

8. Guaranteed by Design. 9. This parameter is guaranteed by design but not tested. The bus switch contributes no propagation delay other than the RC delay of the On Resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance). 10. Off Isolation = 20 log10 [VA/VBn].

UPC1037

Vendor:NECPackage Cooled:SOP/8D/C:97+

Where; Kf is the phase detector gain factor in mA/radian K0 is the VCO gain factor in radian/second/Volt N is the total division ratio from VCO to reference frequency wn is the natural loop bandwidth F0 is the phase margin normally set to 45 Since the phase detector is linear over a range of 2p radian, Kf can be calculated from

UPC1037AH

Vendor:MOTOROLAD/C:07+

Ratio of output level with 1-kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer. All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Ele...

UPC1037C

UPC1037H

Vendor:NECPackage Cooled:SIP-7D/C:03+

wide range of output pulse widths from the Q and Q terminals. The time delay from trigger input to output transition (trigger propagation delay) and the time delay from reset input to output transition (reset propagation delay) and the time delay from reset input to output transition (reset propagation delay) are independent of RX and CX. Leading edge triggering (+TR) and trailing edge triggering (-...

UPC1037H

Vendor:NECPackage Cooled:SIPD/C:03+

wide range of output pulse widths from the Q and Q terminals. The time delay from trigger input to output transition (trigger propagation delay) and the time delay from reset input to output transition (reset propagation delay) and the time delay from reset input to output transition (reset propagation delay) are independent of RX and CX. Leading edge triggering (+TR) and trailing edge triggering (-...

UPC1039

Vendor:NECPackage Cooled:SOP8D/C:07+

making use of a multiple Data Memory buffer technique where input channels written in any of the buffers during frame N will be read out during frame N+2. In the IDT72V8985, the minimum throughput delay achievable in Constant Delay mode will be 32 time slots; for example, when input time slot 32 (channel 31) is switched to output time slot 1 (channel 0). Likewise, the maximum delay is achieved when the first...

UPC1043

Vendor:NECPackage Cooled:DIPD/C:5000

These unconditionally stable amplifiers are designed for use as general purpose 50 ohm gain blocks. Also available in chip form (SNA-500), its small size (0.4mm x 0.4mm) and gold metallization make it an ideal choice for use in hybrid circuits.

UPC1048C

Vendor:NECD/C:07+

Parameter VDD to GND VOUTA, VOUTB, VBZ to GND Digital Input Voltages to GND Operating Temperature Range Maximum Junction Temperature (TJ MAX) Storage Temperature Lead Temperature (Soldering, 10 sec) Package Power Dissipation Thermal Resistance, JA, MSOP-10

UPC1050C

Vendor:NECPackage Cooled:DIP/16

This series of silicon tuning varactors have an epitaxial mesa design with a high temperature passivation. This technology is used to produce abrupt tuning varactor in SOT23 package. This family is designed for a low cost medium to high volume market that may be supplied in tape and reel for automated pick and place assembly on surface mount circuit boards.

UPC1050C

Vendor:NECPackage Cooled:1900

This series of silicon tuning varactors have an epitaxial mesa design with a high temperature passivation. This technology is used to produce abrupt tuning varactor in SOT23 package. This family is designed for a low cost medium to high volume market that may be supplied in tape and reel for automated pick and place assembly on surface mount circuit boards.

UPC1050CA

UPC1058C

Vendor:NECPackage Cooled:DIP-16D/C:8429

ACCURACY Linearity Error(1) Linearity Match Differential Linearity Error Monotonicity, TMIN to TMAX Zero Scale Error Zero Scale Error Drift Full-Scale Error Full-Scale Error Drift Zero Scale Matching Full-Scale Matching Power Supply Rejection Ratio (PSRR)

UPC1059CA

Vendor:NECPackage Cooled:DIPD/C:1993

The input of the ADC is switched to the AGC voltage by the rising slope of the clock. When conversion time has passed (about 1.8 ms at 25C), the digitalized field- strength signal is stored in the output registers D0 to D3 as long as the clock is high and can be read by a micro- computer. The falling slope of the clock switches the input of the ADC to the time-code signal. In the mean- time, the digit...

UPC1059CA

Vendor:NECD/C:1993

The input of the ADC is switched to the AGC voltage by the rising slope of the clock. When conversion time has passed (about 1.8 ms at 25C), the digitalized field- strength signal is stored in the output registers D0 to D3 as long as the clock is high and can be read by a micro- computer. The falling slope of the clock switches the input of the ADC to the time-code signal. In the mean- time, the digit...

UPC105A

Vendor:NECPackage Cooled:CAND/C:560

After Preset Mode inputs have been changed to one of the modes, the next positive-going clock transition changes an internal flip-flop so that the countdown can begin at the second positive-going clock transition. Thus, after an MP (Master Preset) mode, there is always one extra count before the output goes high. Figure 1 illustrates a total count of 3 (8 mode). If the Master Preset mode i...

UPC105A (P)

UPC1060

Vendor:NECPackage Cooled:DIP-8D/C:03+

They provide transparent enhancements to Intels 8xC251Sx family with an additional Synchronous Serial Link Controller (SSLC supporting I2C, µWire and SPI protocols), a Keyboard interrupt interface, a dedicated Baud Rate Generator for UART, and Power Management features.

UPC1060D

Vendor:NECPackage Cooled:1888

Tachyon TS focuses on mass storage applications for any topology that require Class 3 and Class 2 (via software), and SCSI upper layer protocol handling. Coupled with a high performance 66 MHz, 32/64-bit PCI bus inter- face, Tachyon TS provides a cost- effective, high-performance mass storage solution.

UPC1066

Vendor:SOP- 8Package Cooled:NECD/C:2004+

UPC1066C

UPC1066G

Vendor:NECPackage Cooled:SOP3.9mmD/C:1995

In applications where only mono 100W / 4Ω operation is desired, e.g. subwoofer, the output filter may be simplified.Two filter sections may be employed in lieu of sections in parallel. Inductors may be ½ the value with twice the current rating. Capacitors are double the value and resistors are ½ the value at twice the power rating.

UPC1069C

Vendor:NEC/NIKKOPackage Cooled:DIP14D/C:96+

NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = Vcc -0.6V at rated current.

UPC1074AGF

The PALCE29MA16 has 29 inputs to drive each product term (up to 58 inputs with both TRUE and complement versions available to the AND array) as shown in the block diagram in Figure 1. Of these 29 inputs, 4 are dedicated inputs, 16 are from eight I/O logic macrocells with two feedbacks, 8 are from other I/O logic macro- cells with single feedback and one is the I/OE input.

UPC1075G-T1

Vendor:NECPackage Cooled:SOP24D/C:90

Source current: In stand-by condition Source current: While detecting leakage Source current: While detecting abnormal voltage Source current: Immediately after driving of SCR Source current: In stand-by condition Source current: While detecting leakage Source current: Immediately after driving of SCR ISO variation with ambient temperature Maximum current voltage Leakage detecting DC input voltag...

UPC1075G-T1CXA1161M

Vendor:NECPackage Cooled:SOP5.2mmD/C:1990

The input capacitor CI is necessary for compensating line influences. Using a resistor of approx. 1 Ω in series with CI, the oscillating circuit consisting of input inductivity and input capacitance can be damped. The output capacitor CQ is necessary for the stability of the regulating circuit. Stability is guaranteed at values 10 µF and an ESR 10 Ω within the operating temperature r...

UPC107A

Vendor:NECPackage Cooled:CAND/C:689

UPC1091GT(151821-0100)

Vendor:NECPackage Cooled:SOPD/C:06+

The UPC1091GT(151821-0100)M instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every single-word instruction can be executed in a single processor cycle. The UPC1091GT(151821-0100)M assembly language

UPC1091GT(151821-0100)

Vendor:NECPackage Cooled:NECD/C:06+

The UPC1091GT(151821-0100)M instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every single-word instruction can be executed in a single processor cycle. The UPC1091GT(151821-0100)M assembly language

UPC1093-B

D/C:排带

UPC1093G/JM

UPC1093G-1-T1

Vendor:SOP8Package Cooled:1317D/C:NEC

Features • Progressive scan allows individual readout of the image signals from all pixels. • High vertical resolution (480 TV-lines) still images without a mechanical shutter • Square pixel • Supports VGA format • Horizontal drive frequency: 24.54MHz • No voltage adjustments (reset gate and substrate bias are not adjusted.) • High resolution, high sensitivi...

UPC1093G2-T1

Vendor:NECPackage Cooled:SOP-8PD/C:1999

22811-009-DTS Rev ADQ# 2010 All technical information is believed to be accurate, but no responsibility is assumed for errors or omissions. Interpoint reserves the right to make changes in products or specifications without notice. HR150 Series is a trademark of Interpoint. Copyright © 1990 - 1999 Interpoint. All rights reserved.

UPC1093G2-T1

Vendor:NECPackage Cooled:SOP-8PD/C:1999

22811-009-DTS Rev ADQ# 2010 All technical information is believed to be accurate, but no responsibility is assumed for errors or omissions. Interpoint reserves the right to make changes in products or specifications without notice. HR150 Series is a trademark of Interpoint. Copyright © 1990 - 1999 Interpoint. All rights reserved.

UPC1093G2-T2

UPC1093G-E1

Vendor:NECPackage Cooled:SOP8D/C:95

The AMUPC1093G-E1AC and UPC1093G-E1AC are characterized for operation from 0C to 70C. The AMUPC1093G-E1AI is characterized for operation from C40C to 85C. The AMUPC1093G-E1AM and UPC1093G-E1AM are characterized for operation over the full military temperature range of C55C to 125C.

UPC1093GE2

Vendor:necPackage Cooled:necD/C:dc00

Hynix HYMD18M645A(L)6-K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

UPC1093GE2

Vendor:necPackage Cooled:necD/C:dc00

Hynix HYMD18M645A(L)6-K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

UPC1093G-E2(FB)

UPC1093G-EI

Vendor:NECPackage Cooled:SOPD/C:95+

The maximum available current can be calculated based on the open circuit CPO voltage, the dropout voltage of the LDO and the effective output resistance of the charge pump. The open circuit CPO voltage is approximately 2VIN (see Figure 2).

UPC1093GS

Vendor:NECPackage Cooled:SOP3.9mmD/C:1990

The information provided herein is believed to be reliable at press time. Stanford Microdevices assumes no responsibility for inaccuracies or omissions. Stanford Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the users own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circu...

UPC1093GT1

Vendor:NECPackage Cooled:2000

UPC1093G-T1

Vendor:N/APackage Cooled:SOPD/C:06+

Four dedicated test terminals control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to th...

UPC1093G-T1(MS)

Vendor:NECPackage Cooled:SMDD/C:08+

Capacitance of Schottky diode quads is measured using an HP4271 LCR meter. This instrument effectively isolates individual diode branches from the others, allowing accurate capacitance measurement of each branch or each diode. The conditions are: 20 mV R.M.S. voltage at 1 MHz. Agilent defines this measurement as CM, and it is equivalent to the capacitance of the diode by itself. The equivalent diago...

UPC1093G-T2

Vendor:NECPackage Cooled:SOP3.9mmD/C:1996

When the BLANKING input is high, the output source drivers are disabled (OFF); the pnp active pull-down sink drivers are ON. The information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches.

UPC1093G-T2/JM

Vendor:NECPackage Cooled:SOP-8

The TO-220 package is universally preferred for all commercial-industrial applications at power dissipation levels to approximately 50 watts. The low thermal resistance and low package cost of the TO- 220 contribute to its wide acceptance throughout the industry.

UPC1093G-TI

Vendor:NECPackage Cooled:SOPD/C:99/P3

The FM1233A permits a pushbutton (or a signal) to initiate a reset externally. Once this external reset is detected on the reset pin, FM1233 also actively asserts the reset signal to main- tain the Reset Timeout period when the external reset is not present .

UPC1093J

Vendor:N/APackage Cooled:TO92D/C:N/A

The ACPF- 7002 is a high rejection full band transmit filter designed for US PCS handsets. Its performance rivals splitband surface acoustic wave (SAW) transmit filters. Since a single filter provides the rejection, no switches are required, saving board space and external components, eliminating switch loss, and reducing programming complexity.

UPC1093J

Vendor:N/APackage Cooled:TO92D/C:N/A

The ACPF- 7002 is a high rejection full band transmit filter designed for US PCS handsets. Its performance rivals splitband surface acoustic wave (SAW) transmit filters. Since a single filter provides the rejection, no switches are required, saving board space and external components, eliminating switch loss, and reducing programming complexity.

UPC1093J-A

UPC1093J-T

Notes: 1. Some failed sectors may exist in the device. The failed sectors can be recognized by reading the sector valid data written in a part of the column address 800 to 83F (The specific address is TBD.). The sector valid data must be read and kept outside of the sector before the sector erase. When the sector is programmed, the sector valid data should be written back to the sector. 2. An mea...

UPC1093J-T(DT)

UPC1093J-T/JD

UPC1093T / 93

Vendor:NECPackage Cooled:SOT-89D/C:09+

UPC1093T / 93

UPC1093T-1-E1

Vendor:NECD/C:08+

BVDSSDrain-to-Source Breakdown Voltage ∆BV DSS/∆T J Temperature Coefficient of Breakdown Voltage RDS(on)Static Drain-to-Source On-State Resistance VGS(th)Gate Threshold Voltage gfsForward Transconductance IDSSZero Gate Voltage Drain Current

UPC1093T-1-E1

Vendor:NECPackage Cooled:TO-89D/C:00+

BVDSSDrain-to-Source Breakdown Voltage ∆BV DSS/∆T J Temperature Coefficient of Breakdown Voltage RDS(on)Static Drain-to-Source On-State Resistance VGS(th)Gate Threshold Voltage gfsForward Transconductance IDSSZero Gate Voltage Drain Current

UPC1093T-2-E2

Vendor:NECPackage Cooled:SOT-89D/C:00+

Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by 1-bit pull-high op- tions). The external interrupt and timer input are pin-shared with the PC0 and PC1, respectively. The external interrupt input is activated on a high to low transition.

UPC1093T-2-E2

Vendor:NECPackage Cooled:SOT-89D/C:00+

Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by 1-bit pull-high op- tions). The external interrupt and timer input are pin-shared with the PC0 and PC1, respectively. The external interrupt input is activated on a high to low transition.

UPC1093TA

Vendor:NECPackage Cooled:SOT-153D/C:08+

The LMH6560 is a high speed, closed-loop buffer designed for applications requiring the processing of very high fre- quency signals. While offering a small signal bandwidth of 680MHz, and a very high slew rate of 3100V/µs the LMH6560 consumes only 46mA of quiescent current for all four buffers. Total harmonic distortion into a load of 100Ω at 20MHz is −51dBc. The LMH6560 is configured...

UPC1093TA-1-E1

Vendor:NECPackage Cooled:无铅06+D/C:1460

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequenti...

UPC1093TA-E1

Vendor:NECPackage Cooled:SOT153D/C:05+

The power switch is an N-channel MOSFET with a maximum on-state resistance of 135 mΩ (VI(IN) = 5 V). Configured as a high-side switch, the power switch prevents current flow from OUTx to IN and IN to OUTx when disabled. The power switch can supply a minimum of 250 mA per switch.

UPC1093TA-E1

Vendor:NECPackage Cooled:SOT23-5D/C:05+

The power switch is an N-channel MOSFET with a maximum on-state resistance of 135 mΩ (VI(IN) = 5 V). Configured as a high-side switch, the power switch prevents current flow from OUTx to IN and IN to OUTx when disabled. The power switch can supply a minimum of 250 mA per switch.

UPC1093TA-E2

Vendor:NECD/C:02+

With application software such as the Intel LDCM (LANDesk Client Managemet software, the user can read all the monitored parameters of system from time to time. And a pop-up warning can also be activated when the monitored item drifts out of the proper/preset range. Also the user can set the upper and lower limits (alarm thresholds) of these monitored parameters and activate programmable and maskable inter...

UPC1093TA-E2

Vendor:NECPackage Cooled:SOT153

With application software such as the Intel LDCM (LANDesk Client Managemet software, the user can read all the monitored parameters of system from time to time. And a pop-up warning can also be activated when the monitored item drifts out of the proper/preset range. Also the user can set the upper and lower limits (alarm thresholds) of these monitored parameters and activate programmable and maskable inter...

UPC1093T-E1

Vendor:NECPackage Cooled:08+D/C:1000

The switching frequency is internally set at 2.25MHz, allow- ing the use of tiny surface mount inductors and capacitors. The internal synchronous switch increases efficiency and eliminates the need for an external Schottky diode. Low output voltages are easily supported with the 0.6V feedback reference voltage. The LTC3406B-2 is available in a low pro- file (1mm) SOT-23 package. Refer to LTC3406 for appli- c...

UPC1093T-E1\9305

UPC1093T-E1-AZ

Vendor:NECPackage Cooled:N/AD/C:03+

While monitoring SR1 and SR2 for charge and discharge currents, the bq2060 monitors the battery-pack poten- tial and the individual cell voltages through the VCELL1CVCELL4 pins. The bq2060 measures the pack voltage and reports the result in Voltage(). The bq2060 can also measure the voltage of up to four series ele- ments in a battery pack. The individual cell voltages are stored in the optional Manufacturer...

UPC1093T-E2/9369

UPC1093T-T1B

Vendor:NEC ?D/C:3101

3rd Order Intermodulation Distortion (VDD = 26 Vdc, Pout = 9.5 W Avg, 2 - Carrier N - CDMA, IDQ = 550 mA, f1 = 1930 MHz, f2 = 1932.5 MHz and f1 =1987.5 MHz, f2 = 1990 MHz; IM3 Measured in a 1.2288 MHz Integrated Bandwidth Centered at f1 - 2.5 Mhz and f2 +2.5 MHz, Referenced to the Carrier Channel Power)

UPC1094

Vendor:NECPackage Cooled:06+D/C:5000

This family is a 16M bit dynamic RAM organized 4,194,304 x 4-bit configuration with Extended Data Out mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time(50, 60 or 70ns) and refresh cycle(2K ref. or 4K ref.) and power consu...

UPC1094

Vendor:NECD/C:5000

This family is a 16M bit dynamic RAM organized 4,194,304 x 4-bit configuration with Extended Data Out mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time(50, 60 or 70ns) and refresh cycle(2K ref. or 4K ref.) and power consu...

UPC1094G-E2(MS)

Vendor:NECPackage Cooled:SOPD/C:98/99

UPC1094G-T2

Vendor:NECPackage Cooled:01+D/C:01+

Figure 5 shows the effects of a fast transient on the output voltage of the regulator. As shown in this figure, the ESR of the output capacitor produces an instanta- neous drop equal to the (DVESR=ESR3DI) and the ESL effect will be equal to the rate of change of the output current times the inductance of the capacitor. (DVESL =L3DI/Dt). The output capacitance effect is a droop in the output voltage proportio...

UPC1094G-T2

Vendor:NECPackage Cooled:SOP/14D/C:SOP/14

Figure 5 shows the effects of a fast transient on the output voltage of the regulator. As shown in this figure, the ESR of the output capacitor produces an instanta- neous drop equal to the (DVESR=ESR3DI) and the ESL effect will be equal to the rate of change of the output current times the inductance of the capacitor. (DVESL =L3DI/Dt). The output capacitance effect is a droop in the output voltage proportio...

UPC1099

Vendor:NECPackage Cooled:DIPD/C:N/A

The LH543601 has two 36-bit ports, Port A and Port B. Each port has its own port-synchronous clock, but the two ports may operate asynchronously relative to each other. Data flow is initiated at a port by the rising edge of the appropriate clock; it is gated by the corresponding edge- sampled enable, request, and read/write control signals. At the maximum operating frequency, the clock duty cycle may...

UPC1099GSE1

Vendor:NECPackage Cooled:7500D/C:9941+

UPC10CK

D/C:02

Flexible inputs and outputs all ground referred 150 MHz large and small-signal bandwidth 46 dB of calibrated gain control range 70 dB isolation in disable mode 10 MHz 0 15% diff gain and 0 05 diff phase performance at NTSC using application circuit Operates on g5V to g15V power supplies Outputs may be paralleled to function as a multiplexer

UPC1100

Vendor:DIPPackage Cooled:NECD/C:03+

• Layer 2 priority encoding (802.3p) (up to 16 priority queues) • VLAN tagging (IEEE 802.3q) • Flow control (IEEE 802.3x) • Link aggregation (IEEE802.3ad) • Multiple power modes with programmable low power operation • Low power design C 3.3 V/1.8 V, 0.18 µm CMOS • 5V tolerant PCI I/Os • 388-pin PBGA package

UPC1100C

Vendor:NECPackage Cooled:32D/C:NEC

• 3.3V family uses 70% less power than the 5 Volt 7201/ 02/03/04 family • 512 x 9 organization (72V01) • 1024 x 9 organization (72V02) • 2048 x 9 organization (72V03) • 4096 X 9 organization (72V04) • Functionally compatible with 720x family • 25 ns access time • Asynchronous and simultaneous read and write • Fully expandable by both word dept...

UPC1100GS

Vendor:NECPackage Cooled:SOPD/C:99/00

The HYM72V16M636T6 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 128Mbytes memory. The HYM72V16M636T6 HYM72V16M636LT6 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.

UPC1100GSE1

Vendor:NECPackage Cooled:2500

UPC1100GS-E1-A

Vendor:NECPackage Cooled:SOP PBD/C:06+

UPC1100GS-E2

Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the write signal WE is asserted LOW. The address presented to the address bus is loaded into the Address Register. The write signals are latched into the Control Logic block. The data lines are automatically three-stated regardless of the state ...

UPC1100GS-T1

Vendor:NECPackage Cooled:SOP16D/C:93

The LS323 is an 8-bit universal shift storage register with TRI-STATE outputs Its function is similar to the LS299 with the exception of Synchronous Reset Parallel load in- puts and flip-flop outputs are multiplexed to minimize pin count Separate inputs and outputs are provided for flip- flops Q0 and Q7 to allow easy cascading Four operation modes are possible hold (store) shift left shift right and p...

UPC1100GS-T1

Vendor:NECPackage Cooled:SOP16D/C:93

The LS323 is an 8-bit universal shift storage register with TRI-STATE outputs Its function is similar to the LS299 with the exception of Synchronous Reset Parallel load in- puts and flip-flop outputs are multiplexed to minimize pin count Separate inputs and outputs are provided for flip- flops Q0 and Q7 to allow easy cascading Four operation modes are possible hold (store) shift left shift right and p...

UPC112

Package Cooled:NEC

Vo Adjust: A 1 % 0.1 W resistor must be directly connected between this pin and GND to set the output voltage to a value higher than 0.8 V. The temperature stability of the resistor should be 100 ppm/C (or better). The set point range for the output voltage is from 0.8 V to 3.6 V. The resistor value required for a given output voltage may be calculated from the following formula. If this is pin is left...