Index "U"Vendor:NECPackage Cooled:TO-220FD/C:02+
Unlike devices using MOS bilateral switching elements, these bipolar circuits represent fully buffered, unilateral transmission paths when selected. This results in extremely high output to input isolation. They also feature fast make-before-break switching action. These features eliminate such problems as switching 'glitches' and output-to-input signal feedthrough.
Vendor:NECPackage Cooled:TO-220FD/C:02+
Unlike devices using MOS bilateral switching elements, these bipolar circuits represent fully buffered, unilateral transmission paths when selected. This results in extremely high output to input isolation. They also feature fast make-before-break switching action. These features eliminate such problems as switching 'glitches' and output-to-input signal feedthrough.
Vendor:NECPackage Cooled:TO-220FD/C:02+
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Vendor:NECPackage Cooled:N/AD/C:02+
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Vendor:NECPackage Cooled:TO-220FD/C:02+
Highest sustained bandwidth per DRAM device - 1.6GB/s sustained data transfer rate - Separate control and data buses for maximized efficiency - Separate row and column control buses for easy scheduling and highest performance - 32 banks: four transactions can take place simul- taneously at full bandwidth data rates
The LP358 and LP2904 are ideal in applications where wide supply voltage and low power are more important than speed and bandwidth. These applications include portable instrumentation, LCD displays, consumer electronics (MP3 players, toys, etc.), and power supplies.
Vendor:NECPackage Cooled:DIPD/C:04+
The following are trademarks of Conexant Systems, Inc.: Conexant, the Conexant C symbol, Whats Next in Communications Technologies, and SmartDAA. Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and names are the property of their respective owners.
Vendor:NECD/C:03+
† Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Vendor:HECD/C:91+
Vendor:NECD/C:9142
Vendor:NECPackage Cooled:ZIP
Vendor:NECPackage Cooled:ZIPD/C:03+
Designed for 802.16 WiBro and dual mode applications with frequencies from 2300 to 2400 MHz. Suitable for Class AB feedforward and predistortion systems. Typical 2 - Carrier W - CDMA Performance: VDD = 28 Volts, IDQ = 1000 mA, Pout = 20 Watts Avg., Full Frequency Band, Channel Bandwidth = 3.84 MHz, PAR = 8.5 dB @ 0.01% Probability on CCDF. Power Gain 15.4 dB Drain Efficiency 23.5% IM3 @ ...
Vendor:NECPackage Cooled:06+D/C:5500
Vendor:NECPackage Cooled:DIP-16D/C:N/A
Vendor:NECPackage Cooled:DIPD/C:99+
The signal current at the input flows into the summing node of a high-gain amplifier. Shunt feedback through RF converts this current to a voltage with gain of approx- imately 2.2kΩ (1.0kΩ for UPC2502). Schottky diodes clamp the output voltage for large input currents, as shown in Figure 3.
Vendor:NECPackage Cooled:06+D/C:99+
The signal current at the input flows into the summing node of a high-gain amplifier. Shunt feedback through RF converts this current to a voltage with gain of approx- imately 2.2kΩ (1.0kΩ for UPC2502). Schottky diodes clamp the output voltage for large input currents, as shown in Figure 3.
Vendor:NECPackage Cooled:DIPD/C:1993
HIGH SPEED: tPD = 5ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA=25C HIGH NOISE IMMUNITY: VNIH = VNIL = 10% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 04 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFI...
Vendor:NECPackage Cooled:DIPD/C:99
- 2.4GB/s sustained data transfer rate - Separate control and data buses for maximized efficiency - Separate row and column control buses for easy scheduling and highest performance - 32 banks: four transactions can take place simul- taneously at full bandwidth data rates
Vendor:NECPackage Cooled:SIPD/C:1997
The UC3825A and UC3825B have dual alternating outputs and the same pin configuration of the UC3825. The UC3823A and UC3823B outputs operate in phase with duty cycles from zero to less than 100%. The pin configuration of the UC3823A and UC3823B is the same as the UC3823 except pin 11 is now an output pin instead of the reference pin to the current limit comparator. A version parts have UVLO thresholds iden...
Vendor:NECPackage Cooled:SQL-15D/C:03+
As seen in the table above, the cyclic key selection mode is active when the SEL pin is floating or high. Under this mode, any of the sound selections(Flat, Rock, Pops, classic, Jazz) may be selected by pressing the CYC key. The default value is the Flat Mode. This Means that when power is turned ON, the mode is active. Pressing the Cyclic Key lets you go from one sound selection to the other in the foll...
Vendor:ZIP15Package Cooled:NECD/C:2004+
Run: CPU on, peripherals on Idle: CPU off, peripherals on Sleep: CPU off, peripherals off Idle mode currents down to 5.8 µA typical Sleep current down to 0.1 µA typical Timer1 oscillator: 1.1 µA typical, 32 kHz, 2V Watchdog Timer: 2.1 µA typical Two-Speed Oscillator Start-up
Vendor:NECPackage Cooled:07+D/C:2285
o +2.7V to +5.5V Input Range o Output Voltages +0.4V to +3.4V Output at 600mA (Top Circuit) +1.5V Output at 600mA (Bottom Circuit) o Dynamically Variable Output Voltage (Top Circuit) o Adjustable Output Voltage Through Resistive Voltage-Divider (Bottom Circuit) o Internal Switch and Synchronous Rectifier o 0.1µA (typ) IC Shutdown Current o 1MHz PWM Switching Frequency o Syncable to 13MHz O...
Vendor:NECPackage Cooled:CAN8
Vendor:NECD/C:02+03+
Vendor:NECPackage Cooled:DIP-8D/C:8330
† All typical values are at VCC = 12 V, TA = 25C. ‡ The algebraic convention, in which the less-positive (more-negative) limit is designated as minimum, is used in this data sheet for logic voltage levels, e.g., when C 5 V is the maximum, the minimum is a more-negative voltage. Not more than one output should be shorted to ground at a time.
Vendor:NECPackage Cooled:SOP-8D/C:99
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The ...
Vendor:NECPackage Cooled:N/AD/C:92/93
Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. Port 2 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. The operation of port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for d...
Vendor:NECPackage Cooled:2000D/C:97
4. Controls various types of load such as relays, motors, lamps and sole- noids. 5. Eliminates the need for a power sup- ply to drive the power MOSFET A power supply used to drive the power MOSFET is unnecessary because of the built-in optoelectronic device. This results in easy circuit design and small PC board area. 6. Low thermal electromotive force (Approx. 1 µV) (Basic insulation) 7. Rein...
Vendor:NECPackage Cooled:DIP/8D/C:1982
State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC ) Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C Power Off Disables Outputs, Permitting Live Insertion High-Impedance State During Power Up and Power Down ...
Vendor:NECPackage Cooled:CAN
Off, voltage VL is generated at the edges of L because of the energy accumulated during the ton period. There- fore, the peak value of the voltage generated at that time is VIN+VL, and it is stored in the output capacitor CL via SD. This generates the step-up output voltage VOUT that is larger than VIN.
Vendor:availPackage Cooled:NEC D/C:06+
Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. Obviously the databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT¥ circuits outside databook specifi- cations.
Vendor:NECPackage Cooled:SSOPD/C:99
12K Bytes of internal SRAM for general purpose scratchpad 768 Bytes of internal SRAM for general purpose scratchpad or program execution while re-flashing external ROM Two, Double Buffered Bulk Endpoints Two, Bi-directional 512 Byte Buffers for Bulk Endpoints 64 Byte RX Control Endpoint Buffer 64 Byte TX Control Endpoint Buffer
In addition to increased performance and FIFO size, the OXCF950 also provides enhanced features including improved flow control. Automated software flow control using Xon/Xoff and automated hardware flow control using CTS#/RTS# and DSR#/DTR# prevent FIFO over-run. Flow control and interrupt thresholds are fully programmable and readable, enabling programmers to fine- tune the performance of their syst...
Vendor:NECPackage Cooled:98+D/C:n/a
high and brake low are invoked from just two control pins with TTL/CMOS compatible levels. The combination of an extremely low RDS ON and the use of a power IC package with low thermal resistance and high thermal capacity helps to minimize system power dissipation. A blocking capacitor at the supply voltage is the only external circuitry due to the integrated freewheeling diodes.
Vendor:NECPackage Cooled:CAND/C:689
Notes: 1. The luminous intensity, IV, is measured at the peak of the spatial radiation pattern which may not be aligned with the mechanical axis of the lamp package. 2. The dominant wavelength, ëd, is derived from the CIE Chromaticity Diagram and represents the perceived color of the device. 3. 1/2 is the off-axis angle where the luminous intensity is 1/2 the peak intensity.
Vendor:NECPackage Cooled:CAN-8
PALE Pulse Width Address Valid to PALE Falling Edge Address Hold from PALE Falling Edge PALE Falling Edge to RD or WR Falling Edge Chip Select Setup to PALE Falling Edge Address Setup to RD or WR Falling Edge Chip Select Setup to RD or WR Falling Edge Chip Select Hold from RD or WR Rising Edge Address Valid to Input Data Valid RD Falling Edge to Data In Valid Data Hold after RD Rising Edge RD Strobe W...
Vendor:NECPackage Cooled:CAND/C:625
Vendor:NECPackage Cooled:NAD/C:625
Vendor:NECPackage Cooled:DIP-4D/C:99+
CAUTION: 1. Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. 2. This device is ESD sensitive. Use of standard ESD handling precautions is required.
The PI5A317A is a single-pole single-throw (SPST), normally closed (NC) switch. The PI5A318A has the same pinout but is a single-pole, single-throw (SPST, normally open (NO) function. The PI5A319A is a single-pole, double-throw (SPDT) switch
Vendor:NECPackage Cooled:97D/C:1264
NOTES 1Oversampling disabled. Static DAC performance will be improved with increased oversampling ratios. 2DNL measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for Cve DNL, the actual step value lies below the ideal step value. 3Value in brackets for V DD_IO = 2.375 V to 2.75 V. 4External current required to ov...
Vendor:NECPackage Cooled:97D/C:1264
NOTES 1Oversampling disabled. Static DAC performance will be improved with increased oversampling ratios. 2DNL measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for Cve DNL, the actual step value lies below the ideal step value. 3Value in brackets for V DD_IO = 2.375 V to 2.75 V. 4External current required to ov...
Vendor:NECPackage Cooled:98+D/C:SSOP
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.
Vendor:NECPackage Cooled:SSOPD/C:08+
Sampling clock rates can be programmed to 16, 32 or 64K bits/second from an internal clock generator or externally injected in the 8 to 64K bits/second range. The internal clocks are derived from an on-chip reference oscillator driven by an externally connected crystal. The sampling clock frequency is output for the synchronization of external circuits.
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 6).
Vendor:NECPackage Cooled:SOPD/C:06+
Hynix HYMD525G726(L)S4-K/H/L series is registered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 256Mx72 high-speed memory arrays. Hynix HYMD525G726(L)S4- K/H/L series consists of eighteen stacked 128Mx4 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD525G726(L)S4-K/H/L series provide a high performance 8-byte interface i...
Vendor:NEC
External circuitry consists of an opamp, a common PLD, and a quad fet switch, which can fit into a footprint of roughly 1 square inch (6.5 sq. cm). The device also can control two status LEDs, and includes in addition 8 addressable output drive lines and 4 readable spare input lines which can be used to control LEDs, LCDs, or other panel functions without requiring additional control lines from the host CP...
Vendor:NECPackage Cooled:SSOP
The EC4558 consists of two high performance opera- tional amplifiers. The IC features high gain, high input resistance, excellent channel separation, wide range of operating voltage and internal frequency compensa- tion. It is specifically suitable for applications in differ- ential-in, differential-out as well as in potential-metric amplifiers and where gain and phase matched channels are mandatory....
Vendor:NECPackage Cooled:SSOP
The EC4558 consists of two high performance opera- tional amplifiers. The IC features high gain, high input resistance, excellent channel separation, wide range of operating voltage and internal frequency compensa- tion. It is specifically suitable for applications in differ- ential-in, differential-out as well as in potential-metric amplifiers and where gain and phase matched channels are mandatory....
Package Cooled:1134D/C:NEC
1.3.3 Bit-Level Control Bit-level control over many of the microcontrollers I/O ports provides a flexible means to ease layout concerns and save board space. All members of the COP8 family provide the ability to set, reset and test any individual bit in the data memory address space, including memory-mapped I/O ports and associated registers. Three memory-mapped pointers handle register indirect addre...
Vendor:NECPackage Cooled:SOP-8D/C:00+
Serial Clock (SCK) - This pin is used to synchronize the communication between the microcontroller and the IS25C64, IS25C32. Op-codes, byte addresses, or data present on the SI pin and latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK for SPI modes (0,0 & 1,1).
Vendor:NECPackage Cooled:08+D/C:1500
Serial Clock (SCK) - This pin is used to synchronize the communication between the microcontroller and the IS25C64, IS25C32. Op-codes, byte addresses, or data present on the SI pin and latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK for SPI modes (0,0 & 1,1).
Vendor:NECPackage Cooled:DIPD/C:99
• IN-SYSTEM PROGRAMMABLE In-System Programmable (ISP™) 5V Only Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality Reprogram Soldered Devices for Faster Prototyping • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS Complete Programmable Device Can Combine Glue Logic and ...
Package Cooled:DIPD/C:02+
• IN-SYSTEM PROGRAMMABLE In-System Programmable (ISP™) 5V Only Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality Reprogram Soldered Devices for Faster Prototyping • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS Complete Programmable Device Can Combine Glue Logic and ...
Vendor:N/APackage Cooled:N/AD/C:08+09+
• Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4µ W typ. static)µ • All inputs, outputs, and I/O are 5V tolerant • Supports hot insertion • Available in SSOP, ...
Vendor:NECPackage Cooled:99D/C:SOP8
• High Jitter Tolerance • Sampling Rate: Up to 216kHz • µP Interface: 3-wire Serial Interface • Master Clock - 128fs/192fs/256fs/384fs/512fs/768fs/1024fs • Power Supply: 5V 5%(Analog), 3V~3.6V with 5V tolerant I/O(Digital) • Small 30-pin VSOP package • Ta: -10 to 70 C
Vendor:NECPackage Cooled:01+/02+D/C:SOP8-3.9
• High Jitter Tolerance • Sampling Rate: Up to 216kHz • µP Interface: 3-wire Serial Interface • Master Clock - 128fs/192fs/256fs/384fs/512fs/768fs/1024fs • Power Supply: 5V 5%(Analog), 3V~3.6V with 5V tolerant I/O(Digital) • Small 30-pin VSOP package • Ta: -10 to 70 C
Vendor:NECPackage Cooled:SOPD/C:1
UPC258G2(40)-E2 (DS-1L) is a high performance audio controller for the PCI Bus. DS-1L consists of two separated functional blocks. One is the PCI Audio block and the other is the Legacy Audio block. PCI Audio block allows Software Driver to handle maximum of 41 concurrent audio streams with the Bus Master DMA engine. The PCI Audio Engine converts the sampling rate of each audio stream and the streams are mix...
Vendor:NECPackage Cooled:6000
Vendor:NECPackage Cooled:SOP-8D/C:9907
Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test capability in conjunction with the protocol device. The DOUT_TXP and DOUT_TXN outputs are held static during the loop-back test. LOOPEN is held low during standard operational state with external serial outputs and in...
Vendor:755Package Cooled:NECD/C:O2
The MAX3873A successfully meets the quality and reliability standards required of all Maxim products. In addition, Maxims continuous reliability monitoring program ensures that all outgoing product will continue to meet Maxims quality and reliability standards.
Vendor:NECPackage Cooled:0136D/C:854
This demonstration board is a two layer PCB. It uses a ground plane on the bottom and signal and power traces on the top. The ground plane has been opened up around op amp pins sensitive to capacitive loading. Power supply traces are laid out to keep current loop areas to a minimum. The SMA (or SMB) connectors may be mounted either vertically or horizontally.
• In the state where the high side gate is VH and the low side gate is VL, the high side FET connected to the VH pin will be on and the low side FET connected to the UL pin will also be on. • Since the HP output is an open collector output, the high output level is the open state.
Vendor:NECPackage Cooled:2000
Vendor:NECPackage Cooled:SOIC-8/3.9mm/2D/C:2000
An input capacitor of 2.2µF (nominal value) or greater, connected between the Input pin and Ground, located in close proximity to the device, will improve transient response and noise rejection. Higher values will offer supe- rior input ripple rejection and transient response. An input capacitor is recommended when the input source, either a battery or a regulated AC voltage, is located far from ...
Vendor:NECPackage Cooled:5967D/C:00/P3
Vendor:NECPackage Cooled:07+D/C:3305
STOP condition at the end of a Write command triggers the internal EEPROM write cycle. Acknowledge Bit (ACK). An acknowledge signal is used to indicate a successful data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse the receiver pulls the SDA bus low to acknowledge the receipt of the 8 bits of data. Data Input....
Vendor:NECPackage Cooled:TO-220D/C:9542+
Vendor:NECPackage Cooled:06+D/C:1100
Vendor:NECD/C:9724
• 256 Resistor Taps • 2-Wire Serial Interface for write, read, and transfer operations of the potentiometer • Wiper Resistance, 100Ω typical @ 5V • 16 Nonvolatile Data Registers for Each Potentiometer • Nonvolatile Storage of Multiple Wiper Positions • Power On Recall. Loads Saved Wiper Position on Power Up. • Standby Current < 5µA Max • VC...
Vendor:NEC
• 256 Resistor Taps • 2-Wire Serial Interface for write, read, and transfer operations of the potentiometer • Wiper Resistance, 100Ω typical @ 5V • 16 Nonvolatile Data Registers for Each Potentiometer • Nonvolatile Storage of Multiple Wiper Positions • Power On Recall. Loads Saved Wiper Position on Power Up. • Standby Current < 5µA Max • VC...
Vendor:NECD/C:08+
LS Audio Out: An audio output of the Rx path (or selected audios, see Figure 3) for a loudspeaker system. This is available for handsfree operation. This output can be connected to VBIAS when not required, by SW6 (Configuration Command (10H)). A driver amplifier may be required.
Vendor:NECD/C:07+
* Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure of absolute maximum rating conditions for extended periods of time may affect device reliability.
D/C:06+
Vendor:NECPackage Cooled:SOT-163D/C:08+
1. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per MIL−STD−883, Method 3015 Machine Model Method 200 V 2. Latch up capability (85C) "100 mA DC with trigger voltage.
Vendor:NECPackage Cooled:SOT-163D/C:09+
Vendor:NEC
Vendor:NECPackage Cooled:SOT163D/C:02+
The UPC2708T performs write operations at bus speed. No write delays are incurred. Data is written to the memory array mere hundreds of nanoseconds after it has been successfully transferred to the device. The next bus cycle may commence immediately. Fast-write time and unlimited read/write endurance make it superior to other types of nonvolatile memory and a good substitute for ordinary SRAM
Vendor:NECD/C:02+
The UPC2708T performs write operations at bus speed. No write delays are incurred. Data is written to the memory array mere hundreds of nanoseconds after it has been successfully transferred to the device. The next bus cycle may commence immediately. Fast-write time and unlimited read/write endurance make it superior to other types of nonvolatile memory and a good substitute for ordinary SRAM
The device may be erased using the Automatic Erase algorithm. The Automatic Erase algorithm automati- cally programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internal to the device.
Vendor:NECPackage Cooled:SMDD/C:07+
During full duplex transmission, the signal at Tip and Ring consists of both the signal from the device to the line and the signal from the line to the device. The signal input at RX, being sent to the line, must not appear at the output TX. In order to prevent this, the device has an internal cancellation circuit. The measure of attenuation is Transhybrid Loss (THL).
Vendor:NECPackage Cooled:SOT163D/C:02+
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability.
Vendor:NECPackage Cooled:02+D/C:0023+
The Si3038 is an integrated direct access arrangement (DAA) chipset that provides a digital, programmable line interface to meet global telephone line requirements. Available in two 16-pin small outline packages (AC97 interface on Si3024 and phone-line interface on Si3014), the chipset eliminates the need for an analog front end (AFE), an isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid...
Vendor:NECPackage Cooled:08+D/C:2004
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
Vendor:NECPackage Cooled:SOT-163D/C:08+
HPC3130A for Compact PCI Applications Provides Card Detection Mechanism Independent of PCI Present Signals for Advanced Card Protection Provides Path to Guarantee Idle State During PCI Bus Connections Fabricated in Advanced Low-Power CMOS Process Features a CBT Switch† Control Feature for REQ64 Implementation Package Options: C 120-pin QFP Package C 128-pin LQFP Package C 144-pin LQFP Package
Vendor:n/aPackage Cooled:SOPD/C:06+
Item R.M.S. On-State Current Surge On-State Current I2t Peak Gate Power Dissipation Average Gate Power Dissipation Peak Gate Current Peak Gate Voltage Critical Rate of Rise of On-State Current Operating Junction Temperature Storage Temperature Isolation Breakdown VoltageR.M.S.
Vendor:NEC
Vendor:NECPackage Cooled:NECD/C:02+
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with ...
Vendor:NECD/C:2007
Microchip's web site: www.microchip.com Microchip's Technical Library CD-ROM, Order No. DS00161 More than 112 Application Notes available: C Embedded Control Handbook, Order No. DS00092 C Embedded Control Handbook, Volume 2, Math Library, Order No. DS00167 Microchip's Overview, Quality Systems and Customer Interface System, Order No. DS00169 Third party software and h...
Vendor:1200Package Cooled:SOT363
Microchip's web site: www.microchip.com Microchip's Technical Library CD-ROM, Order No. DS00161 More than 112 Application Notes available: C Embedded Control Handbook, Order No. DS00092 C Embedded Control Handbook, Volume 2, Math Library, Order No. DS00167 Microchip's Overview, Quality Systems and Customer Interface System, Order No. DS00169 Third party software and h...
Vendor:NECPackage Cooled:03+D/C:SOT363
In operation, the output transistor is OFF until the strength of the mag- netic field perpendicular to the surface of the chip exceeds the threshold or operate point (BOP). When the field strength exceeds BOP, the output transis- tor switches ON and is capable of sinking 25 mA of current.