UPD75108CW-X14

Package Cooled:96D/C:750

These N-Channel enhancement mode power field effect transistors are produced using Fairchilds proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switch mode power supply.

UPD75108CW-X14

Package Cooled:96D/C:750

These N-Channel enhancement mode power field effect transistors are produced using Fairchilds proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switch mode power supply.

UPD75108CW-X18

D/C:640

Table 1 and Figure 2 help illustrate the output changes in the X- and Y-axes as the unit is tilted from +90 to 0. Notice that when one axis has a small change in output per degree of tilt (in mg), the second axis has a large change in output per degree of tilt. The complementary nature of these two signals permits low cost accurate tilt sensing to be achieved with the MEMSIC device (reference applicat...

UPD75108CW-X20

Vendor:NSECD/C:96

The GS4882 and GS4982 determine odd/even field information by comparing vertical sync with an internally generated horizontal sync. This output is clocked out by the falling edge of vertical sync. The odd/even output is low during even fields and high during odd fields.

UPD75108CW-X20

Vendor:NSECPackage Cooled:DIPD/C:96

The GS4882 and GS4982 determine odd/even field information by comparing vertical sync with an internally generated horizontal sync. This output is clocked out by the falling edge of vertical sync. The odd/even output is low during even fields and high during odd fields.

UPD75108CW-X23

Vendor:N/APackage Cooled:200D/C:06+

n 9-bit Inverting BTL transceiver meets IEEE 1194.1 standard on Backplane Transceiver Logic (BTL) n Supports live insertion n Glitch free power-up/down protection n Typically less than 5 pF bus-port capacitance n Low bus-port voltage swing (typically 1V) at 80 mA n Open collector bus-port output allows Wired-OR n Controlled rise and fall time to reduce noise coupling n TTL compatible driver and co...

UPD75108CW-X23

Package Cooled:DIPD/C:615

n 9-bit Inverting BTL transceiver meets IEEE 1194.1 standard on Backplane Transceiver Logic (BTL) n Supports live insertion n Glitch free power-up/down protection n Typically less than 5 pF bus-port capacitance n Low bus-port voltage swing (typically 1V) at 80 mA n Open collector bus-port output allows Wired-OR n Controlled rise and fall time to reduce noise coupling n TTL compatible driver and co...

UPD75108CW-X30

Vendor:NECD/C:97+

NOTES: 1. Dimensions are in inches. 2. Metric equivalents are given for information only. 3. Unless otherwise specified, tolerance is .005 inch (0.13 mm). 4. Physical characteristics of the die thickness = .0187 inch (0.47 mm). 5. Back metal: Cr - Ni - Ag. 6. Top metal: Al. 7. Back contact: Drain. 8. See 6.5 for ordering information.

UPD75108CW-X56

Vendor:NECPackage Cooled:DIP-64D/C:97+

The TC55V8512JI/FTI is a 4,194,304-bit high-speed static random access memory (SRAM) organized as 524,288 words by 8 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high speed, it operates from a single 3.3 V power supply. Chip enable ( CE ) can be used to place the device in a low-power mode, and output enable ( OE ) provides fast memory access. This device is well suited ...

UPD75108CW-X57

Vendor:NECD/C:97+

The SNIC supports 192 kbit/s (2B+D + overhead) full duplex data transmission on a 4-wire balanced transmission line. Transmission capability for both B and D channels, as well as related timing and synchronization functions, are provided on chip. The signalling capability and procedures necessary to enable customer terminals (TEs) to be activated and deactivated, form part of the MT8931Cs functionality. The...

UPD75108CW-X57

Vendor:NECPackage Cooled:DIP-64D/C:97+

The SNIC supports 192 kbit/s (2B+D + overhead) full duplex data transmission on a 4-wire balanced transmission line. Transmission capability for both B and D channels, as well as related timing and synchronization functions, are provided on chip. The signalling capability and procedures necessary to enable customer terminals (TEs) to be activated and deactivated, form part of the MT8931Cs functionality. The...

UPD75108CW-X68

Vendor:N/APackage Cooled:30

UPD75108CW-X76

Vendor:NECPackage Cooled:DIP-64D/C:97+

UPD75108CW-X77

UPD75108CW-X93

Vendor:NECPackage Cooled:DIPD/C:98+

UPD75108CW-X93

Vendor:NECPackage Cooled:10D/C:98+

UPD75108CW-X95

Vendor:NECPackage Cooled:DIPD/C:1998

The HC138, HC238, HCT138, and HCT238 are high-speed silicon-gate CMOS decoders well suited to memory address decoding or data-routing applications. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low-power Schottky TTL logic. Both circuits have three binary select inputs (A0, A1, and A2). If the device is enabled, these inputs determine ...

UPD75108F6F-535-3BE

Features 1) Built-in bias resistors enable the configuration of an inverter circuit without connecting external input resistors (see the equivalent circuit). 2) The bias resistors consist of thin-film resistors with complete isolation to allow negative biasing of the input. They also have the advantage of almost completely eliminating parasitic effects. 3) Only the on / off conditions need to be ...

UPD75108FGF-506-3BE

D/C:93

1. ISA bus group pins are powered by VCC1 power rail. 2. PC_D pads have 4 mA drive capabilities; other output pads have 16 mA drive capabilities. 3. To interface with PC ISA bus, VCC1 should be connected to 5V power and PC_D bus should be buffered. Direction is given by PC_RD signal. 4. Pin Names in this document exhibiting an overbar (PC_CS for example) indicates that the signal is active low.

UPD75108FGF-533-3BE

Vendor:SHARPPackage Cooled:100D/C:9439

pin signalised an interrupt (logic 0). However, if the Mode 0 & 1 pins are at logic 0, the transceiver returns to the sleep condition when the wake up bus voltage signal is not present. When not in sleep mode all valid bus signals will be sent out on the RxD pin. RxD will be placed in the undriven or off state when in sleep mode .

UPD75108G-525

Package Cooled:QFPD/C:89

Silicon chip on Direct-Copper-Bond substrate - High power dissipation - Isolated mounting surface - 2500V electrical isolation Low cathode to tab capacitance (<25pF) International standard package Planar passivated chips Very short recovery time Extremely low switching losses Low IRM-values Soft recovery behaviour Epoxy meets UL 94V-0 Isolated and UL registered E153432

UPD75108G-600-1B

Vendor:NECPackage Cooled:QFP-64D/C:9036+

The OP4008B will tune from 0 to 5 volts as shown in the adjacent plot. For normal use in a PLL, the tuning voltage will not change much from the nominal oper- ating point. The operating point is determined by: (1) the temperature of the OP4008B case, (2) the refer- ence frequency from the PLL, and (3) the internal characteristics of the key components used in the OP4008B part. Although the nominal operating ...

UPD75108GF

*Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.

UPD75108GF- T74-3B

Vendor:NECPackage Cooled:QFPD/C:06+

UPD75108GF- T74-3BE

Vendor:NECPackage Cooled:QFP

UPD75108GF(A)-910

Vendor:NECPackage Cooled:QFPD/C:99+

Non-inductive. Thermally enhanced Industry standard TO220 package. RoHS compliant. Low thermal resistance, 5.9 C/W resistor hot spot to metal tab. Complete thermal flow design available for easy implementation. Superior vibration durability. Small thin package for high density PCB installation.

UPD75108GF12

UPD75108G-F12

Vendor:NECPackage Cooled:NECD/C:89

256-byte SecSi™ (Secured Silicon) Sector Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data Customer lockable: One time programmable. Once locked, data cannot be changed.

UPD75108GF-533-3BE

Vendor:NECPackage Cooled:QFP

UPD75108GF-N16-3BE

Vendor:NECPackage Cooled:2005

The LCD product described in this specification is designed and manufactured for the standard use in OA equipment and consumer products, such as computers, communication equipment, industrial robots, AV equipment and so on. Do not use the LCD product for the equipment that require the extreme high level of reliability, such as aerospace applications, submarine cables, nuclear power control systems and medic...

UPD75108GF-R36

Package Cooled:05+▲▲

Electrical characteristics apply over the full operating range of input voltage, output load (resistive) and baseplate temperature, unless otherwise specified. All temperatures refer to the operating temperature at the center of the baseplate.

UPD75108GF-T14-3BE

Vendor:NECD/C:02+

Functional Description The UPD75108GF-T14-3BE utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the UPD75108GF-T14-3BE requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to m...

UPD75108GF-T14-3BE

Vendor:NECPackage Cooled:QFPD/C:02+

Functional Description The UPD75108GF-T14-3BE utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the UPD75108GF-T14-3BE requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to m...

UPD75108GF-T23-3BE

Package Cooled:05+▲▲D/C:95+

• Supports AT&T TR62411 and Telcordia GR-1244-CORE Stra- tum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 tim- ing for E1 interface • Selectable input reference signal: 8 kHz, 1.544 MHz or 2.048 MHz • Provides eight types of clock signals: C1.5o, C3o, C2o, C4o, C6o, C8o, C16o and C32o • Provides six types...

UPD75108GF-T52-3BE

Vendor:NECPackage Cooled:QFP

The SN65MLVD047 is a quadruple line driver that complies with the TIA/EIA-899 standard, Electrical Characteristics of Multipoint-Low-Voltage Differential Signaling (M−LVDS). The output current of this M−LVDS device has been increased, in comparison to standard LVDS compliant devices, in order to support doubly terminated transmission lines and heavily loaded backplane bus applications. Ba...

UPD75108GF-T52-3BE

Vendor:NECPackage Cooled:QFPD/C:02+

The SN65MLVD047 is a quadruple line driver that complies with the TIA/EIA-899 standard, Electrical Characteristics of Multipoint-Low-Voltage Differential Signaling (M−LVDS). The output current of this M−LVDS device has been increased, in comparison to standard LVDS compliant devices, in order to support doubly terminated transmission lines and heavily loaded backplane bus applications. Ba...

UPD75108GF-T58-3BE

Vendor:NECPackage Cooled:QFPD/C:06+

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and produ...

UPD75108GF-T76

Vendor:N/APackage Cooled:100

• For indirect jumps and calls that use a 16-bit DAG address register for part of the branch address, the Program Sequencer relies on an 8-bit Indirect Jump page (IJPG) register to supply the most significant eight address bits. Before a cross page jump or call, the program must set the program sequencer IJPG register to the appropriate memory page.

UPD75108GF-T83-3BE

Vendor:NECPackage Cooled:05+▲▲D/C:95+

UPD75108GFY

Vendor:NECPackage Cooled:300D/C:00+

UPD75108GF-Y08-3BE

Vendor:NECPackage Cooled:QFPD/C:9644

The period required by the retransmit operation is now fixed and short. The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.) SuperSync FIFOs are part...

UPD75108GF-Y48-3BE

Vendor:NECPackage Cooled:05+▲▲D/C:96+

21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCCC2.0 V. 22. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs.

UPD75108GF-Y78

Vendor:NECPackage Cooled:QFP/64D/C:00+

MODE (Pin 3): Mode Select Input. This pin selects the maximum USB port current of either 100mA or 500mA. When MODE is high, the current out of CHP will be IVOUT/ 1000. When MODE is low, the current out of CHP will be IVOUT/1000 + 370µA (typical).

UPD75108GF-Y78

Vendor:NECPackage Cooled:00+D/C:00+

MODE (Pin 3): Mode Select Input. This pin selects the maximum USB port current of either 100mA or 500mA. When MODE is high, the current out of CHP will be IVOUT/ 1000. When MODE is low, the current out of CHP will be IVOUT/1000 + 370µA (typical).

UPD75108GY30

The crystal used should be a fundamental mode (do not use third overtone), parallel resonant crystal. To optimize the initial accuracy, connect crystal capacitors from pins X1 to ground and X2 to ground. The value of these capacitors is given by the following equation:

UPD75112796

UPD75112-796

TRI-STATE is a registered trademark of National Semiconductor Corporation WATCHDOGTM is a trademark of National Semiconductor Corporation Novell is a registered trademark of Novell Inc NetWareTM is a trademark of Novell Inc Unix is a registered trademark of AT T Bell Laboratories Windows and Windows 95 are registered trademarks of Microsoft Corporation Windows NTTM is a trademark of Microsoft Corporation

UPD75112CW

Vendor:NECPackage Cooled:253D/C:1996

• Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4µ W typ. static)µ • All inputs, outputs, and I/O are 5V tolerant • Available in SSOP, TSSOP, and TVSOP packages

UPD75112CW

Vendor:NECPackage Cooled:DIPD/C:1996

• Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels (0.4µ W typ. static)µ • All inputs, outputs, and I/O are 5V tolerant • Available in SSOP, TSSOP, and TVSOP packages

UPD75112CW -184

Vendor:NECD/C:93

UPD75112CW -184

Vendor:NECPackage Cooled:DIP

UPD75112CW-052

Vendor:NECPackage Cooled:DIP

NOTES 1 iJA e Thermal resistance between junction and the surrounding environment (ambient) measurements are taken 1 ft away from case in air flow environment iJC e Thermal resistance between junction and package face (case) 2 All values of iJA and iJC may fluctuate depending on the environment (with or without airflow and how much airflow) and device power dissipation at temperature of operation Typic...

UPD75112CW-052

Vendor:NECPackage Cooled:DIP

NOTES 1 iJA e Thermal resistance between junction and the surrounding environment (ambient) measurements are taken 1 ft away from case in air flow environment iJC e Thermal resistance between junction and package face (case) 2 All values of iJA and iJC may fluctuate depending on the environment (with or without airflow and how much airflow) and device power dissipation at temperature of operation Typic...

UPD75112CW-064

Vendor:50

UPD75112CW-184SP

Vendor:NECPackage Cooled:DIP

Teletext 1.5 and 2.5, Closed-Caption, VPS and WSS VBI Data Decoding, TeleWeb Compliant Embedded Emulation Resources with In-Situ Flash Programming Capabilities 1.8V and 3.3V Power supplies Eco Standby mode 27-MHz Crystal Oscillator PC input compatible

UPD75112CW-184SP

Vendor:NECPackage Cooled:DIP

Teletext 1.5 and 2.5, Closed-Caption, VPS and WSS VBI Data Decoding, TeleWeb Compliant Embedded Emulation Resources with In-Situ Flash Programming Capabilities 1.8V and 3.3V Power supplies Eco Standby mode 27-MHz Crystal Oscillator PC input compatible

UPD75112CW-222

Vendor:NECPackage Cooled:DIP-64D/C:97+

High-Bandwidth Data Path (up to 500 MHz (1)) Equivalent to IDTQS3VH251 Device 5-V Tolerant I/Os With Device Powered Up or Powered Down Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 4 Ω Typ) Rail-to-Rail Switching on Data I/O Ports C 0- to 5-V Switching With 3.3-V VCC C 0- to 3.3-V Switching With 2.5-V VCC Bidirectional Data Flow With Near-Zero Propagation Delay ...

UPD75112CW-222

Vendor:NECD/C:97+

High-Bandwidth Data Path (up to 500 MHz (1)) Equivalent to IDTQS3VH251 Device 5-V Tolerant I/Os With Device Powered Up or Powered Down Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 4 Ω Typ) Rail-to-Rail Switching on Data I/O Ports C 0- to 5-V Switching With 3.3-V VCC C 0- to 3.3-V Switching With 2.5-V VCC Bidirectional Data Flow With Near-Zero Propagation Delay ...

UPD75112CW-231

Vendor:NECPackage Cooled:DIPD/C:1997

Parameter MASTER CLOCK (CLI) (See Figure 16) CLI Clock Period CLI High/Low Pulse Width Delay from CLI to Internal Pixel Period Position CLPOB PULSE WIDTH (PROGRAMMABLE)1 SAMPLE CLOCKS (See Figure 18) SHP Rising Edge to SHD Rising Edge DATA OUTPUTS (See Figure 19 and Figure 20) Output Delay From Programmed Edge Pipeline Delay SERIAL INTERFACE (SERIAL TIMING SHOWN IN Figure 14 and Figure 15) M...

UPD75112FGF5353BELCSHA7C535

Vendor:NECPackage Cooled:500D/C:01+

UPD75112GA-F87-3BE

Vendor:NECPackage Cooled:PQFPD/C:9710

To compensate the variation in production there is a fine adjust for each of the VCOs. The fine adjusts of the internal VCOs could be set manually (for test purposes) or set by the automatic mode. Theoretically the sign of the changing (increase/ decrease when the voltage of the phase comparator is to high) is selectable, but we need value 1 () in all cases.

UPD75112GA-F87-3BE

Vendor:NECPackage Cooled:PQFPD/C:9710

To compensate the variation in production there is a fine adjust for each of the VCOs. The fine adjusts of the internal VCOs could be set manually (for test purposes) or set by the automatic mode. Theoretically the sign of the changing (increase/ decrease when the voltage of the phase comparator is to high) is selectable, but we need value 1 () in all cases.

UPD75112GF-644-3BE

Vendor:NECPackage Cooled:QFPD/C:95

Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, T...

UPD75112GF6493BE

Vendor:NECPackage Cooled:300D/C:9319+

UPD75112GF-649-3BE

Vendor:NECPackage Cooled:300

UPD75112GF6863BE

Vendor:NECPackage Cooled:1486

UPD75112GF-686-3BE

Vendor:NECPackage Cooled:QFPD/C:2002+

Due to highly efficient magnetic circuit de- sign, leakage flux is reduced and changes in electrical characteristics from compo- nents being mounted close-together are minimized. This all means a packaging density higher than ever before. • Nominal operating power: 140 mW • Outstanding vibration and shock re- sistance. Functional shock resistance: 750 m/s2 {75G} Destructive...

UPD75112GF-686-3BE

Vendor:NECPackage Cooled:QFPD/C:2002+

Due to highly efficient magnetic circuit de- sign, leakage flux is reduced and changes in electrical characteristics from compo- nents being mounted close-together are minimized. This all means a packaging density higher than ever before. • Nominal operating power: 140 mW • Outstanding vibration and shock re- sistance. Functional shock resistance: 750 m/s2 {75G} Destructive...

UPD75112GF-764

Vendor:NECPackage Cooled:QFPD/C:08+

UPD75112GF-797-3BE

Vendor:NECPackage Cooled:QFPD/C:96+

Optional accessories for module-type MCC 60 version 1 B Keyed gate/cathode twin plugs with wire length = 350 mm, gate = yellow, cathode = red Type ZY 200L (L = Left for pin pair 4/5)UL 758, style 1385, Type ZY 200R (R = right for pin pair 6/7)CSA class 5851, guide 460-1-1

UPD75112GF-E12-3BE

Vendor:NECPackage Cooled:QFPD/C:96+

Immediately upon entering the GS4882/GS4982 the video signal is passed to the devices dual mode input clamp in order to clamp the sync tip of the input video waveform to 1.55 Volts. The GS4882/GS4982s dual mode input clamp, with both Hard Clamp and Soft Clamp capabilities, has been specifically designed for use in high performance sync sepa- ration. The dual mode input clamp aids in maintaining the accuracy ...

UPD75112GF-E13

HiMARK Technology, Inc. reserves the right to change the product described in this datasheet. All information con- tained in this datasheet is subject to change without prior notice. HiMARK Technology, Inc. assumes no responsibility for the use of any circuits shown in this datasheet.

UPD75112GF-E13-3BE

Vendor:NECPackage Cooled:05+▲▲D/C:96+

If the transient performance requirements exceed that specified in the data sheet, or the total amount of load capacitance is above 3,000 µF, the selection of output capacitors becomes more important. For further guidance consult the separate application note, Selecting Output Capacitors for PTH Products in High-Performance Applica- tions.

UPD75112GF-E17-3BE

Vendor:NECPackage Cooled:QFP-D/C:95

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-Q7; UDM corresponds to the data on DQ8-Q15.

UPD75112GF-E20

A MOSFET transistor is constructed of many individual MOSFET cells connected in parallel. They share the current total very evenly. If one of these cells are brought out to a pin, that cell will pass an accurate proportional amount of the total current. This current can be used as a low power sense of the whole current without passing that whole current through a sensing device like a resistor. This small...

UPD75112GF-E20-3BE

Package Cooled:05+▲▲D/C:96+

During the clamping operation, the input video signal is passed through the device's internal color burst filter. The internal filter attenuates the color burst by typically >15 dB. Figure 1 shows the typical frequency response of the internal color burst filter.

UPD75112GF-F10

Vendor:QFPPackage Cooled:QFPD/C:2003+

Shift Frequency Read Cycle Time Access Time Read Recovery Time Read Pulse Width(3) Read Pulse Low to Data Bus at Low Z(4) Write Pulse High to Data Bus at Low Z(4,5) Data Valid from Read Pulse High Read Pulse High to Data Bus at High Z(4) Write Cycle Time Write Pulse Width(3) Write Recovery Time Data Setup Time Data Hold Time Reset Cycle Time Reset Pulse Width(3) Reset Setup Time(4) Reset Recovery T...

UPD75112GF-F20

Vendor:NECPackage Cooled:QFPD/C:2000

Parameter DC INPUT CHARACTERISTICS Input Voltage Range Input Differential Voltage Input Offset Voltage Input Offset Voltage Channel Matching Offset Voltage Tempco Input Bias Current Input Bias Current Tempco Input Offset Current Input Capacitance Input Resistance, Differential Mode Input Resistance, Common Mode Active Gain Common-Mode Rejection Ratio Hysteresis LATCH ENABLE CHARACTERIS...

UPD75112GF-F87-3BE

Vendor:NECPackage Cooled:QFPD/C:9736

combined with thermal shutdown and automatic restart protect the device against overload. The device detects open load condition both is on and off state. Output shorted to VCC is detected in the off state. Device automatically turns off in case of ground pin disconnection.

UPD75112GF-F87-3BE

Vendor:NECD/C:9736

combined with thermal shutdown and automatic restart protect the device against overload. The device detects open load condition both is on and off state. Output shorted to VCC is detected in the off state. Device automatically turns off in case of ground pin disconnection.

UPD75112GF-F91-3BE

Vendor:NECPackage Cooled:QFPD/C:9903+

This parameter is periodically sampled and not 100% tested. This application is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which may be obtained from www.microchip.com.

UPD75112GF-F93-3BE

Vendor:NECPackage Cooled:QFP

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Op...

UPD75112GF-F93-3BE

Vendor:NECPackage Cooled:QFP

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Op...

UPD75112GF-G02-3BE

Vendor:NECPackage Cooled:QFPD/C:*

The Loop Supervision circuit monitors the state of the phone line and when the phone goes Off Hook" the SHK pin goes high to indicate this state. This pin reverts to a low state when the phone goes back "On Hook" or if the loop resistance is too high (>2.3KΩ)

UPD75112GF-G02-3BE

Vendor:NECPackage Cooled:QFPD/C:*

The Loop Supervision circuit monitors the state of the phone line and when the phone goes Off Hook" the SHK pin goes high to indicate this state. This pin reverts to a low state when the phone goes back "On Hook" or if the loop resistance is too high (>2.3KΩ)

UPD75112GF-G09-3BE

Vendor:NECPackage Cooled:QFPD/C:00+

The IGBT is ideal for many high voltage switching applications operating at moderate frequencies where low conduction losses are essential, such as: AC and DC motor controls, power supplies and drivers for solenoids, relays and contactors.

UPD75116

Vendor:NECPackage Cooled:N/AD/C:00+

UPD75116CS-297

Vendor:NSECD/C:9729

Case: SOT-26, Molded Plastic Case material - UL Flammability Rating 94V-0 Moisture sensitivity: Level 1 per J-STD-020A Terminals: Solderable per MIL-STD-202, Method 208 Terminal Connections: See Diagram Marking: Date Code and Marking Code (See Diagrams & Page 3) Weight: 0.015 grams (approx.) Ordering Information (See Page 3)

UPD75116CW-131

Vendor:NECPackage Cooled:DIPD/C:1990

dMAX Dual Data Movement Accelerator. The dMAX is a module designed to perform Data Movement Acceleration. The Data Movement Accelerator (dMAX) controller handles user-programmed data transfers between the internal data memory controller and the device peripherals on the C672x DSPs. The dMAX allows movement of data to/from any addressable memory space including internal memory, peripherals, and external me...

UPD75116CW-131

Vendor:NECPackage Cooled:DIPD/C:1990

dMAX Dual Data Movement Accelerator. The dMAX is a module designed to perform Data Movement Acceleration. The Data Movement Accelerator (dMAX) controller handles user-programmed data transfers between the internal data memory controller and the device peripherals on the C672x DSPs. The dMAX allows movement of data to/from any addressable memory space including internal memory, peripherals, and external me...

UPD75116CW-188

Vendor:NECD/C:99

Conditions at VDRM, single phase, half wave, Tj125 at VDRM, single phase, half wave, Tj125 On-State Current 400A, Tj25 Inst. measurement Tj25IT1AVD6V Tj125VD1 2VDRM IT130AIG100mATj25 1 2VDRM /dt0.1A/sVDdIG 2 VDRM, Exponential wave.Tj125, VD 3 Tj25 Tj25 Junction to case

UPD75116CW-276

Vendor:NECPackage Cooled:DIP64D/C:2007+

Each device includes a voltage regulator, two Hall transducers, temperature com- pensating circuitry, a low-level amplifier, bandpass filter, Schmitt trigger, and an output driver. The on-board regulator permits operation with supply voltages from 4.0 to 26.5 V. The output stage can switch 20 mA over the full frequency response range of the sensor, and is compatible with TTL and CMOS logic circ...

UPD75116CW-A06

Vendor:NECPackage Cooled:DIPD/C:1996

Compliance with PCI Bus Power Management Interface Specification Revision 1.1 (PC99) Compliance with ANSI SCSI standards for class 1, class 2, class 3, and intermix Fibre Channel service: ❒ Second Generation FC Generic Services Definition (FC-GS-2), NCITS 288.200x, Project 1134-D, revision 5.3 ❒ Third Generation FC Generic Services Definition (FC-GS-3) draft, revision 6.2 ❒ Fi...

UPD75116CW-A25

Vendor:NECPackage Cooled:DIPD/C:1995

The HYM72V64C756T4P -Series are high speed 3.3-Volt synchronous dynamic RAM Modules composed of eighteen 64Mx4 bit Synchronous DRAMs in 54-pin TSOPII, two 48-pin SOP Register Buffers, one 24-pin SOP PLL and 8-pin TSSOP 2K bit EEPROM on a 168-pin glass-epoxy printed circuit board. One 0.22µF and one 0.0022µF decoupling capacitors per each SDRAM are mounted on the module. The HYM72V64C756T4P -Ser...

UPD75116CW-A34

Vendor:NECD/C:97+

The signal/pin assignments are listed in Table 4. Low active signals have a  prefix. Pin types are Input, Output or Input/Output. Section Electrical specification and DC characteristics defines the all input and output type structures.

UPD75116CW-A34G

Vendor:NECPackage Cooled:DIPD/C:1996

UPD75116CWA35

Vendor:NECPackage Cooled:277D/C:98+

UPD75116CW-A35

Vendor:NECPackage Cooled:DIPD/C:98+

NOTES: 1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics. 2. Per input driven at the specified level. A and Y pins do not contribute to ∆Icc. 3. This parameter is guaranteed but not tested. 4. This parameter represents the current required to switch internal capacitance at the specified frequency. The A and Y inputs do not contribute to ...

UPD75116CW-A35

Vendor:NECD/C:98+

NOTES: 1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics. 2. Per input driven at the specified level. A and Y pins do not contribute to ∆Icc. 3. This parameter is guaranteed but not tested. 4. This parameter represents the current required to switch internal capacitance at the specified frequency. The A and Y inputs do not contribute to ...

UPD75116CW-A39

Vendor:DIP64Package Cooled:12D/C:NEC

The load impedance is defined as the impedance seen from the UPD75116CW-A39s ANT1, ANT2 into the matching network. Do not confuse this large signal load impedance with a small signal input impedance delivered as input characteristic of RF amplifiers and measured from the application into the IC instead of from the IC into the application for a power amplifier.