UDA1314TS

Vendor:PHILIPSPackage Cooled:SOP

UDA1320ATS

Package Cooled:SSOP

The built-in LDO can be used for a second output voltage derived either from the SEPIC output or directly from the battery. The output voltage of this LDO can be programmed by an external resistor divider or is fixed internally on the chip. The LDO can be enabled separ- ately i.e., using the power good of the SEPIC stage.

UDA1320ATS/N2

Vendor:4705

WRDI - Write Disable The WRDI command disables all write activity by clearing the Write Enable Latch. The user can verify that writes are disabled by reading the WEL bit in the status register and verifying that WEL=0. Figure 5 below illustrates the WRDI command bus configuration.

UDA1320ATS/N2(SSOP2.5K/RL)00

Vendor:PHID/C:0

UDA1320ATSN2

Vendor:PHIPackage Cooled:3900D/C:02+

Once the device detects a button press, it reads the button inputs and updates the synchronization counter. The synchronization counter and crypt key are input to the encryption algorithm and the output is 32 bits of encrypted information. This encrypted data will change with every button press, its value appearing externally to randomly hop around, hence it is referred to as the hopping portion of t...

UDA1321H/102

Vendor:PHILPackage Cooled:98D/C:1620

In case of a faulty blocked dominant TxD input signal the CANH output is switched off automatically after the specified TxD timeout reaction time to prevent a dominant bus. The transmission is continued by next TxD L to H transition without delay.

UDA1321HN101

Vendor:PHILIPSPackage Cooled:1320D/C:9830+

UDA1321H-N101

Vendor:PHILIPSPackage Cooled:QFP64D/C:98+

Capacitance of Schottky diode quads is measured using an HP4271 LCR meter. This instrument effectively isolates individual diode branches from the others, allowing accurate capacitance measurement of each branch or each diode. The conditions are: 20 mV R.M.S. voltage at 1 MHz. Agilent defines this measurement as CM, and it is equivalent to the capacitance of the diode by itself. The equivalent diago...

UDA1321H-N101

Vendor:PHILIPSPackage Cooled:QFP64D/C:98+

Capacitance of Schottky diode quads is measured using an HP4271 LCR meter. This instrument effectively isolates individual diode branches from the others, allowing accurate capacitance measurement of each branch or each diode. The conditions are: 20 mV R.M.S. voltage at 1 MHz. Agilent defines this measurement as CM, and it is equivalent to the capacitance of the diode by itself. The equivalent diago...

UDA1321PS

Vendor:phPackage Cooled:phD/C:dc99

5V CMOS and TTL Compatible Fast Switching Single Event Effect (SEE) Hardened Low Total Gate Charge Simple Drive Requirements Ease of Paralleling Hermetically Sealed Light Weight Complimentary P-Channel Available - IRHLUB7970Z4 n Available on Tape & Reel

UDA1321PSN101

Package Cooled:500D/C:99+

NOTES: 11. Measured using Eastman Kodak neutral white test card having 90% diffuse reflectance located a distance from the front surface of the reflective sensors. Reference: Eastman Kodak catalog number #1257795. 12. Crosstalk is the output voltage measured with the indicated current on the LED and with no reflecting surface. Ambient light is excluded with a black box approximately 20 cm in each dimens...

UDA1321PSN101

Package Cooled:500D/C:99+

NOTES: 11. Measured using Eastman Kodak neutral white test card having 90% diffuse reflectance located a distance from the front surface of the reflective sensors. Reference: Eastman Kodak catalog number #1257795. 12. Crosstalk is the output voltage measured with the indicated current on the LED and with no reflecting surface. Ambient light is excluded with a black box approximately 20 cm in each dimens...

UDA1321T

The Rambus Direct RDRAM™ is a general purpose high-performance memory device suitable for use in a broad range of applications including computer memory, graphics, video, and any other application where high bandwidth and low latency are required.

UDA1321T/N/01

UDA1321TN101

Vendor:phPackage Cooled:phD/C:dc98

The CP3SP33 connectivity processor is an advanced mi- crocomputer with system timing, interrupt logic, instruction cache, data memory, and I/O ports included on-chip, mak- ing it well-suited to a wide range of embedded applications. The block diagram on page 1 shows the major on-chip com- ponents of the CP3SP33.

UDA1325A/106

Package Cooled:06+D/C:800

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input ...

UDA1325H/108

Vendor:PHILIPSPackage Cooled:QFP1420-64D/C:00+

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Companys quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog p...

UDA1325H/N104

Vendor:PHIPackage Cooled:03+D/C:QFP/64

+15 VIN - is the input for applying +15 volts to run the low power section of the hybrid. This pin should be connected to +15 VOUT if running off of the internal regulator. The re- quired bypassing of the +15 VOUT pin is sufficient in this case. For bringing in external +15 volts, this pin should be bypassed with a 10 µF capacitor and a 0.1 µF capacitor as close to this pin as possible.

UDA1325H106

Vendor:PHIPackage Cooled:3750D/C:03+

UDA1325H106

Vendor:PHIPackage Cooled:3750D/C:03+

UDA1325H107

Vendor:PHILIPSPackage Cooled:1097D/C:03/04+

UDA1325HN

UDA1325PS/106

Vendor:PHILIPSPackage Cooled:PHILIPSD/C:800

MAX 3000A devices are lowCcost, highCperformance devices based on the Altera MAX architecture. Fabricated with advanced CMOS technology, the EEPROMCbased MAX 3000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices in the C4, C5, C6, C7, and C10 speed grades are compatible w...

UDA1325PS/N106

Vendor:PHIPackage Cooled:DIPD/C:08+

These two examples show how the NLAS4599 can be used to select from two outputs, such as crystals and digital, or analog signals under microprocessor control. The NLAS4599 will stop or pass any signal between GND and VCC, either digital or analog, and preserve its voltage level. The device is usable beyond 100 MHz, since the 3 dB point is beyond 150 MHz.

UDA1325PS/N106

Vendor:PHIPackage Cooled:N/AD/C:08+

These two examples show how the NLAS4599 can be used to select from two outputs, such as crystals and digital, or analog signals under microprocessor control. The NLAS4599 will stop or pass any signal between GND and VCC, either digital or analog, and preserve its voltage level. The device is usable beyond 100 MHz, since the 3 dB point is beyond 150 MHz.

UDA1328T

Vendor:PHIPackage Cooled:SOP大D/C:N/A

Typical system performance parameters for the receiver are 93 dB gain, 7.5 dB noise figure, input-referred third-order intercept point (IIP3) of +1 dBm, AGC settling time of 8 µs, and Tx-to-Rx switching time of 3 µs. The transmitter typical system performance parameters are an output power range from C7 dBm to +8 dBm in 1 dB steps, C40 dBc carrier leakage after calibration, 22 dB sideband s...

UDA1328T/N1

Vendor:PHILIPSPackage Cooled:TSOPD/C:06+

5.1 Module Interface Connectors 5.2 Module Connector Pin Configuration 5.3 Backlight Connectors 5.4 Backlight Connector Pin Configuration 5.5 Signal Electrical Characteristics 5.6 Interface Timings Characteristics 5.7 Interface Timing Definition

UDA1328T/N1/S1

Vendor:PHIPackage Cooled:SOP-32D/C:0

Unless otherwise specified, these specifications apply over Vcc=5V, VcH1=VcH2=VCL=VccLDO=12V and TA=0 to 70C. Typical values refer to TA=25C. Low duty cycle pulse testing is used which keeps junction and case tem- peratures equal to the ambient temperature.

UDA1328T/NI/S1

Vendor:PHIPackage Cooled:SOPD/C:06+

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm−b...

UDA1330A

Vendor:PHILIPSPackage Cooled:TSSOP16

Generates all clocks required for single and two-way multi-processor (MP) platforms, including: M Four differential current-mode Host clock pairs M Four 66.67MHz 3.3V CK66 clock outputs M Ten 33.3MHz 3.3V PCI clock outputs M Two 3.3V Memory Reference clock outputs M Two 48MHz 3.3V CK48 clock outputs M Two buffered copies of the crystal reference

UDA1330ATSN1

Vendor:PHIPackage Cooled:178D/C:98/P4

UDA1330ATSN2.118

UDA1334ATS

Vendor:PHID/C:05+

LVDS Clock input pins for the ADC. The differential clock signal must be a.c. coupled to these pins. The input signal is sampled on the falling edge of CLK+. See Section 1.1.2 for a description of acquiring the input and Section 2.3 for an overview of the clock inputs.

UDA1334ATS/N2

Vendor:PHILIPSPackage Cooled:4D/C:2005+

Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur.

UDA1334B

Vendor:PHILIPSPackage Cooled:SOP-16D/C:06+

Note 1. For current consumption, it is assumed that high side cell voltage and low side cell voltage are identical. When the cell voltages differ, it is set by the higher voltage. 2. GD pin are high impedance when the current consumption is below the operating limit voltage. 3. When the circuit configuration calls for discharge resumption through charging, the discharge resumption voltage is 2.4V typ.

UDA1334B

Vendor:PHILIPSPackage Cooled:SOP-16D/C:N/A

Note 1. For current consumption, it is assumed that high side cell voltage and low side cell voltage are identical. When the cell voltages differ, it is set by the higher voltage. 2. GD pin are high impedance when the current consumption is below the operating limit voltage. 3. When the circuit configuration calls for discharge resumption through charging, the discharge resumption voltage is 2.4V typ.

UDA1334BT

Vendor:PHIPackage Cooled:SOP-16

HY57V561620 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

UDA1334BT

Vendor:PHI

HY57V561620 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

UDA1334BT/N2

Vendor:PHILPackage Cooled:TSSOPD/C:0514

Forward voltage(typ.) IF=20mA Forward voltage(max.) IF=20mA Reverse current(max.) VR=5V Wavelength at dominant emission(typ.) IF=20mA Wavelength at peak emission(typ.) IF=20mA Spectral line half-width IF=20mA Capacitance VF=0V,f=1MHz

UDA1334BTD

Vendor:PHILIPSD/C:02+

Documentation of the UDA1334BTD controller. Includes details about the CPU, memory, input/output, ReNumeration™, bulk transfers, endpoint zero, iso- chronous transfers, interrupts, resets, power management, registers, AC/ DC parameters, and packages.

UDA1334BTS/

Vendor:PHIPackage Cooled:SSOPD/C:07/08+

The UDA1334BTS/ and UDA1334BTS/ are designed for applications such as microprocessor controlled programmable gain amplifiers, automatic test equipment, communication systems, and data acquisition systems. The UDA1334BTS/ is normally closed and the UDA1334BTS/ is normally open as shown in the Logic Table.

UDA1334BTSN2

Vendor:PHIPackage Cooled:1135D/C:01+

BiFET operational amplifiers offer the inherently higher input impedance of the JFET-input transistors, without sacrificing the output drive associated with bipolar amplifiers. This makes them better suited for interfacing with high-impedance sensors or very low-level ac signals. They also feature inherently better ac response than bipolar or CMOS devices having comparable power consumption.

UDA1334TS

Vendor:PHILIPSPackage Cooled:SSOP16D/C:26

Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions. Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. ©2005 Hamamatsu Photonics K.K.

UDA1335H/N1

Vendor:QFP/64Package Cooled:QFP/64D/C:350

Voltage of 1.8 V High Efficiency Boost, SEPIC or Flyback (Buck-Boost) Topologies Drives External FETs for High-Current Applications Up to 2-MHz Oscillator Synchronizable Fixed Frequency Operation High-Efficiency Low-Power Mode High-Efficiency at Very Low-Power with Programmable Variable Frequency Mode Pulse-by-Pulse Current Limit 5-µA Supply Current in Shutdown 150-µA Supply Current in Sle...

UDA1338H/N1

Vendor:PHILIPSPackage Cooled:03+D/C:QFP

The SN65LVCP40 combines a pair of 1:2 buffers with a pair of 2:1 multiplexers (mux). Selectable switch-side loopback supports system testing. System interconnects and serial backplane applications of up to 4 Gbps are supported. Each of the two independent channels consists of a transmitter with a fan-out of two, and a receiver with a 2:1 input multiplexer.

UDA1340M

Vendor:PH

Pin-Out Compatible with Standard 125 Logic Products 5Ω A/B bi-directional switch Isolation Under Power-Off Conditions Over-voltage tolerant Latch-up performance exceeds 100mA VCC = 2.3V - 3.6V, normal range ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) Output Enable, Active Low Available in TSSOP and QSOP packages

UDA1340M/N1

Vendor:PHILIPSPackage Cooled:SSOPD/C:2001

Byte program and Chip erase Auto program and Auto erase Program/erase operation controlled by software command Program/erase pulse controlled by an embedded timer 10000 program/erase cycles Tri-state output buffer TTL-compatible input and output in read and write mode Contained device-identifier code Incorporated data-protection Available packaging for Surface Mount

UDA1340M118

Max. UnitsConditions CCCVVGS = 0V, ID = 250µA CCCV/C Reference to 25C, ID = 1mA 1.0ΩVGS = 10V, ID = 3.3A „ 4.5VVDS = VGS, ID = 250µA 25VDS = 400V, VGS = 0V µA 250VDS = 320V, VGS = 0V, TJ = 125C 100VGS = 30V nA -100VGS = -30V

UDA1341TS/C

Vendor:PHILIPSPackage Cooled:SSOP28D/C:08+

UDA1341TS/N1

Vendor:PHILIPSD/C:04+

The bq2014 recognizes a valid battery whenever VSB is greater than 0.1V typical. VSB rising from below 0.25V or falling from above 2.25V (VMCV) resets the device. Re- set can also be accomplished with a command over the serial port as described in the Reset Register section.

UDA1341TS/N1518

D/C:0804+

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

UDA1341TSDB

Vendor:PHILIPSPackage Cooled:SSOPD/C:00+

The PCM1780/81/82 is a CMOS, monolithic, inte- grated circuit, which includes stereo digital-to-analog converters and support circuitry in a small 16-lead SSOP package. The data converters use TIs en- hanced multilevel delta-sigma architecture to achieve excellent dynamic performance and improved toler- ance to clock jitter. The PCM1780/81/82 accepts industry standard audio data formats with 16- to ...

UDA1342FSIC

Vendor:PHIPackage Cooled:SSOP28MD/C:2007+

Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, TA = 25C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. Measured by the voltage drop between I and Y pin at indicated current through the swi...

UDA1342T

Positive analog supply pin. This voltage is also used as the reference voltage. This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to GND with 1 µF and 0.1 µF monolithic ceramic capacitors located within 1 cm of the power pin.

UDA1342TS

Vendor:PHILIPS

7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).

UDA1342TSDB

The maximum power package dissipation is the power dissipation level at which the junction temperature reaches its maximum operating value, i.e. 125C. Depending on the ambient power dissipation and thus the maximum available output current.

UDA1342TSDB-T

Vendor:ＮＸＰ

3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-...

UDA1343TT

Vendor:N/APackage Cooled:N/AD/C:08+09+

The TLV277x CMOS operational amplifier family combines high slew rate and bandwidth, rail-to-rail output swing, high output drive, and excellent dc precision. The device provides 10.5 V/µs of slew rate and 5.1 MHz of bandwidth while only consuming 1 mA of supply current per channel. This ac performance is much higher than current competitive CMOS amplifiers. The rail-to-rail output swing and high ou...

UDA1345TS/N1

Vendor:PHIPackage Cooled:SSOP/28D/C:99+

Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by the two ORPs. Each ispLSI 2128 and 2128A device contains four Megablocks.

UDA1345TS/N2A

Vendor:PHILIPSPackage Cooled:SSOPD/C:04+

The dimensional diagrams below compare the critical dimensions of the ON Semiconductor C-106 package with competitive devices. It has been demonstrated that the smaller dimensions of the ON Semiconductor package make it compatible in most lead-mount and chassis-mount applications. The user is advised to compare all critical dimensions for mounting compatibility.

UDA1345TS/V2

Vendor:PHILIPSPackage Cooled:10

UDA1345TSDB

The Digital Receiver Front-end DRX 3960A performs the entire multistandard Quasi Split Sound (QSS) TV IF processing, AGC, video demodulation, and genera- tion of the second sound IF (SIF) with only one SAW filter. The IC is designed for applications in TV sets, VCRs, PC cards, and TV tuners.

UDA1347TS

Vendor:PHILIPSPackage Cooled:SSOP-28PD/C:05+

SOT-89 ------------------------------------------------------------------------------------------------------------------ 0.5W TO-92 -------------------------------------------------------------------------------------------------------------------- 0.6W

UDA1347TS/N2

Vendor:PHIPackage Cooled:SSOPD/C:2001

NOTES: 1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to applying inputs on I/OX. 2. OPTX selects the operating voltage levels for the I/Os and controls on that port. If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that port's I/Os and controls will operate at 2...

UDA134DM

Vendor:PHILIPSPackage Cooled:00+D/C:SOP

SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to Software Data Protection Algorithm). After writing the 3-byte command sequence and after tWC the entire AT28C010-12DK will be protected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or pag...

UDA1350

Vendor:PHL

6. A transient suppressor is normally selected according to the working peak reverse voltage (VRWM), which should be equal to or greater than the DC or continuous peak operating voltage level. 7. VBR measured at pulse test current IT at an ambient temperature of 25C. 8. Surge current waveform per Figure 2 and derate per Figure 3.

UDA1350AH/N2

Vendor:PHILIPSPackage Cooled:2000

The TLC372C is characterized for operation from 0C to 70C. The TLC372I is characterized for operation from −40C to 85C. The TLC372M is characterized for operation over the full military temperature range of −55C to 125C. The TLC372Q is characterized for operation from − 40C to 125C.

UDA1350ATS/N2

Vendor:PHILIPSPackage Cooled:SSOP28D/C:51

This pin represents the output of the charge pump. The voltage at this pin is the bias voltage for the IC. Connect a decoupling capacitor from this pin to ground. The value of the decoupling capacitor should be at least 10x the value of the charge pump capacitor. This pin may be tied to the bootstrap circuit as the source for creating the BOOT voltage.

UDA1350ATSN2

Vendor:PHIPackage Cooled:48000D/C:00+

1. ISA bus group pins are powered by VCC1 power rail. 2. PC_D pads have 4 mA drive capabilities; other output pads have 16 mA drive capabilities. 3. To interface with PC ISA bus, VCC1 should be connected to 5V power and PC_D bus should be buffered. Direction is given by PC_RD signal. 4. Pin Names in this document exhibiting an overbar (PC_CS for example) indicates that the signal is active low.

UDA1350ATSN2

Vendor:PHIPackage Cooled:48000D/C:00+

1. ISA bus group pins are powered by VCC1 power rail. 2. PC_D pads have 4 mA drive capabilities; other output pads have 16 mA drive capabilities. 3. To interface with PC ISA bus, VCC1 should be connected to 5V power and PC_D bus should be buffered. Direction is given by PC_RD signal. 4. Pin Names in this document exhibiting an overbar (PC_CS for example) indicates that the signal is active low.

UDA1350ATSN2B/ATS

During a reprogram cycle, the address locations and 128 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7. Once the end of a program cycle h...

UDA1351H/N1

Vendor:PHIPackage Cooled:N/AD/C:08+

The 20ETF.. FP soft recovery QUIETIR rectifier series has been optimized for combined short reverse recovery time and low forward voltage drop. The glass passivation ensures stable reliable operation in the most severe temperature and power cycling conditions.

UDA1351H/N1

Vendor:PHIPackage Cooled:N/AD/C:08+

The 20ETF.. FP soft recovery QUIETIR rectifier series has been optimized for combined short reverse recovery time and low forward voltage drop. The glass passivation ensures stable reliable operation in the most severe temperature and power cycling conditions.

UDA1351TS

Vendor:PHIPackage Cooled:SSOP-28D/C:N/A

Figure 1 shows a typical soldering profile for the D2 and D3 Packages when soldering a to a printed circuit board. The profile will vary from system to system and solders to solders. Factors that can affect the profile include the type of sol- dering system used, density and type of components on the board or substrate material being used. This profile shows temperature versus time. The two profiles descr...

UDA1351TS/N1.118

Vendor:availPackage Cooled:SSOP28D/C:00+

• Silicon epitaxial planar capacitance diodes with very wide effective capacitance variation for tuning the VHF range 41 ... 170 MHz in hyperband television tuners. • These diodes are available as singles or as matched sets of two or more units according to the tracking condition described in the table of characteristics.

UDA1351TS/N1.118

Vendor:availPackage Cooled:SSOP28D/C:00+

• Silicon epitaxial planar capacitance diodes with very wide effective capacitance variation for tuning the VHF range 41 ... 170 MHz in hyperband television tuners. • These diodes are available as singles or as matched sets of two or more units according to the tracking condition described in the table of characteristics.

UDA1351TS/N1A

Vendor:PHILIPSD/C:00+

DESCRIPTION The STV5346 decoder is a computer-controlled teletext device including an 8 page internal mem- ory. Data slicing and capturing extracts the teletext information embedded in the composite video sig- nal. Control is accomplished via a two wire serial I2C bus ®. Internal ROM provides a character set suitable to display text using up to seven national languages. Different ROM versions wi...

UDA1351TSN1512

UDA1352H/104

Vendor:QFP/64Package Cooled:PHILIPSD/C:900

Split supplies of 3.3V and 2.5V are used. The 3.3V power supply powers a portion of the I/O and the core. The 2.5V is used to power the remaining outputs (CPU and APIC). 2.5V signaling follows JEDEC standard 8-X. Power sequencing of the 3.3V and 2.5V supplies is not required.

UDA1352H/106

Vendor:PHIPackage Cooled:QFP/64D/C:03+

NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage rating...

UDA1352HL/N2

Vendor:PHILIPSPackage Cooled:TQFPD/C:2002

Chip Erase is a six-bus cycle operation. The automatic erase begins on the rising edge of the last WE pulse. Chip Erase does not alter the data of the protected sectors. After the full chip erase the device will return back to the read mode. The hardware reset during Chip Erase will stop the erase but the data will be of unknown state. Any command during Chip Erase except Erase Suspend will be ignored.

UDA1355H/N2.557

UDA1355HN2518

UDA1360

Vendor:PHILIPSPackage Cooled:TSSOP16

(For 5V Supply, Typical Unless Otherwise Noted) n Fixed inverting gain available−1,−2,−5,−10 n DC gain accuracy @2.7V supply LMV101/102/1052% (typ) LMV1106% (typ) n Space saving packagesSC70-5 & SOT23-5 n Industrial temperature range−40˚C to +85˚C n Low supply current130µA n Rail-to-Rail output swing n Guaranteed 2.7V and 5V performance

UDA1360T

D/C:07+

The device is compatible with the JEDEC single power-supply Flash command set standard. Com- mands are written to the command register using standard microprocessor write timings, from where they are routed to an internal state-machine that controls the erase and programming circuits. De- vice programming is performed a byte at a time by executing the four-cycle Program Command. This initiates an i...

UDA1361TS/N1118

NOTES: 1. The SA56004X is optimized for 3.3 VDD operation. 2. Definition of Under Voltage Lockout (UVL): The value of VDD below which the internal A/D converter is disabled. This is designed to be a minimum of 200 mV above the power-on-reset. During the time that it is disabled, the temperature that is in the read temperature registers will remain at the value that it was before the A/D was disabled. Th...

UDA1361TSN1

Vendor:PHIPackage Cooled:14759D/C:01/P4

The devices low VCC detection circuitry protects the users system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds are available, however, Xicors unique circuits allow the threshold to be repro- grammed to meet custom requirement...

UDA1361TSN1.112

The switch is turned on by a single enable (OE) input. When OE is LOW, the switch is on and port A is connnected to port B. When OE is HIGH, the switch between port A and port B is open and the B port is precharged to BIASV through the equivalent of a 10k-ohm resistor.

UDA1380HN

D/C:07+

100KEP PECL/ECL compatible differential output. PECL/ECL termination is with a 50Ω resistor to VCC C2V. Unused single-ended outputs must have a balanced load. For ACCcoupled applications, the output stage emitter follower must have a DC current path to ground. See Termination section.

UDA1380HN/N1

Vendor:PHIPackage Cooled:QFND/C:0217+

secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data Customer lockable: Sector is one-time programmable. Once sector is locked, data cannot be changed.

UDA1380HN/N2118

All formulas are simplified. Refer to the last paragraph of this subsection about the actual output voltage. The following sequence describes the basic operation of the tripler by showing how the voltage at the 2 and 3 nodes, V2 and V3, increases. Q2 turns on, completing the ground path to charge C1 (and the 2 node) to the supply voltage, less a diode voltage drop. V2 (charging) = VIN C VD1 After Q2...

UDA1380TT.

UDA1384H

Vendor:PHILIPSPackage Cooled:QFPD/C:08+09+

The microcontrollers have 2 software-selectable modes of reduced activity and 8 bit clock prescaler for further reduction in power consumption. In Idle mode, the CPU is frozen while the peripherals and the interrupt system are still operating. In the Power- down mode, the RAM is saved and all other functions are inoperative.

UDA1384N/N1

Vendor:PHIPackage Cooled:QFPD/C:QFP

The ML2250 family is a 2-channel mixing speech synthesis device with an on-chip voice data (i.e., phrases) storing mask ROM and a flash memory. Besides playing the built-in voice data, this device can output voice data that is input from outside the device. This ML2250 family allows to select the playback method from the 8-bit PCM, non-linear 8-bit PCM, 16-bit PCM, 2-bit ADPCM2, and 4-bit ADPCM2 algorithm...

UDA1384N/N1

Vendor:PHIPackage Cooled:05+D/C:05+

The ML2250 family is a 2-channel mixing speech synthesis device with an on-chip voice data (i.e., phrases) storing mask ROM and a flash memory. Besides playing the built-in voice data, this device can output voice data that is input from outside the device. This ML2250 family allows to select the playback method from the 8-bit PCM, non-linear 8-bit PCM, 16-bit PCM, 2-bit ADPCM2, and 4-bit ADPCM2 algorithm...

UDA1431T

Vendor:PHILIPPackage Cooled:228D/C:05+

Select the desire reference voltage to be detected by serial data from the MCU. The input voltage level of IN1~IN4 will be magnified 4 times using selected reference voltage as a center. This magnified data will be return to the A-D input port of the MCU. As result, accuracy of the A-D converter of the MCU will be increased by 2 bit.

UDA2917EBTR

Vendor:ALLPackage Cooled:500

PWI is connected to the inverting input of the receive driver. The receive driver output is connected to the AOUTC pin. Thus, a receive level can be adjusted with the pins PWI, AOUTC, and VFO described above. The output of AOUT+ is inverted with respect to the output of AOUTC with a gain of 1. The output signal amplitudes are a maximum of 2.0 VPP. These outputs, above and below the signal ground voltage (VDD...

UDA3000HL/N1

UDA5.6F

Vendor:UNIZONPackage Cooled:SOT23D/C:N/A

BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot

UDA5.6F

Vendor:UNIZONPackage Cooled:N/A

BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot