W29EE512T-90

Vendor:10800Package Cooled:WINBOND

The Am29PDL640G is a 64 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device orga- nized as 4 Mwords. The device is offered in 63- or 80-ball Fine-pitch BGA packages. The word-wide data (x16) ap- pears on DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V VPP is not required for write or erase operations.

W29EE512T-90

Vendor:10800Package Cooled:2000

The Am29PDL640G is a 64 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device orga- nized as 4 Mwords. The device is offered in 63- or 80-ball Fine-pitch BGA packages. The word-wide data (x16) ap- pears on DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V VPP is not required for write or erase operations.

W29F002TPC-120

Vendor:WINBONDPackage Cooled:2000

W29F020T-90B

W29F040-90

Package Cooled:QFP

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except d...

W29F040B-120K1

Vendor:10800Package Cooled:WINBOND

The Hynix HYM71V8M655B(L)T6 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 64Mbytes memory. The Hynix HYM71V8M655B(L)T6 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.

W29F040B-70

Vendor:10800Package Cooled:WINBOND

(MAX2700/MAX2701 EV kit (Figure 3), VCC = +2.7V to +3.3V, SHDN = GAIN_SET = VCC, X2_EN = GND, VAGC = 1.25V, CEXT+ con- nected to CEXT-; no RF input signals applied; RFIN, LNAIN, LO inputs are terminated with 50Ω, LNAOUT connected to VCC through a 10nH inductor; MIX_I, MIX_Q, QIN1+, QIN1-, QOUT1, IIN1+, IIN1-, IOUT1, QIN2+, QIN2-, QOUT2, IIN2+, IIN2-, IOUT2 pins are unconnected; TA = -40C to +85C, unless ...

W29F102P-50B

W29F102P-55B

W29F102P-70

Vendor:some stockPackage Cooled:PLCCD/C:original stock

Master mode and snapshot mode output signal. Active HIGH during readout. The two-wire serial interface register setting switches this pin between input and output. Master mode and snapshot mode output signal. Active HIGH when image data are on data output bus. The two-wire serial interface register setting switches this pin between input and output. Master mode output signal. Active HIGH during exposure...

W29F102Q-45

Vendor:WinbontPackage Cooled:TSOP40D/C:99+

Referring to the Functional Block Diagram, the RF input stage is a differential amplifier, so that the input impedance is high. The triggering threshold at the RF amplifier input is about 15 µV at 1 MHz. This means that a pulsed RF input signal of 15 µV will exceed the threshold and trigger the blanker. The external capacitor at the dV/dt detector circuit (C13) is selected so that audio sign...

W29F102Q50

Vendor:WINBOND Package Cooled:TSOP40D/C:2006

The TLC3541 and TLC3545 are designed to operate with low power consumption. The power saving feature is further enhanced with an auto-power down mode. This product family features a high-speed serial link to modern host processors with an external SCLK up to 15 MHz. Both families use a built-in oscillator as the conversion clock, providing a 2.67 µs maximum conversion time.

W29F102Q55

Vendor:WINBOND Package Cooled:TSOP40D/C:2006

The MAX9765/MAX9766/MAX9767 family combines speaker, headphone, and microphone amplifiers, all in a small thin QFN package. The MAX9765 is targeted at stereo speaker playback applications and includes a stereo bridge-tied load (BTL) speaker amp, stereo headphone amp, single-ended output mic amp, input MUX, and I 2C control. The MAX9766 is targeted at mono speaker playback applications and includes a mono B...

W29F102Q-55

Vendor:N/APackage Cooled:2000D/C:08+09+

The line based adaptive comb filter in the TMC22x5yA adds or subtracts the high frequency data from three adjacent field lines to produce the average of the high frequency luminance by canceling the chrominance signals, which in flat fields of color are 180 degrees apart. Unfortunately flat fields of color are rare and, when vertical transitions in the picture occur, ...

W29F102Q-55B

W29F102Q-70

W29F102Q-70B

W29L040P-90B

Vendor:LINEARPackage Cooled:D/SD/C:05+06+07+

W29ZZ512P-70

Vendor:WINBONDPackage Cooled:1000

W2A43A100KAT2A

Vendor:AVXPackage Cooled:0805-100KD/C:08+

Output for control of the variable output amplifiers. When the MODE pin (34) is a logic high, the MODE_OUT pin is driven low. When the MODE pin (34) is a logic low, the MODE_OUT pin is driven high. This pin is intended for MUTE control of an external headphone amplifier. Leave unconnected when not used for headphone amplifier control.

W2A45A100KAT2A

W2A45C103KAT2A

W2A45C103MAT2A

Vendor:AVX

W2A46C474MAT2A

D/C:184000

The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK . A Delay Locked Loop (DLL) circuit is driven from the clock input and output timing for read operations is syn- chronized to the input clock.

W2A46D684MAT2A

Package Cooled:0402X4D/C:52000

The 1-wire serial communication port (5Kb/s) allows an external processor to read and write the internal registers of the bq2016. Communication with the bq2016 is useful for pack testing or host processing of the available battery information. The internal registers include available battery capacity, voltage, temperature, current, and battery status. The RBI input maintains the register set in the event ...

W2A4YC103MAT2A

Vendor:N/APackage Cooled:0402X4D/C:3000

W2A4YC471MAT2A

Vendor:AVXD/C:06+

When handling individual devices (which are not yet mounted on a circuit board), be sure that the environment is protected against electrostatic electricity. Operators should wear anti-static clothing, and containers and other objects that come into direct contact with devices should be made of anti-static materials. The Channel-to-Ambient thermal resistance Rth (ch-a) and the drain power dissipation PD va...

W2A4ZC103MAT1A

Vendor:AVXPackage Cooled:SMDD/C:2008+

When one of the cell voltages exceeds V(PROTECT), an internal current source begins to charge the capacitor, C(DELAY), connected to the CD pin. If the voltage at the CD pin, VCD, reaches 1.2 V, the OUT pin is activated and transitions high. An externally connected NCH FET is activiated and blows the external fuse in the positive battery rail, see Figure 1.

W2A4ZC104MAT2A

AC Coupled Single Supply Operation Figures 3 and 4 show possible non-inverting and inverting configurations for input signals that go below ground. The input is AC coupled to prevent the need for level shifting the input signal at the source. The resistive voltage divider biases the non-inverting input to VCC 2 = 2.5V.

W2A4ZD104MAT2A

Vendor:N/APackage Cooled:0402X4

It must also be noted that in (noninverting) gain configurations (with low values of gain resistor), a high level of input overdrive can result in a large input error current, which may then result in a significant power dissipation in the input stage. This power must be included when computing the junction temperature rise due to total internal power.

W2A4ZD104MAT2A

Vendor:AVXPackage Cooled:N/AD/C:1566

It must also be noted that in (noninverting) gain configurations (with low values of gain resistor), a high level of input overdrive can result in a large input error current, which may then result in a significant power dissipation in the input stage. This power must be included when computing the junction temperature rise due to total internal power.

W2B-3DFK200BTA

Vendor:N/APackage Cooled:N/AD/C:99

• High efficient InGaN technology • Chromaticity Coordinate categorized according to CIE1931 per packing unit • Luminous intensity ratio in one packing unit IVmax/IVmin 1.6 • Typical color temperature 5500 K • ESD class 1 • EIA and ICE standard package • Compatible with infrared, vapor phase and wave solder processes according to CECC • Available ...

W2B-3DFK200GDA

W2B-3DFK233GDA

W2D15A240A

Vendor:AVXD/C:02+

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ARM7TDMI is a trademark of Advanced RISC Machines (ARM) Limited.

W2D15A240A

Vendor:AVXPackage Cooled:0805电容D/C:02+

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ARM7TDMI is a trademark of Advanced RISC Machines (ARM) Limited.

W2-DSB010-TA \W2

W2F11A1018AT1A

Vendor:AVXPackage Cooled:0805-100PD/C:08+

Applications • Digital fieldbus isolation: DeviceNet, SDS, Profibus • AC plasma display panel level shifting • Multiplexed data transmission • Computer peripheral interface • Microprocessor system interface

W2F11A2218AT

n Memory mapped I/O n Software selectable I/O options (TRI-STATE ® Output, Push-Pull Output, Weak Pull-Up Input, High Impedance Input) n Up to 8 high current outputs n Schmitt trigger inputs on ports G and L n Packages: 44 PQFP with 40 I/O pins 44 PLCC with 40 I/O pins 40 DIP with 36 I/O pins 28 DIP/SOIC with 24 I/O pins

W2F11A2218AT1F

W2F15C1038AT1A

D/C:07+

This quad monolithic silicon voltage suppressor is designed for applications requiring transient overvoltage protection capability. It is intended for use in voltage and ESD sensitive equipment such as computers, printers, business machines, communication systems, medical equipment, and other applications. Its quad junction common anode design protects four separate lines using only one package. These ...

W2FC-SR 0661RA

Vendor:OMRONPackage Cooled:n/aD/C:08+

W2G110-AM41-92

W2GD-10

Vendor:OMRONPackage Cooled:06+D/C:module

The CIP 3250A is a new CMOS IC that contains on a single chip the entire circuitry to interface analog YUV/ RGB/Fast Blank to a digital YUV system. The Fast Blank signal is used to control a soft mixer between the digi- tized RGB and an external digital YUV source. The CIP supports various output formats such as YUV 4:1:1/4:2:2 or RGB 4:4:4.

W2L16C684MAT1S-COC

W2L16D105MAQ1AJ

D/C:07+

W2L16D474MAT15

D/C:07+

NOTES: Add a -1 suffix for internal metallurgical bond. When ordering devices with tighter tolerances than specified for the VZ voltage nominal of 6.35 V, add a hyphened suffix to the part number for desired tolerance, e.g. 1N827-1-2%, 1N829-1-1%, 1N829A-1%, 1N829A-1-1%, etc. oZener impedance measured by superimposing 0.75 mA ac rms on 7.5 mA dc @ 25 C. The maximum allowable change observed over the ent...

W2L1YC473MAT1S

W2M-120-A2A-3B3B

W2S110AO01-67

W3000

W3000C

Vendor:LUCENTPackage Cooled:TSSOPD/C:SSOP-16

nous Preset/Reset of the macrocells flip-flop. Note that the Power-on Reset leaves all macrocells in the "zero" state when power is properly applied, and that the Preset/Reset feature for each macrocell can also be disabled. Control terms CT2 and CT3 can be used as a clock signal to the flip-flops of the macrocells, and as the Output Enable of the macrocells output buffer. Control terms CT4 a...

W3000C

Vendor:LUCENTPackage Cooled:00+D/C:SSOP-16

nous Preset/Reset of the macrocells flip-flop. Note that the Power-on Reset leaves all macrocells in the "zero" state when power is properly applied, and that the Preset/Reset feature for each macrocell can also be disabled. Control terms CT2 and CT3 can be used as a clock signal to the flip-flops of the macrocells, and as the Output Enable of the macrocells output buffer. Control terms CT4 a...

W3000D

Vendor:AGRPackage Cooled:TSSOPD/C:N/A

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input an...

W300C

W300H

Vendor:CYPRESSPackage Cooled:SSOP-56D/C:00+

Hynix HYMD132G725B(L)8-M/K/H/L series is registered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 32Mx72 high-speed memory arrays. Hynix HYMD132G725B(L)8-M/ K/H/L series consists of eighteen 16Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD132G725B(L)8-M/K/H/L series provide a high performance 8-byte interface in 5....

W3011FCL22780

W3013BCL

Vendor:LUCENTPackage Cooled:SSOPD/C:N/A

The MAU100 series has limitation of maximum connected capacitance at the output. The power module may be operated in current limiting mode during start-up, affecting the ramp-up and the startup time. For optimum performance we recommend 100uF maximum capacitive load for dual outputs and 220uF capacitive load for single outputs. The maximum capacitance can be found in the data.

W302H

Vendor:CYPRESSPackage Cooled:SSOPD/C:00+

Over Vin range Measured at center of case, auto-reset Surface temprature of module pins or case Per Bellcore TR-332 50% stress, Ta =40C, ground benign Mil-STD-883D, Method 2002.3 Half Sine, mounted to a fixture Mil-STD-883D, Method 2007.2,Suffix N 20-2000 Hz, PCB mountedSuffixes A, C Materials meet UL 94V-0

W302H

Vendor:CYPRESSPackage Cooled:SSOPD/C:00+

Over Vin range Measured at center of case, auto-reset Surface temprature of module pins or case Per Bellcore TR-332 50% stress, Ta =40C, ground benign Mil-STD-883D, Method 2002.3 Half Sine, mounted to a fixture Mil-STD-883D, Method 2007.2,Suffix N 20-2000 Hz, PCB mountedSuffixes A, C Materials meet UL 94V-0

W3030A

Vendor:LUCENTPackage Cooled:QFP0707-32D/C:00+

W30404

Vendor:N/APackage Cooled:N/AD/C:04+

W305A

W305BH

Vendor:CYPackage Cooled:IC WORKSD/C:05+

The NCP1501 is a dual mode regulator that operates either as a PWM Buck Converter or as a Low Drop Out Linear Regulator. If a synchronization signal is present, the NCP1501 operates as a current mode PWM converter with synchronous rectification. The synchronization signal allows the user to control the location of the spurious frequency noise generated by a PWM converter. Linear mode is active when a s...

W305BHT

Vendor:CYPackage Cooled:SOP56D/C:02+

The pre-emphasis is used to compensate for long or lossy transmission media. Separate pins are provided for each output to minimize power consumption. Pre-emphasis is programmable to be off or to preset values per the Pre- emphasis Control Selection Table.

W305BHT

Vendor:CYPackage Cooled:02+D/C:02+

The pre-emphasis is used to compensate for long or lossy transmission media. Separate pins are provided for each output to minimize power consumption. Pre-emphasis is programmable to be off or to preset values per the Pre- emphasis Control Selection Table.

W30C491-L

Vendor:WINBONDPackage Cooled:2005

• Industrial applications for daisy chaining multiple devices • Industrial control in latency critical applications • Port redundancy and port monitoring • Security cameras • VoIP phone and ATA adaptors

W3100A-LF

D/C:07+

External I/O for Timer/Counter 2 Timer/Counter 2 Capture/Reload Trigger Serial Port 1 Input Serial Port 1 Output External Interrupt 2 (Positive Edge Detect) External Interrupt 3 (Negative Edge Detect) External Interrupt 4 (Postive Edge Detect) External Interrupt 5 (Negative Edge Detect)

W310H

Vendor:CYPRESSPackage Cooled:IC WORKSD/C:0202+

FF/IR and AF are synchronized to the port clock that writes data into its array. EF/OR and AE are synchronized to the port clock that reads data from its array. Programmable offset for AE and AF are loaded in parallel using Port A or in serial via the SD input. Three default offset settings are also provided. The AE threshold can be set at 8, 16, or 64 locations from the empty boundary and AF threshold...

W310R27F

W312-02

Package Cooled:9389

W312H

Vendor:CYPRESSPackage Cooled:SSOP-48D/C:00+

Two different interfaces are supported on the network side. The first is a conventional seven wire ENDEC interface that connects to the LAN83C694 for 10BASE-T and coax 10 Mbps Ethernet networks. The second interface follows the MII (Media Independent Interface) specification draft standard, consisting of 4 bit wide data transfers at the nibble rate. This interface is applicable to 10 Mbps or 100 Mbps networks...

W3150A+

Vendor:WiznetD/C:08+

W31R27FA1

6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin ) ICC. CPD is used to determine the no−load dynamic power consumption; PD = CPD VCC2 fin ) ICC VCC.

W320-02H

Vendor:CYPRESSPackage Cooled:SSOP-56D/C:01+

PnP Card Autoconfiguration Sequence Compliant Supports Two Logical Devices Decodes 10-Bit I/O Address Location With Programmable 1-, 2-, 4-, 8-, 16-Byte Block Size Maps Interrupts to Six Interrupt Outputs IRQ3C IRQ7 and IRQ9 Provides Simple 3-Terminal Interface to SGS-Thomson EEPROM 2K/4K ST93C56/66 or Equivalent 3-State Output EEPROM Interface Allows the EEPROM to be Accessed by Another Controller Pr...

W320-02X

Vendor:CYPRESSPackage Cooled:TSSOP-56D/C:00+

Ground. Oscillator input. Oscillator output. Active high reset. (with internal pull-down resistor) Key scan input 0. (Schmitt-trigger with 10K/33K/50K pull-up resistor) Key scan input 1. (Schmitt-trigger with 10K/33K/50K pull-up resistor) Key scan input 2. (Schmitt-trigger with 10K/33K/50K pull-up resistor) Key scan input 3. (Schmitt-trigger with 10K/33K/50K pull-up resistor) Key scan input 4. (Schmitt-trig...

W320-02X

Vendor:CYPRESSPackage Cooled:TSSOP-56D/C:00+

Ground. Oscillator input. Oscillator output. Active high reset. (with internal pull-down resistor) Key scan input 0. (Schmitt-trigger with 10K/33K/50K pull-up resistor) Key scan input 1. (Schmitt-trigger with 10K/33K/50K pull-up resistor) Key scan input 2. (Schmitt-trigger with 10K/33K/50K pull-up resistor) Key scan input 3. (Schmitt-trigger with 10K/33K/50K pull-up resistor) Key scan input 4. (Schmitt-trig...

W32003H

Vendor:CYPPackage Cooled:2818D/C:0138+

pins together. When the PE input is LOW, the LS195A appears as four common clocked D flip-flops. The data on the parallel inputs P0, P1, P2, P3 is transferred to the respective Q0, Q1, Q2, Q 3 outputs following the LOW to HIGH clock transition. Shift left operations (Q3 Q2) can be achieved by tying the Qn Outputs to the PnC1 inputs and holding the PE input LOW. All serial and parallel data transfers a...

W320-03HT

Vendor:CYPPackage Cooled:SOPD/C:07+

I and Q channel LVDS Data Outputs that are not delayed in the output demultiplexer. Compared with the DId and DQd outputs, these outputs represent the later time samples. These outputs should always be terminated with a 100Ω differential resistor.

W320-03XTWN

Vendor:CYPRESSPackage Cooled:1000D/C:01+

W320-04H

Vendor:CYPRESSPackage Cooled:07+D/C:20

• Supply voltage: 3 V/5 V/7.5 V • Built-in a 5-volt power-supply source driver for TFT type LCD • Low consumption power (typ. 200 mW) • Supporting the NTSC, PAL, PAL-M and PAL-N sys- tems • Supporting composite, component and color differen- tial signal input • Video signal, analog RGB (2 systems) One is for OSD (analog/digital). • Each mode setting is possible with...

W320-04HT

Vendor:IN STOCKPackage Cooled:SSOPD/C:CYPRESS

The 28F400B3, 28F800/008B3, 28F160/016B3, 38F320/032B3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

W32004X

Vendor:IC WORKSPackage Cooled:786D/C:01+

Programmable Refresh Timer for DP84xx DRAM Controller NS32008 16 32 to DP8409A 17 18 19 28 29 Interface NS32332 to DP8417 18 19 28 29 Interface 68000 08 10 to DP8409A 17 18 19 28 29 Interface (up to 8 MHz) 68000 08 10 to DP8409A 17 18 19 28 29 Interface (up to 12 5 MHz) 68020 to DP8417 18 19 28 29 Interface 8086 88 186 188 to DP8409A 17 18 19 28 29 Interface 80286 to DP8409A 17 18 19 28 29 Interface 16...

W32004X

Vendor:IC WORKSPackage Cooled:786D/C:01+

Programmable Refresh Timer for DP84xx DRAM Controller NS32008 16 32 to DP8409A 17 18 19 28 29 Interface NS32332 to DP8417 18 19 28 29 Interface 68000 08 10 to DP8409A 17 18 19 28 29 Interface (up to 8 MHz) 68000 08 10 to DP8409A 17 18 19 28 29 Interface (up to 12 5 MHz) 68020 to DP8417 18 19 28 29 Interface 8086 88 186 188 to DP8409A 17 18 19 28 29 Interface 80286 to DP8409A 17 18 19 28 29 Interface 16...

W320-04X

Vendor:advantage seriesPackage Cooled:TSSOPD/C:original stock

CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures. UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 SABER© is a Copyright of Analogy Inc.

W320-04XPHI

Vendor:CYPRESSPackage Cooled:217D/C:01+

W320H

Package Cooled:SMD

• Available with Colon for Clock Display • Compact Package 0.300 x 0.500 inches Leads on 2.54 mm (0.1 inch) Centers • Choice of Colors AlGaAs Red, High Efficiency Red, Yellow, Green, Orange • Excellent Appearance Evenly Lighted Segments Mitered Corners on Segments Surface Color Gives Optimum Contrast 50 Viewing Angle • Design Flexibility Common ...

W32-0RX0251-0G

JTAG In-System Programming (ISP) reduces de- velopment time, simplifies manufacturing flow, and lowers the cost of field upgrades. The JTAG ISP interface eliminates the need for sockets and pre-programmed memory and logic devices. For manufacturing, end products may be assembled with a blank DSM device soldered to the circuit board and programmed at the end of the manufac- turing line in 10 to 20 s...

W320X

Vendor:CYPRESSPackage Cooled:TSSOP-48D/C:00+

The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The ...

W320X

Vendor:CYPRESSPackage Cooled:TSSOP-48D/C:00+

The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The ...

W320XA19

Note 5: Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

W32-2RX0447-1B

W3285Q

Vendor:PLCC-28

The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontrol- ler fails to restart a timer within a selectable time-out interval, the device activates the RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power.

W32C42-05G

Package Cooled:SMD

The W32C42-05G is an integrated circuit in advanced CMOS technology for demodulation and decoding of a DAB signal according to ETS 300 401. The channel decoder part includes the main features OFDM demodulation and time and frequency synchronization synchronization algorithms on OAK DSP core platform. The audio source decoder supports ISO MPEG 1, 2 layer II half and full sampling rate. The data decoder...

W32-ORX251-OG

Vendor:NECD/C:98

The DS1543 is in the write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout the cycle. CE and WE must return inactive for a minimum of tWR prior to the initiation of a subsequent read or write cycle. Data in must be valid tDS prior to the end of the write and remain va...

W32-ORX251-OG

Vendor:NECD/C:98

The DS1543 is in the write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout the cycle. CE and WE must return inactive for a minimum of tWR prior to the initiation of a subsequent read or write cycle. Data in must be valid tDS prior to the end of the write and remain va...

W33173CH

Package Cooled:裸芯片D/C:07+

The DS1270 devices execute a write cycle whenever WE and CE signals are active (low) after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) b...

W33274

This 64kbit memory array can be partitioned into pass- word protected or non-password protected areas. When password protected, the contents are readable after sending a Memory Read password. The contents of a password protected portion of the memory array are writeable with a Memory Write Password. This array is re-writable up to the limit of the EEPROM endurance.

W33C93BJM

Vendor:WDCPackage Cooled:PLCCD/C:95+

W33H3CH