W78E52BP-24/40

Vendor:WinbondPackage Cooled:PLCC

NON-HERMETIC LOW COST CERAMIC 70mil PACKAGE +21.5dBm TYPICAL OUTPUT POWER 8.0dB TYPICAL POWER GAIN AT 18GHz TYPICAL 0.85dB NOISE FIGURE AND 11.0dB ASSOCIATED GAIN AT 12GHz 0.3 X 250 MICRON RECESSED MUSHROOM GATE Si3N4 PASSIVATION ADVANCED EPITAXIAL HETEROJUNCTION PROFILE PROVIDES EXTRA HIGH POWER EFFICIENCY, AND HIGH RELIABILITY

W78E52BP-40 PLCC 30/TUBE

W78E52C40

W78E52C-40

Vendor:WINBONDD/C:09+

This stand alone controller provides several special enhancements to satisfy the needs for low power standby and protection features. In standby mode frequency reduction is used to lower the power consumption and provide a stable output voltage in this mode. The frequency reduction is limited to 20kHz / 21.5 kHz (typ.) to avoid audible noise. In case of failure modes like open loop, overvoltage or ov...

W78E52CF-40

Vendor:WINBONDPackage Cooled:QFP-44

ACCURACY Linearity Error(1) Linearity Match Differential Linearity Error Monotonicity, TMIN to TMAX Zero Scale Error Zero Scale Error Drift Full-Scale Error Full-Scale Error Drift Zero Scale Matching Full-Scale Matching Power Supply Rejection Ratio (PSRR)

W78E52CP-40

Vendor:WINBONDPackage Cooled:PLCC

2-V to 5.5-V VCC Operation Supports Mixed-Mode Voltage Operation on All Ports High On-Off Output-Voltage Ratio Low Crosstalk Between Switches Individual Switch Controls Extremely Low Input Current ESD Protection Exceeds JESD 22 C 2000-V Human-Body Model (A114-A) C 200-V Machine Model (A115-A) C 1000-V Charged-Device Model (C101)

W78E52CP-40

Vendor:WINBONDD/C:2005

2-V to 5.5-V VCC Operation Supports Mixed-Mode Voltage Operation on All Ports High On-Off Output-Voltage Ratio Low Crosstalk Between Switches Individual Switch Controls Extremely Low Input Current ESD Protection Exceeds JESD 22 C 2000-V Human-Body Model (A114-A) C 200-V Machine Model (A115-A) C 1000-V Charged-Device Model (C101)

W78E52F-24

Vendor:WINBONDPackage Cooled:QFPD/C:01+

ISB = 2 mA Fully asynchronous and simultaneous read and write operation Empty, Full, and Programmable Almost Empty and Almost Full status flags TTL-compatible Retransmit function Output Enable (OE) pin Independent read and write enable pins Supports free-running 50% duty cycle clock inputs Width-Expansion Capability Depth-Expansion Capability through token-passing scheme (no external logic required) 6...

W78E52F-24

Vendor:IN STOCKPackage Cooled:01+D/C:WINBOND

ISB = 2 mA Fully asynchronous and simultaneous read and write operation Empty, Full, and Programmable Almost Empty and Almost Full status flags TTL-compatible Retransmit function Output Enable (OE) pin Independent read and write enable pins Supports free-running 50% duty cycle clock inputs Width-Expansion Capability Depth-Expansion Capability through token-passing scheme (no external logic required) 6...

W78E52P

Vendor:WinbondPackage Cooled:PLCCD/C:08+

Hynix HYMD232M646A(L)8-J/M/K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline Dual In-Line Memory Modules (SO-DIMMs) which are organized as 32Mx64 high-speed memory arrays. Hynix HYMD232M646A(L)8-J/M/K/H/L series consists of eight 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 200pin glass-epoxy substrate. Hynix HYMD232M646A(L)8-J/M/K/H/L series provide a high performance 8-b...

W78E52P24

The Hyundai HY5DU564022 is a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY5DU564022 is orga- nized as 4 banks of 16,777,216x4.

W78E52P-24

Package Cooled:WIN

Single 2.5V - 3.6V or 2.7V - 3.6V Supply Serial Peripheral Interface (SPI) Compatible 20 MHz Max Clock Frequency Page Program Operation C Single Cycle Reprogram (Erase and Program) C 4096 Pages (528 Bytes/Page) Main Memory Supports Page and Block Erase Operations Two 528-byte SRAM Data Buffers C Allows Receiving of Data while Reprogramming of Nonvolatile Memory Continuous Read Capability through Entire...

W78E52P-40

Vendor:WINBONDPackage Cooled:PLCC44D/C:08+

Converts Y, Cr, Cb data to analog RGB and composite or S-video and composite video Supports CCIR recommendations 601 and 656 All digital video encoding Selectable master/slave mode for sync signals Switchable chrominance bandwidth CCIR 624 PAL SMPTE or 170M NTSC compatible outputs GENLOCK mode I2C bus serial microprocessor interface Only VP5313 supports Macrovision anti-taping Rev. 7.01 Line 21...

W78E54

Vendor:WinbondPackage Cooled:PLCCD/C:08+

The Fairchild Switch FST16862 provides 20-bits of high- speed CMOS TTL-compatible bus switching. The low On Resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise.

W78E54-40

Vendor:WINBOND

When external capacitors are used with any I.C. regulator it is sometimes necessary to add protection diodes to prevent the capacitors from discharging through low current points into the regulator. Figure 18 shows the W78E54-40 with the recommended protection diodes for output voltages in excess of 25 V or high capacitance values (Co > 25uF, Cadj > 10uF). Diode D1 prevents Co from discharging thru the...

W78E54B-40DL

W78E54BP

Vendor:WINBONDD/C:04+

A random read requires a dummy byte write sequence to load in the data word address which is then clocked in and acknowledged by the EEPROM. The microcontroller must then generate another start con- dition. The microcontroller now initiates a current ad- dress read by sending a device address with the read/write select bit high. The EEPROM acknowl- edges the device address and serially clocks out the data w...

W78E54C-40

Vendor:availD/C:2007+

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input ...

W78E54P

Package Cooled:WINBONDD/C:04+

The high-side power transistor can only be turned on after a fixed time delay following the return to ground of the low-side power transistors gate. The low-side transistor can only be turned on after a fixed time delay following the high-side transistor turn-off signal.

W78E54P-40

Vendor:2000Package Cooled:WINBONDD/C:07+

• Master Synchronous Serial Port (MSSP) module supporting 3-wire SPI™ (all 4 modes) and I2C™ Master and Slave modes • Enhanced Addressable USART module: - Supports RS-485, RS-232 and LIN 1.2 - RS-232 operation using internal oscillator block (no external crystal required) - Auto-Wake-up on Start bit - Auto-Baud Detect • 10-bit, up to 13-channel Analog-to-Digital ...

W78E56

Vendor:WINBONDPackage Cooled:1000

Bass adjustment can be made by changing the values of the capacitor connected between BL1~BL2 and BR1~BR2. Please refer to Fig.7. The larger the capacitor value used, the frequency response curve shifts down. Like wise, the smaller the capacitor value, the frequency response curve shifts the opposite direction. In Fig.7, at 9dB different capacitor value exhibit different frequency responses. A capacitor...

W78E58/B-24/40

Vendor:WINBONDPackage Cooled:DIP

W78E58-24

Vendor:WinbondPackage Cooled:DIP40

When a negative voltage is applied to pins 8 and 9, there should be no abnormal operation of internal circuits between 0 and 6V. However, if a negative voltage exceeding -6V is applied, thyristor operation may result, so it is recommended that an external clamping diode be added.

W78E58-24P

Vendor:WINGBONDPackage Cooled:DIP

W78E58-40

Vendor:WINBONDPackage Cooled:DIP

Third-Order IMD Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Common-Mode Voltage Range Input Resistance

W78E58B

Vendor:WINBONDD/C:04+

Normally the PWM comparator will sense a ramp crossing a control voltage (error amp output) and termi- nate the pulse. Leading edge blanking (LEB) causes the PWM comparator to be ignored for a fixed amount of time after the start of the pulse. This allows noise in- herent with switched mode power conversion to be re- jected. The PWM ramp input may not require any filtering as result of leading edge b...

W78E58B/BP-40

Vendor:WINBONDPackage Cooled:ORG PACKINGD/C:08+

W78E58B-40

Vendor:WINBONDPackage Cooled:DIP

• Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 clock, OC-3 port and 155.52 Mbit/s application • Supports ITU-T G.813 Option 1 clocks • Supports ITU-T G.812 Type IV clocks • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface • Selectable reference inputs: 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 M...

W78E58BF-40

Vendor:availD/C:2007+

en = Noise Voltage of the Transistor referred to the input. (Figure 3) I = Noise Current of the Transistor referred to the input. n (Figure 4) K = Boltzmans Constant (1.38 x 10−23 j/K) T = Temperature of the Source Resistance (K) R = Source Resistance (W)

W78E58BP-24

Vendor:WINBONDD/C:1500

• High self-resonant frequency values. • High Q values at higher frequencies. • Molded construction provides superior strength and moisture resistance. • Wirewound construction. • Tape and reel packaging for automatic handling, 3,000/reel, EIA481. • Compatible with vapor phase and infrared reflow soldering.

W78E58BP-40

Vendor:WINBONDD/C:N/A

Level-triggered control input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes LOW, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock (unless SYNC is taken HIGH before this edge in which case the rising edge of SYNC acts as an interrupt and the write sequence is i...

W78E58P

Vendor:WINBONDD/C:08+

The W78E58P and W78E58P provide higher dynamic range and lower total harmonic distortion than our industry standard CS5321 modulator, while consuming signifi- cantly less power per channel. The modulators generate an oversampled serial bit stream at 512 kbits per second when operated from a clock frequency of 2.048 MHz. The W78E58P and W78E58P are available in a small 24-pin SSOP package, providing e...

W78E58P-24

D/C:02+

The MC100EPT622 is a 10- Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL (Positive ECL) levels are used only +3.3 V and ground are required. The device has an OR- ed enable input which can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs (ENTTL). If the inputs are left open, they will default to the enable state. The device design has been optimized for low channel- to- channel skew

W78E615BP

Vendor:WinbondPackage Cooled:PLCCD/C:08+

Whatever crossover current that might occur in the low-power drivers is dramatically reduced by the series resistor, R4. Additionally, driving the high-power complementary pair using this resistor divider scheme all but eliminates crossover current in this critical output driver. This increases both the drivers efficiency and its reliability.

W78E61D-40

Vendor:WinbondPackage Cooled:QFP-48D/C:1998+

Package Description 100-Lead LQFP 100-Lead LQFP 100-Lead CSPBGA 100-Lead CSPBGA 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 52-Lead LQFP 64-Lead LFCSP 52-Lead LQFP 64-Lead LFCSP 52-Lead LQFP 64-Lead LFCSP 52-Lead LQFP 64-Lead LFCSP 52-Lead LQFP 64-Lead LFCSP 52-Lead LQFP 64-Lead LFCSP

W78E62

The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry steals power whenever the I/O, RST , or VCC pins are high. When using the 1-Wire port in battery operate mode, RST and VCC provide no power since they are low. However, I/O will provide sufficient power as long as the specified timing and voltage requirements are met. The advantages of parasite power are two-fold: 1) by parasit...

W78E62B-40

Package Cooled:1000

+15 VOUT- is a regulated +15 volt output available for ex- ternal uses. Up to 25 mA is available at this pin. A 100 microfarad capacitor should be connected as close to this pin as possible and returned to GND along with a 0.22 micro- farad monolithic ceramic capacitor. CAUTION: See Voltage Regulator Power Dissipation.

W78E62B-40

Package Cooled:1000

+15 VOUT- is a regulated +15 volt output available for ex- ternal uses. Up to 25 mA is available at this pin. A 100 microfarad capacitor should be connected as close to this pin as possible and returned to GND along with a 0.22 micro- farad monolithic ceramic capacitor. CAUTION: See Voltage Regulator Power Dissipation.

W78E62BP

Vendor:WINBOWPackage Cooled:1000D/C:N/A

The Hitachi HN58S65A series is electrically erasable and programmable ROM organized as 8192-word 8-bit. It has realized high speed, low power consumption and high reliability by employing advanced MNOS memory technology and CMOS process and circuitry technology. They also have a 64-byte page programming function to make their write operations faster.

W78E62P-40

Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled low by the clock chip (indicating processor VTT voltage is stable), the clock chip

W78E632A-40PL

W78E65

Vendor:WinbondD/C:08+

W78E65F-40

Vendor:availD/C:2007+

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input ...

W78E671002

Vendor:WindondD/C:07/08+

W78E747E

Vendor:WINBONDPackage Cooled:2005D/C:500

The MAX 3000A device architecture is based on the linking of highCperformance LABs. LABs consist of 16Cmacrocell arrays, as shown in Figure 1. Multiple LABs are linked together via the PIA, a global bus that is fed by all dedicated input pins, I/O pins, and macrocells.

W78E747E

Vendor:WINBONDD/C:01+

The MAX 3000A device architecture is based on the linking of highCperformance LABs. LABs consist of 16Cmacrocell arrays, as shown in Figure 1. Multiple LABs are linked together via the PIA, a global bus that is fed by all dedicated input pins, I/O pins, and macrocells.

W78E767D-CF

Vendor:WINBONDD/C:01+

1: Care should be taken so as to not exceed the thermal dissipation capability of the package 2: Size your output capacitor to meet the transient loading requirement. If you have a very dynamic load, a lower ESR and larger value capacitor will improve the response to these load steps.

W78E767-SM

Vendor:WINBONDD/C:00+

The UCC3961 provides all the circuitry required on the primary side of a secondary-side controlled power supply. It features a free running 60-kHz to 360-kHz oscillator which is synchronizable to the secondary-side PWM signal and also has the ability to accept start/stop PWM commands from the isolating pulse-edge transformer (PET). The use of an extremely small and low-cost pulse transformer allows for h...

W78E812

Vendor:WINBONDPackage Cooled:DIPD/C:07+

Bidirectional TVS series for thru-hole mounting Suppresses transients up to 1500 watts @ 10/1000 µs (see Figure 1) Clamps transient in less than 100 pico seconds Working voltage (VWM) range 5.5 V to 185 V Hermetic sealed DO-13 metal package JAN/TX/TXV military qualifications also available per MIL-PRF-19500/507 for the tighter tolerance A suffix types by adding the JAN, JANTX, or JANTXV prefix, e.g. ...

W78E812P

Vendor:WINBONDPackage Cooled:PLCCD/C:04+

W78E858A40DL

Vendor:WinbondPackage Cooled:DIPD/C:06+

Description ground for substrate charge-pump (phase detector) output Colpitts oscillator and substrate ground Colpitts oscillator input (resonator connection) power for Colpitts oscillator power for LNA and PA external capacitor to stabilise LNA LNA first stage ground low noise RF amplifier (LNA) input LNA, PA and substrate ground power amplifier output external bias resistor for power amplifier mi...

W78E858A40DL

Vendor:WinbondPackage Cooled:DIPD/C:06+

Description ground for substrate charge-pump (phase detector) output Colpitts oscillator and substrate ground Colpitts oscillator input (resonator connection) power for Colpitts oscillator power for LNA and PA external capacitor to stabilise LNA LNA first stage ground low noise RF amplifier (LNA) input LNA, PA and substrate ground power amplifier output external bias resistor for power amplifier mi...

W78E858A40FL

Vendor:WinbondPackage Cooled:QFPD/C:06+

Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY sig- nals that the port is trying to access the same location currently being accessed by the other port. The Interrupt flag (INT) per- mits communication between ports or systems by means of a mail box. The semaphores are used to pass a ...

W78E858A40PL

Vendor:WinbondPackage Cooled:PLCCD/C:06+

NOTES: 1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics. 2. Per TTL-driven input (VIN = 3.4V, control inputs only). A, B, and AB pins do not contribute to ∆Icc. 3. This current applies to the control inputs only and represents the current required to switch internal capacitance at the specified frequency. The A, B, and AB inputs generate ...

W78E858P

Vendor:WINBONDPackage Cooled:PLCCD/C:04+

Note: It is natural to assume that with the addition of the averaging capacitor, the LOG AV output would become the average of the log of the absolute value of IIN. However, since the capacitor forces an ac ground at the emitter of the output transistor, the capacitor charging currents are proportional to the antilog of the voltage at the base of the output transistor. Since the base voltage of the outp...

W78E858P

Vendor:WINBONDPackage Cooled:PLCCD/C:04+

Note: It is natural to assume that with the addition of the averaging capacitor, the LOG AV output would become the average of the log of the absolute value of IIN. However, since the capacitor forces an ac ground at the emitter of the output transistor, the capacitor charging currents are proportional to the antilog of the voltage at the base of the output transistor. Since the base voltage of the outp...

W78ERD2A40DL

Vendor:WINBONDPackage Cooled:Winbond

• Vz-Iz characteristics are semilogarithmic linear from IZ = 1nA to 1mA and have sharper breakdown knees in a low current region, and also lower VZ temperature coefficients . • Low dynamic impedance and low noise in the low current region (approximately 1/10 lower than the current zeners).

W78ERD2A40DN

Package Cooled:DIP

Number of channels: 2 Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame Prioritized 16 message buffers for data and IDs Supports multiple messages Flexible configuration of acceptance filtering: Full bit compare / Full bit mask / Two partial bit masks Supports up to 1Mbps CAN bit timing setting: MB...

W78ERD2A40FL

Vendor:availPackage Cooled:WinbondD/C:2007+

The device has up to 37 software-configurable I/O pins, or- ganized into five ports called Port B, Port C, Port G, Port H, and Port I. Each pin can be configured to operate as a gen- eral-purpose input or general-purpose output. In addition, many I/O pins can be configured to operate as inputs or out- puts for on-chip peripheral modules such as the UART, tim- ers, or Microwire/SPI interface.

W78ERD2A40FN

Vendor:WINBONDPackage Cooled:PLCCD/C:0728vgc+

NOTES: (1) dBFS refers to dB below Full Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) Refer to Timing Diagram footnotes for the differential linearity performance conditions for the SO and SSOP packages. (4) IMD is referred to the larger of the two input signals. If referred to the peak envelope signal ( 0dB), the intermodulation products will be 7...

W78ERD2A40PL

Vendor:availPackage Cooled:WinbondD/C:2007+

PG# (15) The PG# pin is an open-drain, active-low output with no internal pull-up resistor. It can be used to switch a load or enable a DC/DC converter. PG# is enabled immediately after VGATE reaches VDD C VGT and the DRAIN SENSE voltage is less than 2.5V. Voltage on these pins cannot exceed 12V, as referenced to VSS.

W78I054A24DL WINBOND DIP 2007

W78IE52/P

Vendor:WINBONDPackage Cooled:ORG PACKINGD/C:08+

W78IE52P

Vendor:WINBONDD/C:2005

The e5130 contains 4 independent driver outputs with an ON resistance of typically 25 W (15 W) for the P-channel output transistors and typically 20 W (13 W) for the N-channel output transistors at a supply voltage of 1.5 V (3 V). To obtain a fast transi- tion of the outputs even for slow rise/fall time input signals, all digital inputs (IN1 to IN4) have a Schmitt-trigger characteristic with a hysteresis o...

W78IE54

Vendor:WINBONDD/C:07+

The HIP6601 and HIP6603 provide the user total flexibility in choosing the gate drive voltage. The HIP6601 lower gate drive is fixed to VCC [+12V], but the upper drive rail can range from 12V down to 5V depending on what voltage is applied to PVCC. The HIP6603 ties the upper and lower drive rails together. Simply applying a voltage from 5V up to 12V on PVCC will set both driver rail voltages.

W78IE54/P

Vendor:WINBONDPackage Cooled:ORG PACKINGD/C:08+

W78IE54P

Vendor:WINBONDPackage Cooled:PLCCD/C:07+

FEATURES High Slew Rate: 10 V/ s Min Fast Settling Time: 0.9 s to 0.1% Type Low Input Offset Voltage Drift: 10 V/ C Max Wide Bandwidth: 3.5 MHz Min Temperature-Compensated Input Bias Currents Guaranteed Input Bias Current: 18 nA Max (125 C) Bias Current Specified Warmed Up over Temperature Low Input Noise Current: 0.01 pA/Hz Type High Common-Mode Rejection Ratio 86 dB Min Pin Compatible with Standa...

W78IRD2A25DL

Notes: 1. The luminous intensity, I v, is measured at the peak of the spatial radiation pattern which may not be aligned with the mechanical axis of the lamp package. 2. The dominant wavelength, ëd, is derived from the CIE Chromatically Diagram and represents the perceived color of the device. 3. 1/2 is the off-axis angle where the luminous intensity is 1/2 the peak intensity.

W78IRD2A25DN

Vendor:in stockPackage Cooled:DIP-40D/C:06+

ST-BUS & GCI Mode for Sin/Rout (Input). When in ST-BUS or GCI operation, this pin in conjunction with the ENA2 pin, selects the proper mode for Sin/Rout pins (see ST-BUS and GCI Operation description). Connect this pin to Vss in SSI mode.

W78IRD2A25PL

High-speed ADC Family Companion Chip Selectable 1:2 or 1:4 DMUX Ratio Power Consumption: 2.6W LVDS Compatible Differential Data and Clock Inputs (100Ω Terminated) LVDS Compatible Differential Data and Data Ready Outputs Staggered or Simultaneous Data Outputs C 11th Bit = Ports A, B, C and D Clock in Staggered Mode Selectable Active Edge for Input and Output Clocks: C Only Rising: CLK and DR Mode C...

W78L051A24PL

Vendor:WINBONDPackage Cooled:PLCCD/C:04+

a8237 MegaCore function implementing a programmable direct memory access (DMA) controller Optimized for FLEX® architecture Provides four independent channels Offers static read/write or handshaking modes Includes direct bit set/reset capability Uses approximately 1,201 FLEX logic elements (LEs) Functionally based on the Intel 8237A and Harris 82C37A devices, except as noted in Variations & Clar...

W78L051C24DL

Vendor:WINBONDPackage Cooled:PLCCD/C:04+

The analog signal input. Internally biased at VDD/2, this input requires an external coupling capacitor. The source impedance should be less than 100 . Output channel noise levels will improve with an even lower source impedance. See Figure 3. Negative Supply No Connection The recovered analog signal is output at this pin. It is the buffered output of a lowpass filter and requires external compon...

W78L051C24DL P1089

W78L051C24FL

Vendor:WINBONDD/C:04+

A SCx/SDx downstream pair, or channel, is selected by the contents of the control register. This register is written after the PCA9544A has been addressed. The 3 LSBs of the control byte are used to determine which channel is to be selected. When a channel is selected, it will become active after a stop condition has been placed on the I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state...

W78L051C24FL

Vendor:WINBONDD/C:04+

A SCx/SDx downstream pair, or channel, is selected by the contents of the control register. This register is written after the PCA9544A has been addressed. The 3 LSBs of the control byte are used to determine which channel is to be selected. When a channel is selected, it will become active after a stop condition has been placed on the I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state...

W78L051C24PL

Vendor:WINBONDD/C:04+

other than the GSM Tx path, thus achiev- ing low loss. For the GSM Tx path, the SP7T + LPF structure can achieve lower loss than the diplexer structure since a LPF has smaller insertion loss than a diplexer. Furthermore, these devices achieve ultralow loss by using Sonys unique JPHEMT process. This contributes sig- nificantly to reduced current consumption during Tx and higher Rx sensitivity.

W78L052A24DL

Vendor:availPackage Cooled:PLCCD/C:2007+

The PCA9544A provides 4 interrupt inputs, one for each channel and one open drain interrupt output. When an interrupt is generated by any device, it will be detected by the PCA9544A and the interrupt output will be driven LOW. The channel need not be active for detection of the interrupt. A bit is also set in the control byte. Bits 4 C 7 of the control byte correspond to channels 0 C 3 of the PCA9544A, ...

W78L052A24FL

Vendor:NUVOTOND/C:134

BUFFER TO MAIN MEMORY PAGE PROGRAM WITH BUILT-IN ERASE: Data written into either buffer 1 or buffer 2 can be programmed into the main memory. To start the operation, an 8-bit opcode, 83H for buffer 1 or 86H for buffer 2, must be followed by the three reserved bits, 12 address bits (PA11 - PA0) that specify the page in the main memory to be written, and nine additional dont care bits. When a low-to-high tran...

W78L052A24FL

Vendor:WINBONDD/C:04+

BUFFER TO MAIN MEMORY PAGE PROGRAM WITH BUILT-IN ERASE: Data written into either buffer 1 or buffer 2 can be programmed into the main memory. To start the operation, an 8-bit opcode, 83H for buffer 1 or 86H for buffer 2, must be followed by the three reserved bits, 12 address bits (PA11 - PA0) that specify the page in the main memory to be written, and nine additional dont care bits. When a low-to-high tran...

W78L052A24FL WINBOND QFP 2007

W78L052A24PL

Vendor:WINBONDPackage Cooled:PLCCD/C:04+

These high intensity blue and green LEDs are based on InGaN material technology. InGaN is the most efficient and cost effective material for LEDs in the blue and green region of the spectrum. The 472 nm typical dominant wavelength for blue and 526 nm typical dominant wavelength for green are well suited to color mixing in full color signs.

W78L052C24DL

Vendor:WINBONDPackage Cooled:DIP-40D/C:04+

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

W78L052C24FL

Vendor:WINBONDD/C:04+

3Msps Sampling ADC with Two Simultaneous Differential Inputs 1.5Msps Throughput per Channel Low Power Dissipation: 14mW (Typ) 3V Single Supply Operation 2.5V Internal Bandgap Reference with External Overdrive 3-Wire Serial Interface Sleep (10µW) Shutdown Mode Nap (3mW) Shutdown Mode 80dB Common Mode Rejection at 100kHz 0V to 2.5V Unipolar Input Range Tiny 10-Lead MS Package

W78L052C24FL

Vendor:WINBONDPackage Cooled:QFP-44D/C:04+

3Msps Sampling ADC with Two Simultaneous Differential Inputs 1.5Msps Throughput per Channel Low Power Dissipation: 14mW (Typ) 3V Single Supply Operation 2.5V Internal Bandgap Reference with External Overdrive 3-Wire Serial Interface Sleep (10µW) Shutdown Mode Nap (3mW) Shutdown Mode 80dB Common Mode Rejection at 100kHz 0V to 2.5V Unipolar Input Range Tiny 10-Lead MS Package

W78L052C24PL

Vendor:WINBONDD/C:04+

Initiating A Conversion Please refer to Figure 4. The SP8480 was de- signed to require a minimum of control to per- form a 12-bit conversion. The control input used is R/C which tri-states the outputs and starts the conversion when low. The STATUS line indi- cates when a conversion is in process and when it is complete. The A control input is used to

W78L052C24PL

Vendor:WINBONDD/C:04+

Initiating A Conversion Please refer to Figure 4. The SP8480 was de- signed to require a minimum of control to per- form a 12-bit conversion. The control input used is R/C which tri-states the outputs and starts the conversion when low. The STATUS line indi- cates when a conversion is in process and when it is complete. The A control input is used to

W78L054A24DL

The LVT16373 and LVTH16373 contain sixteen D-type latches with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but inde- pendent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the Dn enters the latches. In this condition ...

W78L054A24DL

Vendor:WinbondD/C:06+

The LVT16373 and LVTH16373 contain sixteen D-type latches with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but inde- pendent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the Dn enters the latches. In this condition ...

W78L054A24FL

Genesis Microchip Inc. reserves the right to change or modify the information contained herein without notice. It is the customers responsibility to obtain the most recent revision of the document. Genesis Microchip Inc. makes no warranty for the use of its products and bears no responsibility for any errors or omissions that may appear in this document.

W78L054A24PL

Package Cooled:PLCC

Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

W78L054C24DL

Vendor:WINBONDD/C:04+

DESCRIPTION The HCC40192B, HCC40193B, (extended tem- perature range) and the HCF40192B, HCF40193B (intermediate temperature range) are monolithic in- tegrated circuits, available in 16-lead dual in-line plastic or ceramic package and platic micro pack- age. The HCC/HCF40192B Presettable BCD Up/Down Counter and the HCC/HCF40193B Pres- ettable Binary Up/Down Counter each consist of 4 synchronously clo...

W78L054C24DL WINBOND DIP 2007

W78L054C24FL

Vendor:NUVOTONPackage Cooled:QFPD/C:42

1) CPD is defined as the value of the ICs internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per gate)

W78L054C24FL WINBOND QFP 2007

W78L054C24PL

Vendor:WINBONDD/C:0744+

An enhanced, multiple cell security scheme is provided that prevents reading of the JEDEC programming file when secured. After the device has been secured using this mechanism, the only way to clear the security is to execute a bulk-erase instruction.

W78L054C24PL

Vendor:WINBONDPackage Cooled:PLCCD/C:0744+

An enhanced, multiple cell security scheme is provided that prevents reading of the JEDEC programming file when secured. After the device has been secured using this mechanism, the only way to clear the security is to execute a bulk-erase instruction.

W78L054C24PL WINBOND PLCC 2007

W78L058A24DL

Vendor:WINBONDD/C:04+

(1) S/N can be improved for common mode noise on internal and external signal transmission due to differential input/output. (2) CMRR (common mode rejection ratio):60 dB typ. (3) PSRR (power supply rejection ratio):80 dB typ. (4) Consumption current1.5mA typ.

W78L058A24DL

Vendor:WINBONDD/C:04+

(1) S/N can be improved for common mode noise on internal and external signal transmission due to differential input/output. (2) CMRR (common mode rejection ratio):60 dB typ. (3) PSRR (power supply rejection ratio):80 dB typ. (4) Consumption current1.5mA typ.

W78L058A24FL

Vendor:WINBONDPackage Cooled:QFPD/C:04+

Hynix HYMD216M726A(L)6-J/M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to iden- tify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.