WP91566L1N 103

Vendor:TIPackage Cooled:SOPD/C:0008#

WP91566L4N

Package Cooled:SMDD/C:97

Note) 1. At on-state when drain voltage exceeds the "Short circuit load protection voltage", output current begin to oscillate. 2. When drain voltage exceeds the "Drain clamp voltage" output MOS turn on, so drain voltage are clamped before the drain-source junction become breakdown.

WP91566L6N

The SY10EP31V is a D flip-flop with set and reset. The device is pin and functionally equivalent to the EL31 and LVEL31 devices. With AC performance much faster than the EL31 and LVEL31 devices, the EP31V is ideal for applications requiring the fastest AC performance available. Both SET and RESET inputs are asynchronous, level triggered signals. Data enters the master portion of the flip-flop when C...

WP91566L6N470

Package Cooled:08+D/C:07+

The RM3283 contains two discrete ARINC 429 receiver channels. Each channel contains three main sections: a resistor input network, a window comparator, and a logic output buffer stage. The first stage provides overvoltage protection and biases the signal using voltage dividers and current sources, providing excellent input common mode rejection. The test inputs are provided to set the outputs to ...

WP91566-L7M/5100R

D/C:07+

WP91566L7N

D/C:121500

The AT40KALs patented 8-sided core cell with direct horizontal, vertical and diagonal cell-to-cell connections implements ultra fast array multipliers without using any busing resources. The AT40KALs Cache Logic capability enables a large number of design coefficients and variables to be implemented in a very small amount of silicon, enabling vast improvement in system speed at much lower cost than convent...

WP-91566L7N103

D/C:9100

The ISP1521 has seven downstream facing ports. If not used, ports 3 to 7 can be disabled. The vendor ID, product ID and string descriptors on the hub are supplied by the internal ROM; they can also be supplied by an external I2C-bus™ EEPROM or a microcontroller.

WP91571L2

Vendor:NSPackage Cooled:1000

Data output of ADC C (MSB:CD8, LSB:CD1) (format 2) When MODE1 = L, MODE0 = L, CD8 outputs MSB flag of BD8CBD5 (format 1) When MODE1 = L, MODE0 = L, CD7 outputs LSB flag of BD8CBD5 (format 1) When MODE1 = H, MODE0 = L, CD8 outputs B channel flag of BD8CBD1 (format 3) When MODE1 = H, MODE0 = L, CD7 outputs B channel flag of BD8CBD1 (CD8CCD1) (format 3)

WP91574L1

Vendor:NS

WP91574L1

Vendor:NS

WP91574L3

Vendor:FAIRCHILDD/C:99+

DISP high disables the LED display. DISP tied to VCC allows PROGX to connect di- rectly to VCC or VSS instead of through a pull-up or pull-down resistor. DISP floating allows the LED display to be active during charge. DISP low activates the display. See Table 1.

WP91574L3

Vendor:FAIRCHILDD/C:99+

DISP high disables the LED display. DISP tied to VCC allows PROGX to connect di- rectly to VCC or VSS instead of through a pull-up or pull-down resistor. DISP floating allows the LED display to be active during charge. DISP low activates the display. See Table 1.

WP-91608L2

Vendor:DIPD/C:99+

The HT6P20A/B/D detects the logic state of the internal programmed address and the external data pins, and then trans- mits the detected information during the code period. Each address/data bit can be set to one of the following two logic states:

WP91641L2

Vendor:IRPackage Cooled:TO-247D/C:04+

WP91670L1

Vendor:FAIRCHILKPackage Cooled:500D/C:07+

Thermocompression bonding is recommended. Welding or conductive epoxy may also be used. For additional information see Application Note 979, The Handling and Bonding of Beam Lead Devices Made Easy, or Application Note 993, Beam Lead Device Bonding to Soft Substrates.

WP91670L2

Vendor:TIPackage Cooled:SOP-14D/C:2000

In cases in which absolute stability under all load conditions is required, it may be necessary to insert a small inductor in the output lead to isolate the circuit from capacitive loads. A 3µH inductor (1A) in parallel with a 22Ω resistor is adequate. The derivation of circuit constants is shown in Appendix B. Curves of control action versus electrical rotation are also given.

WP91678

Vendor:TIPackage Cooled:SOPD/C:N/A

WP91678L6

Vendor:TIPackage Cooled:SOP24WD/C:2007+

3) Two-stage power-fail warning: A separate low-line comparator compares VCC to a preset threshold 120mV above the reset threshold; the low-line and reset thresholds can be programmed externally. 4) Watchdog fault output: Assertion of WDO if the watch- dog input is not toggled within a preset timeout period.

WP91678L7

Package Cooled:04D/C:950

The ISL6550 includes a 5-bit DAC (Digital-to-Analog Converter), which is programmed by the five VID inputs. The voltage range of the BDAC (Buffered DAC output) is determined by the DACHI and DACLO voltage levels, which are externally adjustable through the R1, R2, R3 resistor divider network. VREF5 is a precision-trimmed 5V reference, and is used to set the voltage at the top of the resistor div...

WP91695L1

D/C:08+/09+

The PCM58P is a complete, precision 18-bit digital- to-analog converter with ultra-low distortion over a very wide frequency range. The latched serial input data format of the PCM58P is totally based on the widely successful 16-bit PCM56P format (with the addition of two more data bits). The PCM58P features a very low noise and fast settling current output.

WP91695L1

Package Cooled:SOP24WD/C:08+/09+

The PCM58P is a complete, precision 18-bit digital- to-analog converter with ultra-low distortion over a very wide frequency range. The latched serial input data format of the PCM58P is totally based on the widely successful 16-bit PCM56P format (with the addition of two more data bits). The PCM58P features a very low noise and fast settling current output.

WP9170

Vendor:WmbondPackage Cooled:SOP20WD/C:2007+

The HYM72V16M656B(L)T6 -Series are gold plated socket type Dual In-line Memory Modules suitable for easy inter- change and addition of 128M bytes memory. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.

WP91700L1

Package Cooled:4000D/C:500

q COMPLETE EVALUATION PLATFORM FOR THE PCM1742 STEREO AUDIO DAC q ONBOARD LOW-PASS FILTERS FOR THE LEFT AND RIGHT CHANNELS q EASY CONFIGURATION USING ONBOARD SWITCHES AND JUMPERS q 96kHz DIGITAL AUDIO RECEIVER ACCEPTS S/PDIF AND OPTICAL INPUTS

WP91701L1

Vendor:PHILIPSPackage Cooled:225D/C:00+

Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Pin Configuration Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics Characteristics Standby Input Characteristics Test Input Characteristics Reset Input Characteristics Main Clock Input Characteristics Active Video Output Characteristics A...

WP-91701L1

Vendor:SPackage Cooled:SOP16SD/C:2007+

TTL/CMOS input enable pin. Used to control the LOUT0-LOUT2 outputs and acts as a frequency select pin. LEN, DSEL, and LSEL are used together to decode the selection and post divide of the LVDS output bank, see the LVDS Output Post- Divider and Frequency Select Table for proper decoding. Internal 25kΩ pull-up. When disabled, LOUT0-LOUT2 outputs are LOW, and the complimentary outputs are HIGH. The thresh...

WP91712L01T

Vendor:NSPackage Cooled:SOPD/C:07+

Low-power dissipation Operating: 15 mW/MHz (typical) Single power supply voltage of 5 V 10% Power down features using CE Data retention supply voltage of 2.0 to 5.5 V Direct TTL compatibility for all inputs and outputs Wide operating temperature range of −40 to 85C Standby Current (maximum): 20 µA

WP91742L01

Vendor:CYPackage Cooled:252D/C:99/00+

• Feature • Precision Voltage Monitor for 3V, 3.3V or 5V Power Supplies • 6µA Supply Current • 140ms Minimum Reset Pulse Width • RESET Remains Valid with VCC as Low as 1.4V • Active Low Manual Reset Input • No External Components • 4-Pin SOT-143 Package

WP91742LO1

WP91749L1

Vendor:FAIPackage Cooled:SOP/14D/C:99+

P43P42/SBT4P41/SBI4/RXD4P40/SBO4/TXD4P87/LED7/D7P86/LED6/D6P85/LED5/D5P84/LED4/D4P83/LED3/D3P82/LED2/D2P81/LED1/D1P80/LED0/D0VSS2P77/SDO7/NDKP76/SDO6/NWEP75/SDO5/NREP74/SDO4/NCSP73/SDO3/A19P72/SDO2/A18P71/SDO1/A17P70/SDO0/A16P67/KEY7/A15P66/KEY6/A14P65/KEY5/A13P64/KEY4/A12

WP917CK/4YGWT

WP91819

WP91819L1

Vendor:NSPackage Cooled:SOPD/C:06+

All of the Ultra37000 devices are electrically erasable and In- System Reprogrammable (ISR), which simplifies both design and manufacturing flows, thereby reducing costs. The ISR feature provides the ability to reconfigure the devices without having design changes cause pinout or timing changes. The Cypress ISR function is implemented through a JTAG- compliant serial interface. Data is shifted in and o...

WP91819L1

Vendor:NSPackage Cooled:SOPD/C:06+

All of the Ultra37000 devices are electrically erasable and In- System Reprogrammable (ISR), which simplifies both design and manufacturing flows, thereby reducing costs. The ISR feature provides the ability to reconfigure the devices without having design changes cause pinout or timing changes. The Cypress ISR function is implemented through a JTAG- compliant serial interface. Data is shifted in and o...

WP91819L3

Vendor:NSPackage Cooled:SOIC-8D/C:06+

The TPS211xA family of power multiplexers enables seamless transition between two power supplies, such as a battery and a wall adapter, each operating at 2.8−5.5 V and delivering up to 1 A. The TPS211xA family includes extensive protection circuitry, including user-programmable current limiting, thermal protection, inrush current control, seamless supply transition, cross-conduction blocking, and re...

WP91819L3

Vendor:NSPackage Cooled:SMD8D/C:06+

The TPS211xA family of power multiplexers enables seamless transition between two power supplies, such as a battery and a wall adapter, each operating at 2.8−5.5 V and delivering up to 1 A. The TPS211xA family includes extensive protection circuitry, including user-programmable current limiting, thermal protection, inrush current control, seamless supply transition, cross-conduction blocking, and re...

WP91819L3T

Vendor:TIPackage Cooled:SOPD/C:07+

The chip-erase mode can be initiated by a six-byte command sequence. After the command loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed within fast 100 mS (max). The host system is not required to provide any control or timing during this operation. If the boot block programming lockout is activated, only the data in the other memory sectors w...

WP918289L5

WP-91832

Vendor:SND/C:05+

The Bus Interface Unit (BIU) controls the interface between the on-chip modules to the internal core bus. It determines the configured parameters for bus access (such as the num- ber of wait states for memory access) and issues the appro- priate bus signals for each requested access.

WP-91832L1

Vendor:TIPackage Cooled:06+D/C:500

The WP-91832L1 is a digital burst mode charge-transfer (QT) sensor designed specifically for touch controls; it includes all hardware and signal processing functions necessary to provide stable sensing under a wide variety of changing conditions. Only a single low cost, non-critical capacitor is required for operation.

WP91835L2

Vendor:FAIPackage Cooled:SOP/14D/C:99+

WP91847L1

Package Cooled:SOPD/C:03+

The PHY-link interface can follow either the IEEE 1394a-2000 protocol or the IEEE 1394b-2002 protocol. When using a 1394a-2000 LLC such as the TSB12LV26, the BMODE terminal must be deasserted. The PHY-link interface then operates in accordance with the legacy 1394a-2000 standard. When using a 1394b LLC such as the TSB82AA2, the BMODE terminal must be asserted. The PHY-link interface then conforms to the ...

WP91849L1

Vendor:PHILIPSPackage Cooled:SOP14D/C:99+

The LM4040 utilizes fuse and zener-zap reverse breakdown voltage trim during wafer sort to ensure that the prime parts have an accuracy of better than 0.1% (A grade) at 25˚C. Bandgap reference temperature drift curvature correction and low dynamic impedance ensure stable reverse break- down voltage accuracy over a wide range of operating tem- peratures and currents. Also available is the LM4041...

WP91850L2T

Vendor:SOP16Package Cooled:3001D/C:98+

The LTC®3901 is a secondary side synchronous rectifier driver designed to be used in isolated push-pull and full- bridge converter power supplies. The chip drives two external N-channel MOSFETs and accepts a transformer- generated bipolar input to maintain sychronization with the primary side controller.

WP91860L2

Vendor:TIPackage Cooled:4000D/C:00+

The WP91860L2M supports call messages in either tone, numerical or character outputs at signal speeds of 512 bps or 1200 bps using a 76.8 kHz system clock, or 2400 bps using a double-speed 153.6 kHz system clock. Note that output timing values for 2400 bps mode operation are not shown in this datasheet, but can be obtained by halving the values for 1200 bps mode operation.

WP91860L2

Vendor:TIPackage Cooled:4000D/C:00+

The WP91860L2M supports call messages in either tone, numerical or character outputs at signal speeds of 512 bps or 1200 bps using a 76.8 kHz system clock, or 2400 bps using a double-speed 153.6 kHz system clock. Note that output timing values for 2400 bps mode operation are not shown in this datasheet, but can be obtained by halving the values for 1200 bps mode operation.

WP91860OLZ

Package Cooled:SOP-20D/C:02+

WP91893L3

Vendor:NSPackage Cooled:SOP16SD/C:2007+

The SNAP! Pulse programming algorithm uses an initial pulse of 100 microseconds (µs) followed by a byte verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-µs pulses per byte are provided before a failure is recognized.

WP91902

Vendor:NatlonlPackage Cooled:SOP8SD/C:N/A

Low power, high speed CMOS FLASH technology Fully static design Wide operating voltage range: 2.0V to 5.5V High Sink/Source Current: 25 mA Industrial temperature range Low power consumption: - < 2 mA typical @ 5V, 4 MHz - 20 µA typical @ 3V, 32 kHz - < 1 µA typical standby current

WP91902L

Vendor:NSCPackage Cooled:SMD

TheCD54HC00,CD74HC00,CD54HCT00,and CD74HCT00 logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The 74HCT logic family is functionally pin compatible with the standard 74LS logic family.

WP91902L

Vendor:NSCPackage Cooled:SMDD/C:01+

TheCD54HC00,CD74HC00,CD54HCT00,and CD74HCT00 logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The 74HCT logic family is functionally pin compatible with the standard 74LS logic family.

WP91902L2

Vendor:NS

available. The data applied to the data inputs are transferred to the Q outputs of latches when the strobe input is held high. When the strobe input is taken low, the information data applied to the data input at a time is retained at the output of the latches. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

WP91908L

Vendor:INTELPackage Cooled:PLCC/28D/C:03+

WP91908L2

Vendor:NATIONAL INSTRUMENTSPackage Cooled:PLCC-28

The 212 encoders are a series of CMOS LSIs for remote control system applications. They are capable of encoding information which consists of N address bits and 12-N data bits. Each ad- dress/data input can be set to one of the two logic states. The programmed addresses/data are transmitted together with the header bits

WP-91919L1

Vendor:100Package Cooled:AMD

WP91924

WP91924L1

Vendor:TID/C:2007+

NOTES 1. The difference between the measured and the ideal code width (VREF/256) is the DNL error (Figure 3). The INL error is the maximum distance (in LSBs) from the best fit line to any transition voltage (Figure 4). Accuracy is a function of the sampling rate (FS). 2. Guaranteed, not tested. 3. Specified values guarantee functionality. Refer to other parameters for accuracy. 4. C1dB bandwidth is a measu...

WP91936L1

Hynix HYMD512G726(L)4-K/H/L series is registered 184-pin double data rate Synchronous DRAM Dual In-Line Mem- ory Modules (DIMMs) which are organized as 128Mx72 high-speed memory arrays. Hynix HYMD512G726(L)4-K/H/L series consists of eighteen 128Mx4 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD512G726(L)4-K/H/L series provide a high performance 8-byte interface in 5.25&quo...

WP91963J2CYP

D/C:95

WP91966

VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25C. For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. This parameter specifies the dynamic power-supply current associat...

WP91966L1

Vendor:NSPackage Cooled:PLCC28

DATA POLLING: The AT28C010-12DK features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write c...

WP91966L1/74F899QC

Vendor:NSPackage Cooled:PLCC28D/C:96+

WP91966LI

Vendor:NS

• Process Technology: Poly Load • Organization: 64Kx8 • Power Supply Voltage: 4.5~5.5V • Low Data Retention Voltage: 2V(Min) • Three state output and TTL Compatible • Package Type: 32-SOP-525, 32-TSOP1-0820F

WP91973L1

Vendor:NSPackage Cooled:9505D/C:590

The device has several operating modes dependent on the applied voltages to the S1 and S0 pins as shown in Table 1. In all the modes listed the channel multiplexers, D/A Register, LFO, and the output pulse dividers will always be powered up as long as there is a voltage source connected to the VDD pin.

WP91973L1T

Vendor:availPackage Cooled:NSCD/C:04+

Port 0: Is an 8-bit open drain bi-directional I/O port. Port 0 pins that have 1s written to them float, and in this state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. In this application it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code Bytes during program validation. ...

WP91973L2

Vendor:availPackage Cooled:NSCD/C:01+

Battery-Powered Devices Battery-Powered Alarm Circuits Smoke Detectors CO2 Detectors Smart Battery Packs PDAs Low Quiescent Current Voltage Reference Cameras and Portable Video Equipment Pagers and Cellular Phones Solar-Powered Instruments Consumer Products Microcontroller Power

WP91973L2

Vendor:availPackage Cooled:NSCD/C:01+

Battery-Powered Devices Battery-Powered Alarm Circuits Smoke Detectors CO2 Detectors Smart Battery Packs PDAs Low Quiescent Current Voltage Reference Cameras and Portable Video Equipment Pagers and Cellular Phones Solar-Powered Instruments Consumer Products Microcontroller Power

WP91973L3

Vendor:NATIONAL INSTRUMENTSPackage Cooled:PLCC

Notes: (1) OIP3 is measured with two tones at 1 MHz spacing at 0 dBm output power per tone. (2) The value for Thermal Resistance is based on a Device Voltage (VCC) of +5.5 Volts. 3. Performance as measured on ANADIGICS test fixture (see Figure 3).

WP91973L4

Vendor:availPackage Cooled:NSCD/C:03+

Vdd=2.7V~3.3V, TA = -25C to 85C(E) / -40C to 85C(I), unless otherwise specified -70-85 #SymbolParameter Min. Max. Min. Max. Read Cycle 1tRCRead Cycle Time70-85- 2tAAAddress Access Time-70-85 3tACSChip Select Access Time-70-85 4tOEOutput Enable to Output Valid-20-20 5tBA/LB, /UB Access Time-70-85 6tCLZChip Select to Output in Low Z10-10- 7tOLZOutput Enable to Output in Low Z5-5- 8tBLZ/LB,...

WP91975L1

Vendor:TIPackage Cooled:500D/C:SOP

FUNCTIONAL DESCRIPTION STAND-BY STATE The external capacitor,Cx, is fully charged to Vcc in the stand-by state. Hence, before triggering, transistor Qp and Qn (connected to the Rx/Cx node) are both turned-off. The two comparators that control the timing and the two reference voltage sources stop operating. The total supply current is therefore only leakage current. TRIGGER OPERATION Triggering occ...

WP92048L1

Vendor:NATIONAL INSTRUMENTSPackage Cooled:.

CioA or B portVCC = 5 V,16 † All typical values are at VCC = 5 V, TA = 25C. ‡ For I/O ports, the parameters IIH and IIL include the off-state output current. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

WP92048LI

WP92049L1

Vendor:PHILIPSPackage Cooled:SMD14D/C:01+

Note 4 In all applications transient segment output current must be limited to 50 mA This may be accomplished in dc applications by connecting a 2 2k resistor from the anode-supply filter capacitor to the display anode or by current limiting the anode driver in multiplex applications

WP92050L1

Vendor:PHILIPSPackage Cooled:210D/C:NULL

When a transition of the PHASE input occurs, CT is discharged to near ground during the crossover delay time (the crossover delay time is present to prevent simultaneous conduction of the source and sink drivers). After the crossover delay, CT is charged by an internal current source of approximately 1 mA. The comparator output remains blanked until the voltage on CT reaches approximately 3.0 volts.

WP92069L01

Vendor:.Package Cooled:2005D/C:03+

WP92080L2

Vendor:NSCPackage Cooled:SOP14D/C:SOP14

Note: while operation of the CS8920A is possi- ble without the use of an attached EEPROM, special design considerations are required. Fur- thermore, some of the CS8920A functions, such as Plug and Play capabilities and wakeup frame recognition are not possible without an attached EEPROM. Please contact Crystals CS8920A technical support for more information on the

WP92086

Vendor:NSPackage Cooled:SOP20

The Sequence Generator is a block oriented address gener- ator. This means that the desired address sequence is sub- divided into one or more address blocks, each containing a user defined number of addresses. User supplied configura- tion data determines the number of address blocks and the characteristics of the address sequence to be generated.

WP92086L1

Vendor:NSPackage Cooled:SOP20WD/C:2007+

The 3-STATE control gate operates as two input and such that if either G1 and G2 are high, all eight outputs are in the high impedance state. In order to enhance PC board layout, the 74AC541 offers a pinout having inputs and outputs on opposite side of the package. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient exces...

WP92096L

Vendor:MOTD/C:00+

WP92096L

WP92099

Vendor:NATIONAL INSTRUMENTSPackage Cooled:PLCC

WP92099L2

This is a complete series of 5 Watt Zener diodes with tight limits and better operating characteristics that reflect the superior capabilities of silicon−oxide passivated junctions. All this in an axial lead, transfer−molded plastic package that offers protection in all common environmental conditions.

WP-92099L2

Vendor:PHILIPSPackage Cooled:PLCC

VFB to the output of the error amplifier. Note 4: Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. Note 5: TJ is calculated from the ambient TA and power dissipation PD according to the following formula: TJ = TA + (PD • JA). Note 6: The DFN switch on-resistance is guaranteed by correlation to wafer level measurements.

WP9211

Vendor:NSD/C:08+/09+

Address Setup Time to Falling Edge of URD Address Hold Time from Rising Edge of URD URD Pulse Width URD Falling Edge to Output Data Valid Rising Edge of URD to Output Data Invalid RDRDY Delay from Rising Edge of URD UWR Pulse Width Input Data Valid before Rising Edge of UWR Input Data Hold after Rising Edge of UWR WRRDY Delay from Rising Edge of UWR

WP92114L1

Vendor:NSPackage Cooled:SOIC-8D/C:08+

The HY638256 is a high-speed 32,768 x 8-bits CMOS static RAM fabricated using Hyundai's high performance twin tub CMOS process technology. This high reliability process coupled with high-speed circuit design techniques, yields maximum access time of 15ns. The HY638256 has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 2.0 volt. It is suitable for use in high-...

WP92114L1

Vendor:NSPackage Cooled:SOIC-8D/C:00+

The HY638256 is a high-speed 32,768 x 8-bits CMOS static RAM fabricated using Hyundai's high performance twin tub CMOS process technology. This high reliability process coupled with high-speed circuit design techniques, yields maximum access time of 15ns. The HY638256 has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 2.0 volt. It is suitable for use in high-...

WP92114-L1

range in compliance with present and future application needs, including non temperature con- trolled environments. The mechanical design offers the choice of surface mount or through-hole versions, delivered in ready- to-use tubes, trays or tape & reel package, and compatibility with semi and fully aqueous cleaning processes. The PKF series is manufactured using highly automated manufacturing lines wi...

WP92119

D/C:08+/09+

Transmit alarm detectors: C Loss of Transmit Clock (TLOC) C Transmit Short Circuit (TSHORT) Receive alarm detectors: C Loss of Signal (RLOS) C Loss of Analog Input (RALOS) C Bipolar/Line Code Violations Automatic and on-demand transmit alarms: C AIS following TLOC C Automatic AIS clock switching

WP92119L

Vendor:.Package Cooled:SOP

The microphone input is a switchable interface for two differential microphone inputs. The first stage is a low noise differential amplifier that provides a selectable gain of C2.62 dB or 5.38 dB, which is routed to output pins MICOUTP and MICOUTN. The second stage amplifier gain is set externally. The first and second stages may be tied directly together with a specified gain or an external filter may be...

WP92121L1

Broad Support Program: A BSP layer is provided to allow easy porting of proprietary software on the SOC architecture. The BSP provides a unique hardware abstraction layer model valid for the entire product line. This approach allows reuse of the custom solfware through the entire MTC-50xxx product line(*).

WP-92141L2

Designing the circuits properly will improve the PS2601 optocoupler (Single Transistor type) by having a base pin in terms of switching speed, elimination of noise in input signals, and output leakage current (collector dark current, and application to high- voltage circuits).

WP92161

Vendor:CYP

Seven npn Darlington pairs -55C to 125C ambient operating temperature range Collector currents to 600mA Output voltages from 50V to 95V Internal clamping diodes for inductive loads DTL, TTL, PMOS, or CMOS compatible inputs Hermetic ceramic package

WP92161L01

Vendor:advantage series

When calculating synchronous frequencies, use tSU if all inputs are on dedicated input pins. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tS1. Determine which of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tS1) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for the synchronous configuration.

WP92161-L01

Vendor:CYPackage Cooled:SOJD/C:01+

This single mode transceiver is a Class 1 laser product. It complies with IEC-60825 and FDA 21 CFR 1040.10 and 1040.11. The transceiver must be operated within the specified temperature and voltage limits. The optical ports of the module shall be terminated with an optical connector or with a dust plug.

WP92161L1

WP92161LO1

WP92168AD

Vendor:FAIRCHIL..Package Cooled:PLCCD/C:08+

! High-speed 8-bit microprocessor interface allowing direct connection to both the 8080 and 6800 ! Serial interface ! Single supply operation, 2.4 - 3.5V ! Maximum 9V LCD driving output voltage ! 2X / 3X / 4X on chip DC-DC converter ! Voltage regulator ! Voltage follower (LCD bias: 1/5 or 1/6) ! On chip oscillator

WP92168L1 (100302)

WP92168L1 100302

Vendor:NSCPackage Cooled:PLCC28D/C:08+

WP92168L1/100302

Vendor:NSPackage Cooled:PLCC28D/C:99+

WP92168L1/100302

Vendor:NSPackage Cooled:PLCC28D/C:99+