WSC00022K000JTA

Vendor:ＶＩＳＨＡＹ

WSC00022K200JTA

WSC000247R00JEA

Vendor:ＶＩＳＨＡＹ

WSC00024K640FTA

Vendor:ＶＩＳＨＡＹ

WSC000251R00JTA

Vendor:VISHAYD/C:0551+

WSC0002R1000FTA

Vendor:DLD/C:06+/07+

The HEF4060B is a 14-stage ripple-carry binary counter/divider and oscillator with three oscillator terminals (RS, RTC and CTC), ten buffered outputs (O3 to O9 and O11 to O13) and an overriding asynchronous master reset input (MR). The oscillator configuration allows design of either RC or crystal oscillator circuits. The oscillator may

WSC0002R1000FTA

Vendor:DLD/C:06+/07+

The HEF4060B is a 14-stage ripple-carry binary counter/divider and oscillator with three oscillator terminals (RS, RTC and CTC), ten buffered outputs (O3 to O9 and O11 to O13) and an overriding asynchronous master reset input (MR). The oscillator configuration allows design of either RC or crystal oscillator circuits. The oscillator may

WSC0002R5600FTA

Vendor:ＶＩＳＨＡＹ

WSC-1

Package Cooled:钽电容D/C:9539

1 2 1 MAC Receive Section The receive section (Figure 1-3 ) controls the MAC receive operations during reception loopback and transmission During reception the deserializer goes active after detecting the one byte SFD (Start of Frame Delimiter) pattern (Section 2 1) consisting of a 10101011 sequence It then frames the incoming bits into octet boundaries and transfers the

WSC-1.11

Vendor:DALE(vishay)Package Cooled:SOJ-4D/C:00+

HY57V168010D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band- width. All input and output voltage levels are compatible with LVTTL.

WSC1.332-1R79

WSC-1.8OHM5

WSC-1/2-0.39

WSC-1/2-0.39

WSC-10.11

D/C:1000

WSC-1-0.681

Vendor:VISHAYPackage Cooled:SOPD/C:2000

NOTES: (1) COB = Complementary Offset Binary. (2) Complementary Twos Complementobtained by inverting the most significant bit MSB (pin 1). (3) CSB = Complementary Straight Binary. (4) Voltages given are the nominal value for transition to the code specified.

WSC-1-0.681

Vendor:VISHAYPackage Cooled:3200D/C:2000

NOTES: (1) COB = Complementary Offset Binary. (2) Complementary Twos Complementobtained by inverting the most significant bit MSB (pin 1). (3) CSB = Complementary Straight Binary. (4) Voltages given are the nominal value for transition to the code specified.

WSC10681

Package Cooled:3200

WSC-10R11

Vendor:ＶＩＳＨＡＹ

WSC-1-100 OHM -5R79

Vendor:ＶＩＳＨＡＹ

WSC1-150-3TR

WSC-1R751

Vendor:ＶＩＳＨＡＹ

WSC210OHM1

WSC-230R1

D/C:6000

NOTE: 1. This is intended to operate in the SSTL_2 type IV unterminated mode without series resistors on the outputs. 2. All typical values are at respective nominal VDDQ. 3. Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be crossing.

WSC2334

WSC251518R00JTA

WSC25152R000FEA

D/C:06+

Notes: *All PIO signals are shared with other physical pins. See the pin descriptions beginning on page 21 and Table 2 on page 29 for information on shared functions. ** RTS1/RTR1 and CTS1/ENRX1 are multiplexed with PCS3 and PCS2, respectively. See the pin descriptions beginning on page 21.

WSC25152R000FTA

WSC25155R000FTA

WSC2515R5000FTA

Vendor:ＶＩＳＨＡＹ

WSC2R174FR79

WSC4527-30OHM-1

WSC4527-4.75-1

WSC45274K640FTA

Vendor:ＶＩＳＨＡＹ

WSC692712R10FBA

Vendor:ＶＩＳＨＡＹ

WSC692712R10FEA

Vendor:ＶＩＳＨＡＹ

WSC69271R000FTA

Vendor:ＶＩＳＨＡＹ

WSC692754R90FEA

Vendor:ＶＩＳＨＡＹ

WSC692754R90FTA

Vendor:ＶＩＳＨＡＹ

WSD411

Vendor:JATPackage Cooled:SOT-23D/C:05+

♦ Plastic package has Underwriters Laboratory Flammability Classification 94V-0 ♦ This series is UL listed under the Recognized Component Index, file number E54214 ♦ Glass passivated chip junctions ♦ Typical IR less than 0.1µA ♦ High case dielectric strength ♦ Ideal for printed circuit boards ♦ High temperature soldering guaranteed: 260C/10 seconds at ...

WSD551H

Vendor:MOTD/C:08+

Turn-On Time: In the circuit of Figure 1, turning Q1 on applies a low voltage to the STBY control (pin 2) and disables the regulator ouput. Correspondingly, turning Q1 off removes the low-voltage signal and enables the output. Once enabled, the output will typically experience a 10C15ms delay followed by a predictable ramp-up of voltage. The regulator should provide a fully regulated output voltage wit...

WSD751H

Vendor:ONPackage Cooled:SOD-323D/C:08+

WSDA2212

Vendor:WSPackage Cooled:DIP

Four of the seven instructions end with the transmission of the instruction byte. The basic sequence is illustrated in Figure 3. These two-byte instructions exchange data between the Wiper Counter Register and one of the Data Registers. A transfer from a Data Register to a Wiper Counter Register is essentially a write to a static RAM. The response of the wiper to this action will be delayed tWRL. A t...

WSF128K16-XG1UX

WSF-25151305TR(WSF-25121305TR)

WSF512K32-XG2TX

WSH-01-392

WSHLP1207-1R5M 1.5U 28A

WSI27C010-12DMB

A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of SIZE. A LOW selects long-word operation. BM works with SIZE and BE to select the bus size and endian arrangement for Port B. The level of BM must be static throughout device operation.

WSI27C010L-10DMB

Vendor:WSI

The XR16C854/854D1 (854) is an enhanced quad Universal Asynchronous Receiver and Transmitter (UART) each with 128 bytes of transmit and receive FIFOs, transmit and receive FIFO counters and trigger levels, automatic hardware and software flow control, and data rates of up to 2 Mbps. Each UART has a set of registers that provide the user with operating status and control, receiver error indications, ...

WSI27C010L-10L

Vendor:WSIPackage Cooled:05+D/C:120

WSI27C010L-10LI

Vendor:WSIPackage Cooled:05+D/C:115

WSI27C010L-12/DMB

Vendor:DMB/5962Package Cooled:2005

The VHC14 is an advanced high speed CMOS Hex Schmitt Inverter fabricated with silicon gate CMOS technol- ogy. It achieves the high speed operation similar to equiva- lent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. Pin configuration and function are the same as the VHC04 but the inputs have hysteresis between the positive-going and negative-going input thresholds, which are...

WSI27C010L-12DI

Vendor:WSIPackage Cooled:DIP

Maximum repetitive peak reverse voltage Maximum RMS voltage Maximum DC blocking voltage Maximum average forward rectified current 0.375(9.5mm) lead length at TA=75 C Peak forward surge current 8.3ms single half sine-wave superimposed on rated load (JEDEC Method) Maximum instantaneous forward voltage at 1.0A Maximum DC reverse currentTA=25 C at rated DC blocking voltageTA=100 C Maximum reverse recovery ti...

WSI27C010L-12LI

Vendor:WSIPackage Cooled:05+D/C:115

WSI27C010L-15D

Package Cooled:DIP(散新)

• M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave • Busy and Interrupt Flags • Devices are capable of withstanding greater than 2001V electrostatic charge. • On-chip port arbitration logic • Full on-chip hardware support of semaphore signaling between ports • Fully asynchronous operation from either port • LVTTL-compatible, single ...

WSI27C010L-15DI

Vendor:WSID/C:DIP

WSI27C010L-15DMB

Vendor:WSIPackage Cooled:DIPD/C:04+

Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any p...

WSI27C010L-15LMB

Vendor:WSIPackage Cooled:05+D/C:133

WSI27C010L-20DMB

Vendor:WSID/C:04+

The WSI27C010L-20DMB CPLD is electrically reprogrammable using industry standard device programmers from vendors such as Data I/O, BP Microsystems, SMS, and others. The WSI27C010L-20DMB also includes an industry-standard, IEEE 1149.1, JTAG interface through which In-System Program- ming (ISP) and reprogramming of the device are sup- ported.

WSI27C128L-12DMB

Vendor:WSIPackage Cooled:DIPD/C:N/A

The READ ROM command sequence is the fastest sequence that allows the host to read the 8-bit family code and 48-bit identification number. It is used if only one SDQ slave device is attached to the bus. The READ ROM sequence starts with the host generating the RESET pulse of at least 480 µs. The bq2022 responds with a PRESENCE pulse. Next, the host continues by issuing the READ ROM command, 33h, and...

WSI27C128L-90D/5

Vendor:WSID/C:N/A

Parameter ENCODE INPUTS (ENCODE, ENCODE) Differential Input Voltage Range Differential Input Resistance Differential Input Capacitance LOGIC OUTPUTS (D15 to D0) Logic Compatibility Logic 1 VoltageILOAD 100 mA Logic 0 VoltageILOAD 100 mA Output Coding Series Output Resistanceper Bit

WSI27C128L-90D/5

Vendor:WSID/C:N/A

Parameter ENCODE INPUTS (ENCODE, ENCODE) Differential Input Voltage Range Differential Input Resistance Differential Input Capacitance LOGIC OUTPUTS (D15 to D0) Logic Compatibility Logic 1 VoltageILOAD 100 mA Logic 0 VoltageILOAD 100 mA Output Coding Series Output Resistanceper Bit

WSI27C210L-12D

Vendor:WSID/C:93

WSI27C210L-12DMB

Vendor:WSIPackage Cooled:2000

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input ...

WSI27C210L-15L

Vendor:WSIPackage Cooled:PLCCD/C:99+

Left Channel Input (capacitor coupled to input port) Left Channel Output (capacitor coupled to output port) Ground I2C Data Input I2C Clock Input Power Supply Right Channel Output (capacitor coupled to input port) Right Input Channel (capacitor coupled to output port)

WSI27C256-20DI/Y

Vendor:WSID/C:89

WSI27C256F-55

Vendor:WSIPackage Cooled:DIP

Inputs Are TTL-Voltage Compatible Provide Bus Interface From Multiple Sources in High-Performance Systems High-Current 3-State Outputs Interface Directly With System Bus Buffered Inputs and Outputs Package Options Include Ceramic Chip Carriers (FK) and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

WSI27C256L-10DI

Vendor:WSID/C:DIP

High performance and low cost solution Synchronous operation with high efficiency TTL-compatible 5 bit DAC, output voltage selection from 1.3V to 3.5V programmable High current totem pole output, up to 2 A for direct driving of the external N-Channel power MOSFETs. 200 KHz fixed frequency internal oscillator Fast transient response Power-Good output voltage monitor Over-Voltage and Over-Current protection

WSI27C256L-12T/5

Vendor:WSIPackage Cooled:DIPD/C:04+

The SN54 / 74LS155 and SN54 / 74LS156 are high speed Dual 1-of-4 Decoder/Demultiplexers. These devices have two decoders with common 2-bit Address inputs and separate gated Enable inputs. Decoder a has an Enable gate with one active HIGH and one active LOW input. Decoder b has two active LOW Enable inputs. If the Enable functions are satisfied, one output of each decoder will be LOW as selected by the a...

WSI27C256L-15D

Vendor:WSIPackage Cooled:DIPD/C:04+

0.6 mA to 15 mA operating current 0.6Ω dynamic impedance at any current Available with temperature coefficients of 0.001%/˚C 7µV wideband noise 5% initial tolerance 0.002% long term stability Low cost Subsurface zener

WSI27C256L-90

Vendor:WSID/C:01+

Ceramic Capacitors Above 150 kHz the performance of aluminum electrolytic capacitors becomes less effective. To further improve the reflected input ripple current or the output transient response, multilayer ceramic capacitors can also be added. Ceramic capacitors have very low ESR and their resonant frequency is higher than the bandwidth of the regulator. When used on the output their combined ESR is...

WSI27C256L-90T/5

Vendor:WSIPackage Cooled:DIPD/C:04+

The device is powered-up in normal operation mode with the OS in comparator mode, temperature threshold of 80 C and hysteresis of 75 C, so that it can be used as a stand-alone thermostat with those pre-defined temperature set points. The conversion rate is programmable, with a default of 10 conversions/sec.

WSI27C512-12T

Vendor:WSID/C:91

WSI27C512L-10

Vendor:WSID/C:90

This 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. The ALVCH162373 is particularly suitable for imple-menting buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one16-bit latch. When the latch enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q out...

WSI27C512L-10

Vendor:WSID/C:90

This 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. The ALVCH162373 is particularly suitable for imple-menting buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one16-bit latch. When the latch enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q out...

WSI27C512L-10DMB

Vendor:WSI

HY5DV651622 offers fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock(falling edges of the CLK ), Data(DQ), Data strobes(LDQS/UDQS) and Write data masks(LDM/UDM) inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve...

WSI27C512L-12D

Vendor:WSID/C:04+

The ispLSI 2192VE is a High Density Programmable Logic Device containing 192 Registers, nine or twelve Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2192VE features in-system programmability through the Bound- ary Scan Test Access Port (TA...

WSI27C512L-12D

Vendor:WSID/C:DIP

The ispLSI 2192VE is a High Density Programmable Logic Device containing 192 Registers, nine or twelve Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2192VE features in-system programmability through the Bound- ary Scan Test Access Port (TA...

WSI27C512L-12DI

Vendor:WSI

The TL05x are fully specified at 15 V and 5 V. For operation in low-voltage and/or single-supply systems, Texas Instruments LinCMOS families of operational amplifiers (TLC-prefix) are recommended. When moving from BiFET to CMOS amplifiers, particular attention should be paid to the slew rate and bandwidth requirements, and also the output loading.

WSI27C512L-15

Vendor:WSIPackage Cooled:DIPD/C:565

Unlike other nonvolatile memory technologies, there is no write delay with MRAM. The entire memory operation occurs in a single bus cycle. Therefore, any operation including read or write can occur immediately following a write. Data Polling, a technique used with EEPROMs to determine if the write is complete is unnecessary. Page write, a technique used to enhance EEPROM write performance is also unnecessary ...

WSI27C512L-15D

Vendor:WSIPackage Cooled:DIPD/C:04+

Ci is required when regulator is located an appreciable distance from power supply filter. Co is not needed for stability, however, it does improve transient response. Since IADJ is controlled to less than 100µA, the error associated with this term is negligible in most applications.

WSI27C512L-15DMB

Vendor:WSIPackage Cooled:DIPD/C:DIP

Ultra low dropout voltage Output adjusts from 1.23V to 15V Guaranteed 50 mA output current Uses tiny SOT-23 package Requires few external components < 1 µA quiescent current when shutdown Low ground pin current at all loads High peak current capability (150 mA typical) Wide supply voltage range (2.5VC16V) Overtemperature/overcurrent protection −40˚C to +125˚C Junction t...

WSI27C512L-15DMB

Vendor:WSIPackage Cooled:DIPD/C:04+

Ultra low dropout voltage Output adjusts from 1.23V to 15V Guaranteed 50 mA output current Uses tiny SOT-23 package Requires few external components < 1 µA quiescent current when shutdown Low ground pin current at all loads High peak current capability (150 mA typical) Wide supply voltage range (2.5VC16V) Overtemperature/overcurrent protection −40˚C to +125˚C Junction t...

WSI27C512L-20DMB

WSI27C512L-85DI

Vendor:WSI

WSI53S1681AJ

Vendor:availPackage Cooled:99+D/C:04+

The L1 memory system is the primary highest performance memory available to the Blackfin processor core. The L2 memory provides additional capacity with slightly lower performance. Lastly, the off-chip memory system, accessed through the External Bus Interface Unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing more than 768M bytes of external physical memory.

WSI57C010F-12DMB

Vendor:WSIPackage Cooled:DIPD/C:N/A

Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, there derived from benchmark timing patterns. The following guidelines relflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing ...

WSI57C010F-25DMB

Vendor:WSIPackage Cooled:99+00+D/C:3520

WSI57C010F-25E

Vendor:WSIPackage Cooled:TSOPD/C:96+

Red tinted, diffused Green tinted, diffused Yellow tinted, diffused Orange tinted, diffused Orange tinted, diffused Red tinted, diffused Un-tinted, diffused Green tinted, diffused Red tinted, diffused Green tinted, diffused Yellow tinted, diffused Orange tinted, diffused Orange tinted, diffused

WSI57C010F-25E

Vendor:WSIPackage Cooled:TSOPD/C:96+

Red tinted, diffused Green tinted, diffused Yellow tinted, diffused Orange tinted, diffused Orange tinted, diffused Red tinted, diffused Un-tinted, diffused Green tinted, diffused Red tinted, diffused Green tinted, diffused Yellow tinted, diffused Orange tinted, diffused Orange tinted, diffused

WSI57C010F-35

Vendor:WSI

The IXDP610 Digital Pulse Width Modulator (DPWM) is a programmable CMOS LSI device which accepts digital pulse width data from a microprocessor and generates two complementary, non-overlapping, pulse width modula- ted signals for direct digital control of switching power bridge. The DPWM is designed to be operated under the direct control of a microprocessor and interfaces easily with most standard micro...

WSI57C010F-35

Vendor:WSI

The IXDP610 Digital Pulse Width Modulator (DPWM) is a programmable CMOS LSI device which accepts digital pulse width data from a microprocessor and generates two complementary, non-overlapping, pulse width modula- ted signals for direct digital control of switching power bridge. The DPWM is designed to be operated under the direct control of a microprocessor and interfaces easily with most standard micro...

WSI57C010F-35DMB

Vendor:WSIPackage Cooled:99+00+

NOTES: (1) Test levels: (A) 100% tested at 25C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (2) Junction temperature = ambient for 25C guaranteed specifications. (3) Junction temperature = ambient at low temperature limit: junction temperature = ambient +23C at high temperature limit for over temperatur...

WSI57C010F-45D

Vendor:WSIPackage Cooled:99+00+D/C:04+

These Precision Optical Perform- ance AlInGaP LEDs provide superior light output for excellent readability in sunlight and are extremely reliable. AlInGaP LED technology provides extremely stable light output over long periods of time. Precision Optical Performance lamps utilize the aluminum indium gallium phos- phide (AlInGaP) technology.

WSI57C010F-45DI

Vendor:WSIPackage Cooled:99+00+D/C:98

WSI57C010F-45L

Vendor:WSID/C:96

WSI57C010F-55D

Vendor:WSIPackage Cooled:DIPD/C:04+

READ: The WSI57C010F-55D is accessed like an EPROM. When WSI57C010F-55DE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever WSI57C010F-55DE or OE is high. This dual-line control gives designers flexibility in preventing bus conten- tion. WSI57C010F-55DHIP ERASE: When the...

WSI57C010F-55D

Vendor:WSIPackage Cooled:99+00+D/C:04+

READ: The WSI57C010F-55D is accessed like an EPROM. When WSI57C010F-55DE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever WSI57C010F-55DE or OE is high. This dual-line control gives designers flexibility in preventing bus conten- tion. WSI57C010F-55DHIP ERASE: When the...

WSI57C010F-55DMB

Vendor:WSIPackage Cooled:DIPD/C:N/A

When input power is +29 dBm, heating in the Tx filter due to RF losses causes the filter membranes to heat up beyond 85C. This, in turn, causes the filter response to shift further left (down in fre- quency), resulting in increased insertion loss at the high end of the Tx band (1910 MHz). Agilent Technologies takes this into account in the manufacture and final test of the duplexer all specifications f...