Index "X"Vendor:XICORPackage Cooled:DIPD/C:300
Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in data line while the clock line is high will be interpreted as a START or STOP condition.
Vendor:XICORPackage Cooled:DIPD/C:N/A
Pin-for-Pin Compatible with UCC280X Controllers Enhanced Performance UC284X for New Designs 100-mA Typical Start-Up Current 500-mA Typical Operating Current Internal Soft Start at Power-On and After Fault 100-ns Internal Leading Edge Blanking
Vendor:DIPPackage Cooled:XICROD/C:350
Vendor:XICORD/C:N/A
The APX9142 is an integrated Hall Effect Sensor IC designed for electric commutation of DC brushless motor applications. The APX9142 still can operate at as low as 3 volts. The APX9142 is available in low cost TO -92M4 package with 3 different magnetic ranks.
Vendor:XICORPackage Cooled:DIPD/C:N/A
The APX9142 is an integrated Hall Effect Sensor IC designed for electric commutation of DC brushless motor applications. The APX9142 still can operate at as low as 3 volts. The APX9142 is available in low cost TO -92M4 package with 3 different magnetic ranks.
Vendor:XICORD/C:08+
Small Size Surface Mount DPAK Package Passivated Die for Reliability and Uniformity Blocking Voltage to 800 V On−State Current Rating of 4.0 A RMS at 108C High Immunity to dv/dt − 500 V/ms at 125C High Immunity to di/dt − 6.0 A/ms at 125C Epoxy Meets UL 94, V−0 @ 0.125 in ESD Ratings: Human Body Model, 3B u 8000 V Machine Model, C u 400 V
Vendor:XICORPackage Cooled:DIPD/C:N/A
Package Cooled:DIP/SMD
† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltag...
Vendor:XICORPackage Cooled:SMDD/C:00+
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5241/AD5242 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid...
Vendor:XICORD/C:01+
Note 7: Thermal regulation is defined as the change in output voltage at a time T after a change in power dissipation is applied, excluding load or line regulation effects. Specifications are for 200 mA load pulse at VIN = 20V (3W pulse) for T = 10 ms.
Vendor:XICORD/C:01+
Note 7: Thermal regulation is defined as the change in output voltage at a time T after a change in power dissipation is applied, excluding load or line regulation effects. Specifications are for 200 mA load pulse at VIN = 20V (3W pulse) for T = 10 ms.
Vendor:XICORD/C:01+
Note: Most lens assemblies reverse the viewed scene onto the sensor array, which generally means that pin 1 should be located at the bottom of the p.c. board. To ensure correct display orientation, check the lens specification prior to laying out the printed circuit board.
Vendor:XICORPackage Cooled:00+/ 01+D/C:400
Vendor:XICORPackage Cooled:00+/ 01+D/C:300
Vendor:XICORPackage Cooled:00+/ 01+D/C:300
Vendor:XICORPackage Cooled:00+ /01+D/C:300
Vendor:XICORPackage Cooled:00+/ 01+D/C:300
Vendor:XICORPackage Cooled:02+03+D/C:300
Vendor:XICORPackage Cooled:02+03+D/C:300
Vendor:XICORD/C:98+
Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Vendor:XICORD/C:98+
INTRODUCTION National Semiconductor (NSC) is committed to provide ap- plication information that assists our customers in obtaining the best performance possible from our products. The fol- lowing information is provided in order to support this com- mitment. The reader should be aware that the optimization of performance was done using a specific printed circuit board designed at NSC. Variations in p...
Vendor:XICORPackage Cooled:00+/ 01+D/C:98+
6.4 Qualification. With respect to products requiring qualification, awards will be made only for products which are, at the time of award of contract, qualified for inclusion in Qualified Products List QPL-19500 whether or not such products have actually been so listed by that date. The attention of the contractors is called to these requirements, and manufacturers are urged to arrange to have the produc...
Vendor:XICORPackage Cooled:02+03+D/C:300
Vendor:XICORPackage Cooled:02+03+D/C:300
Vendor:XICOR
The devices operate in the newly developed LinSkip mode. In this operating mode, the device switches seamlessly from the power saving, pulse-skip mode at light loads, to the low-noise, constant-frequency linear-regulation mode, once the output current exceeds the device-specific output current threshold.
Vendor:XICORPackage Cooled:96+D/C:168
The RF front end of the receiver is a heterodyne configuration that converts the input signal into a 1-MHz IF signal. According to the block diagram, the front end consists of an LNA (low noise amplifier), LO (local oscillator), a mixer and RF amplifier. The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal oscillator) generates the reference frequency fXTO. The VCO (...
Vendor:XICORPackage Cooled:DIPD/C:98+
Vendor:XICORPackage Cooled:DIPD/C:98+
Vendor:XICORPackage Cooled:DIPD/C:98+
Vendor:XICORD/C:98+
Vendor:XICORPackage Cooled:00+ /01+D/C:100
The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal must be connected to VDD through a 1-kΩ resistor. The SE and SM terminals must be tied to ground through a 1-kΩ resistor.
Vendor:XICORPackage Cooled:00+ /01+D/C:100
The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal must be connected to VDD through a 1-kΩ resistor. The SE and SM terminals must be tied to ground through a 1-kΩ resistor.
Vendor:XICORPackage Cooled:00+/ 01+D/C:400
Notes: 1. The algebraic convention, where most negative value is a minimum and most positive is a maximum, is used in this data sheet. 2. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing. 3. Guaranteed by design. 4. ∆RON = RON max. - RON min. 5. Flatness is defined as the difference between the maximum and minimum value of On-Resistance measured.
Vendor:XICORPackage Cooled:00+/ 01+D/C:98+
HALF Input/Output: this is an input in NT mode and an output in TE mode identifying which half of the S-interface frame is currently being written/read over the ST-BUS (HALF = 0 sampled on the falling edge of C4b within the frame pulse low window, identifies the information to be transmitted/received in the first half of the S-Bus frame while HALF=1 identifies the information to be transmitted/received into t...
Vendor:XICORD/C:98+
Note 1. Test voltage must be applied within dv/dt rating. Note 2. Guaranteed to trigger at an IF value less than or equal to max. IFT , recommended IF lies between Rated IFT and absolute max. IFT . Note 3. Measured with input leads shorted together and output leads shorted together.
Vendor:XICORD/C:98+
Vendor:XICORPackage Cooled:00+/ 01+D/C:300
The LM236, LM336 voltage references are easier to use than zener diodes. Their low impedance and wide current range facilitate biasing in any circuits. Besides, the breakdown voltage or the temperature coefficient can be adjusted so as to optimize the per- formance of the circuit. Figure 1 represents a LM336 with a 10kΩ potenti- ometer to adjust the reverse breakdown voltage can be adjusted w...
Vendor:XPackage Cooled:1000
The ADV7183A has a 5-line, superadaptive, 2D comb filter that gives superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to video standard and signal quality with no user intervention required. Video user controls such as brightness, contrast, saturation, and hue are also available within th...
Vendor:XPackage Cooled:1000
The ADV7183A has a 5-line, superadaptive, 2D comb filter that gives superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to video standard and signal quality with no user intervention required. Video user controls such as brightness, contrast, saturation, and hue are also available within th...
Vendor:XICORPackage Cooled:00+ /01+D/C:300
Integrated Pulse Shaping Circuit. Built-in B3ZS/HDB3 Encoder (which can be disabled). Accepts Transmit Clock with duty cycle of 30%-70%. Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications. Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499-CORE and
Vendor:XICORPackage Cooled:00+ /01+D/C:300
Integrated Pulse Shaping Circuit. Built-in B3ZS/HDB3 Encoder (which can be disabled). Accepts Transmit Clock with duty cycle of 30%-70%. Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications. Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499-CORE and
Package Cooled:00+/ 01+D/C:02+
The RC4700 uses a simple 5-stage pipeline, similar to the pipeline structure implemented in the IDT79R32364. This pipelines simplicity allows the RC4700 to be lower cost and lower power than super-scalar or super-pipelined processors. The pipeline stages are shown in Figure 3 on page 3.
Vendor:XICORPackage Cooled:00+/ 01+D/C:02+
The RC4700 uses a simple 5-stage pipeline, similar to the pipeline structure implemented in the IDT79R32364. This pipelines simplicity allows the RC4700 to be lower cost and lower power than super-scalar or super-pipelined processors. The pipeline stages are shown in Figure 3 on page 3.
Vendor:XICORD/C:98+
NEC's NE663M04 is fabricated using NEC's UHS0 25 GHz fT wafer process. With a typical transition frequency of 19 GHz the NE663M04 is usable in applications from 100 MHz to 5 GHz. The NE663M04 provides excellent low voltage/low current performance.
Vendor:XICORPackage Cooled:00+/ 01+D/C:300
NEC's NE663M04 is fabricated using NEC's UHS0 25 GHz fT wafer process. With a typical transition frequency of 19 GHz the NE663M04 is usable in applications from 100 MHz to 5 GHz. The NE663M04 provides excellent low voltage/low current performance.
Vendor:XICORPackage Cooled:00+/ 01+D/C:01+
The Advanced Interrupt Controller (AIC) controls the internal interrupt sources from the internal peripherals and the four external interrupt lines (including the FIQ), to provide an interrupt and/or fast interrupt request to the ARM7TDMI. It integrates an 8-level priority controller and, using the Auto-vectoring feature, reduces the interrupt latency time.
Vendor:XICORPackage Cooled:00+ /01+D/C:98+
The CS42416 integrated PLL provides a low-jitter system clock. The internal stereo ADC is capable of independent chan- nel gain control for single-ended or differential analog inputs. All six channels of DAC provide digital volume control and dif- ferential analog outputs. The general purpose outputs may be driven high or low, or mapped to a variety of DAC mute controls or ADC overflow indicators.
Vendor:XICORD/C:98+
The Simtek STK12C68-M is a fast static RAM (40, 45 and 55ns), with a nonvolatile EEPROM element incor- porated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation) take place automatically upon power down using charge stored in an external 100 &m...
Vendor:XICORPackage Cooled:5899D/C:DIP
Vendor:XICORPackage Cooled:899D/C:899
Vendor:XICORPackage Cooled:899D/C:899
Vendor:XICORPackage Cooled:.D/C:1288
Vendor:XICORPackage Cooled:1288D/C:1288
Vendor:XICORPackage Cooled:.D/C:1358
Vendor:XICORPackage Cooled:.D/C:899
Vendor:XPackage Cooled:1000
The received serial data is converted to parallel format by the on-chip serial to parallel converters and stored sequentially in a 256-position Data Memory. The sequential addressing of the Data Memory is generated by an internal counter that is reset by the input 8 kHz frame pulse (F0i) marking the frame boundaries of the incoming serial data streams.
Vendor:XICORPackage Cooled:294
Vendor:XICORPackage Cooled:294D/C:P
Package Cooled:PLCC32
MOSFET gates can be efficiently switched up to 2MHz using the ISL6208. Each driver is capable of driving a 3000pF load with propagation delays of 8ns and transition times under 10ns. Bootstrapping is implemented with an internal Schottky diode. This reduces system cost and complexity, while allowing the use of higher performance MOSFETs. Adaptive shoot-through protection is integrated to prevent both MOSFETs...
Vendor:XICOR
By means of controlling pin 24 less than 0.5 V, it can make the audio muting condition. The muting time constant is decided by R1 and C4 and these parts is related the pop noise at power ON/OFF.The series resistance; R1 must be set up less than 15 kΩ, we recommend 10 kΩ. The muting function have to be controlled by a transistor, FET and µ-COM port which has IMUTE 250 µA ability. Te...
Vendor:XICOR
By means of controlling pin 24 less than 0.5 V, it can make the audio muting condition. The muting time constant is decided by R1 and C4 and these parts is related the pop noise at power ON/OFF.The series resistance; R1 must be set up less than 15 kΩ, we recommend 10 kΩ. The muting function have to be controlled by a transistor, FET and µ-COM port which has IMUTE 250 µA ability. Te...
Vendor:XICORD/C:04+05+
3 lines symetrical (I/O) low-pass-filter High efficiency in EMI filtering Very low PCB space consuming: 1.6 x 1.6 mm2 Very thin package: 0.65 mm High efficiency in ESD suppression on both input & output PINS (IEC61000-4-2 level 4) High reliability offered by monolithic integration High reducing of parasitic elements through inte- gration & wafer level packaging.
Vendor:XICORPackage Cooled:CDIPD/C:04+
5 V Regulators Both low-side and high-side driver circuits incorporate a 5 V linear regulator circuit. The low-side regulator provides the supply voltage for the control logic and high-voltage level shift circuit. This allows HSIN and LS IN to be directly compatible with 5 V CMOS logic without the need of an external 5 V supply. The high-side regulator provides the supply voltage for the noise reje...
Vendor:XICORPackage Cooled:1000D/C:P
Vendor:XICORPackage Cooled:600D/C:P
HIGH SPEED : tPD = 21 ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4µA(MAX.) at TA=25C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 4017
Vendor:XICORPackage Cooled:127D/C:P
This IC provides protection for lithium ion batteries in the event of overcharging, overdischarging and overcurrents. When anomalies occur during charging or at other times and excessive voltages are applied, after a certain time has elapsed for each cell an external FET switch is turned off (overcharging detection); and in order to prevent overdischarge of the battery during discharge, when the voltage of i...
Vendor:XICORPackage Cooled:.D/C:34
Vendor:XICORPackage Cooled:DIPD/C:98+(original stok)
Notes: (1) Clip mounting (on case), where lead does not overlap heatsink with 0.110 offset (2) Clip mounting (on case), where leads do overlap heatsink (3) Screw mounting with 4-40 screw, where washer diameter is 4.9mm (0.19) (4) Pulse test: 300µs pulse width, 1% duty cycle
Vendor:XICORPackage Cooled:.D/C:30
See Figure 2 and Figure 3. Temperature range for Y version is −40C to +125C. Guaranteed by design and characterization, not subject to production test. All input signals are specified with tr = tf = ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
Vendor:XICORPackage Cooled:.D/C:30
See Figure 2 and Figure 3. Temperature range for Y version is −40C to +125C. Guaranteed by design and characterization, not subject to production test. All input signals are specified with tr = tf = ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
Vendor:N/APackage Cooled:DIPD/C:08+09+
Serial data output; 5-V CMOS logic level tri-state output for output (status) register data; sends 16-bit status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless device is selected by CS = low, therefore, several ICs can operate on only one data output line only.
Vendor:N/APackage Cooled:N/AD/C:08+09+
Serial data output; 5-V CMOS logic level tri-state output for output (status) register data; sends 16-bit status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless device is selected by CS = low, therefore, several ICs can operate on only one data output line only.
Vendor:XICORPackage Cooled:DIP
Unless otherwise stated, VDD = 3.3V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are 3 from typical.
Vendor:N/APackage Cooled:00+ /01+D/C:08+09+
The device operates on demand via a sync input pin. The sync input can also be used to avoid external noise sources and cross-interference from adjacent QRG capacitive sensors. Unique among capacitance sensors, this device features spread-spectrum burst modulation, permitting extremely high noise rejection characteristics for very robust signals even in high EMI environments.
Vendor:XICORPackage Cooled:DIPD/C:N/A
Internal Organization When ORG is connected to VDD or ORG is floated, the (´16) memory organi- zation is selected. When ORG is tied to VSS, the (´8) memory organization is selected. There is an internal pull-up resistor on the ORG pin. (HT93LC66-A)
Vendor:N/APackage Cooled:N/AD/C:08+09+
Read Write Logic - The Read/Write Logic accepts inputs from the system bus and gen- erates control signals for the other functional blocks of the X28C256DI-35. ADDR(1:0) select one of the three counters or the Control Word Regis- ter to be read from/written into. A low'' on the RD input tells the X28C256DI-35 that the CPU is reading one of the counters. A low'' on the WR input tells the X28C256DI-35 that th...
Vendor:N/APackage Cooled:DIPD/C:08+09+
Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 42mH, IAS = 5.5A, VDD = 50V, RG = 25 Ω, Starting TJ = 25C 3. ISD 5.5A, di/dt 200A/µs, VDD BVDSS, Starting TJ = 25C 4. Pulse Test : Pulse width 300µs, Duty cycle 2% 5. Essentially independent of operating temperature
Vendor:XICORPackage Cooled:DIPD/C:NULL
The active polarity of CLPDM and SHP (active high or active low) can be chosen through the serial interface, refer to serial interface for details. The default value of CLPDM and SHP is active low. However, right after power on, this value is unknown. For this reason, it must be set to the appropriate value by using the serial interface, or reset to the default value by the RESET pin. The description and t...
Vendor:XICORPackage Cooled:DIPD/C:NULL
The active polarity of CLPDM and SHP (active high or active low) can be chosen through the serial interface, refer to serial interface for details. The default value of CLPDM and SHP is active low. However, right after power on, this value is unknown. For this reason, it must be set to the appropriate value by using the serial interface, or reset to the default value by the RESET pin. The description and t...
Vendor:XICORPackage Cooled:02+D/C:598
1) Limited by junction temperature. Pulsed current is also limited by wiring 2) <500 Ohm or shorting Ifb to gnd may damage the part with Isd around 120A 3) >5000 Ohm or leaving Ifb open will shutdown the part. No current will flow in the load.
Vendor:XICORD/C:DIP
Optimized for 2.5V LVTTL Guaranteed Low Skew < 25ps (max) Very low duty cycle distortion < 300ps (max) High speed propagation delay < 2ns. (max) Up to 200MHz operation Very low CMOS power levels Hot insertable and over-voltage tolerant inputs 1:10 fanout buffer 2.5V VDD Available in TSSOP package
Vendor:XICORD/C:99+
NOTES: 1. The Phase Voltage is capable of withstanding -7V when the BOOT pin is at GND. 2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. See Tech Brief TB379. 4. For JC, the ca...
Vendor:XICORPackage Cooled:CDIP28D/C:——
The X28C256DMB is a 16-channel short-haul line interface unit (LIU) that supports E1/T1/J1 from a single 3.3V power supply. A wide variety of applications are supported through internal impedance matching. A single bill of material can supportE1/T1/J1withminimumexternal components. Redundancy is supported through nonintrusive monitoring, optimal high-impedance modes, and configurable 1:1 or 1+1 backup enha...
Vendor:XICORPackage Cooled:DIPD/C:N/A
C Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulat- ed EEPROM) C In-Application Programming (IAP) C 224 general purpose registers (register file) availa- ble as RAM, accumulators or index pointers
Vendor:XICORPackage Cooled:DIPD/C:0038+
Data is clocked on the negative transition of the CLOCK waveform. If less than 30 negative clock transitions have been received when the ENABLE line goes low (i.e., only B,M and A will have been clocked in), then the R counter latch will remain unchanged and only M and A will be transferred from the input shift register to the counter latches. This will protect the R counter from being corrupted by any glit...
Vendor:INTELPackage Cooled:00+D/C:2550
Maximum Frequency >1.0 GHz Typical 50 ps Output-to-Output Skew PECL Mode Operating Range: VCC = 3.135 V to 3.8 V with VEE = 0 V ECL Mode Operating Range: VCC = 0 V with VEE = C3.135 V to C3.8 V Open Input Default State Synchronous Enable/Disable Master Reset for Synchronization of Multiple Chips VBB Output LVDS and HSTL Input Compatible 20-Lead Pb-Free Package Available
Vendor:XICORPackage Cooled:DIPD/C:98+(original stok)
Vendor:XICORPackage Cooled:DIPD/C:N/A
Vendor:XICORPackage Cooled:DIPD/C:N/A
Fully static operation and Tri-state outputs TTL compatible inputs and outputs Low power consumption Battery backup(L/LL-part) - 2.0V(min) data retention Standard pin configuration - 32pin 525mil SOP - 32pin 400mil TSOP-II (Standard and Reversed)