X5045S8-2.7A

Vendor:INTERSILPackage Cooled:SOP8D/C:06+

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to an FR4 board using 0.5 sq in drain pad size....

X5045S8-2.7T1

Vendor:XICORPackage Cooled:SOP-8D/C:05+

The X5045S8-2.7T1 is a synchronous-pipelined Burst SRAM designed specifically to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous ope...

X5045S8I-2.7 G

Vendor:XICORPackage Cooled:SO-8

X5045S8I-2.7A

Vendor:IntersilPackage Cooled:SOP8D/C:1

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY fmax = 180 MHz Maximum Operating Frequency tpd = 5.0 ns Propagation Delay TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels Electrically Erasable and Reprogrammable Non-Volatile Programmable Speed/Power Logic Path Optimization

X5045S8I-4.5

Vendor:XICORPackage Cooled:DIP/SMDD/C:07+08+

Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. © Copyright 1989 Gennum Corporation.All rights reserved.Printed in Canada.

X5045S8I-4.5AT1

Auto Memory Store Function This function automatically locates and stores up to six stations, starting from the current point on the selected band. Press and hold the ATP button for more than 2 seconds to begin the ATP operation. After automatically storing the station, preset scan will begin, starting with preset number 1. Preset scanning will continue until it is canceled. • If ATP is started in th...

X5045S8IT1

Vendor:INTERSILPackage Cooled:SOP-8D/C:06+

State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus  Design for 2.5-V and 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC ) Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C High Drive (C12/12 mA at 3.3-V VCC) Ioff and Power-Up 3-State Support Hot Insertion Use Bus Hold on Data ...

X5045S8IT1

State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus  Design for 2.5-V and 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC ) Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C High Drive (C12/12 mA at 3.3-V VCC) Ioff and Power-Up 3-State Support Hot Insertion Use Bus Hold on Data ...

X5045S8IZ

Vendor:INTERSILPackage Cooled:SOP-8D/C:06+

Figure 2 illustrates the logic block architecture. Each logic block contains control terms, a PAL array, a PLA array, and 16 macrocells. The six control terms can individually be configured as either SUM or PRODUCT terms, and are used to control the preset/reset and output enables of the 16 macrocells flip-flops. In addition, two of the control terms can be used as clock signals (see Macrocell Archi- ...

X5045S8IZ-2.7

Vendor:INTERSILPackage Cooled:SOP-8D/C:06+

Ideally, the relative size of measurement error should be fairly constant at various PFs, assuming that there is no phase error. In reality, the CTs introduce a small phase error that is generally constant in the amount of current lead or lag they create. The relative size the of measurement error can vary significantly with the power factor, however. If we calculate the percentage of error as ((cos)...

X5045S8IZ-4.5A

Vendor:INTERSILPackage Cooled:SOP8D/C:06+

Short-circuit current is internally limited. The device responds to a sustained overcurrent condition by turning off after a tON time delay. The device then stays off for a period, tOFF, that is 32 times the tON delay. The device then begins pulsing on and off at the tON/(tON+tOFF) duty cycle of 3%. This drastically reduces the power dissipation during short-circuit and means heat sinks need only accommod...

X5045S8IZT1

Package Cooled:SOP-8

efficiency minimizes the requirement for heat-sinking and the low output ripple minimizes the need for additional filtering. For maximum flexibility, power can be traded between outputs as required. The VSX60 series feature virtually all of the options required by design engineers but not at the competitions typical additional price for each option. This multitude of features are standard on the VS...

X5045S8IZT1

Package Cooled:SOP-8

efficiency minimizes the requirement for heat-sinking and the low output ripple minimizes the need for additional filtering. For maximum flexibility, power can be traded between outputs as required. The VSX60 series feature virtually all of the options required by design engineers but not at the competitions typical additional price for each option. This multitude of features are standard on the VS...

X5045S8T1

Light intensity is controlled by reducing the voltage at the CTRL input. As the CTRL input voltage is reduced below the user defined maximum value, the oscillator signal driving the N-Channel MOSFET is interrupted by the ErrorAmp/Comparator. The pulse skip modulating of the N-Channel MOSFET causes a reduction in the regulated current equal to the ratio of the reduced CTRL voltage to the maximum CTRL voltage.

X5045S8T1-2.7 F

Vendor:XICORPackage Cooled:SO-8

X5045S8TI INTERSIL

X5045S8Z

Vendor:INTERSILPackage Cooled:SOP8D/C:06+

Output Rise/Fall Time20% to 80%200t R / tF NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs o...

X5045S8Z-2.7

Vendor:XICORD/C:05+

Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input reference voltage.

X5045S8ZT1

Package Cooled:SOP-8

Each 6B Series module and board is a complete microcontroller-based process monitoring and control system, with all calibration, address and linearizing parameters stored in non-volatile memory. Being microcontroller-based, 6b Series

X5045S8ZT1

Each 6B Series module and board is a complete microcontroller-based process monitoring and control system, with all calibration, address and linearizing parameters stored in non-volatile memory. Being microcontroller-based, 6b Series

X5045SG

Vendor:N/APackage Cooled:N/AD/C:08+09+

convection cooling and have an operational ambient temperature range in compliance with present and future application needs, including non temperature controlled environments. The mechanical design offers the choice of surface mount or through-hole versions, delivered in ready-to-use tubes, trays or tape & reel package and compatibility with semi and fully aqueous cleaning processes. The PKF series is ...

X5045SI XICOR

X5045SI.

Vendor:XICORD/C:2008+

X5045SI-2.7

Vendor:XICORD/C:309

Note 5: Timing specifications are sample tested at +25C to ensure compliance. All input control signals are specified with tr = tf = 20ns (10% to 90% of +5V) and timed from a voltage level of 1.6V. Note 6: t3 and t6 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V. Note 7: t7 is defined as the time required for the data lines to change 0.5V w...

X5045SI-2.7A

Vendor:SOPD/C:INTERSIL

4.4 Conformance inspection. Conformance inspection shall be in accordance with MIL-PRF-19500, and as specified herein. If alternate screening is being performed in accordance with E.5.3.1d of MIL-PRF-19500, a sample of screened devices shall be submitted to and pass the requirements of group A1 and A2 inspection only (table VIb, group B, subgroup 1 is not required to be performed again if group B has already ...

X5045SI2.7V

Vendor:XICORPackage Cooled:SOPD/C:04+

For more details on UniqueWare and how to set up data files, please refer to the UniqueWare Project Setup Manual, available as Application Note 99 from Dallas Semiconductor. The UniqueWare Project Setup Software is available from the Dallas Semiconductor FTP Site at ftp://ftp.dalsemi.com/pub/auto_id, file name "unwsetup.exe."

X5045SIZ

D/C:08+

NOTES: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 Ω. VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance.

X5045SIZ-2.7

Vendor:availPackage Cooled:INTERSILD/C:07+

The PKA 2000 I Series DC/DC power modules are designed in accordance with EN 60 950, Safety of information technology equipment including electrical business equipment and certified by SEMKO. The PKA power modules are recognized by UL and meet the applicable requirements in UL 1950 Safety of information technology equip- ment, the applicable Canadian safety require- ments and UL 1012 Standard for power sup...

X5045Z

Vendor:INTPackage Cooled:SOPD/C:8

This device has been designed to meet the increasing demand for white SMD LED. The package of the TLMW310. is the PLCC-2 (equiv- alent to a size B tantalum capacitor). It consists of a lead frame which is embedded in a white thermoplast. The reflector inside this package is filled with a mixture of epoxy and TAG phosphor. The TAG phosphor converts the blue emission par- tially to yellow, which mixe...

X5045ZAP

Vendor:INTERSILPackage Cooled:SOP-8D/C:N/A

X5045ZAP

Vendor:INTERSILPackage Cooled:SOP-8D/C:N/A

X5045ZG

Vendor:INTERSILPackage Cooled:SOP8D/C:06+

X5045ZI

Vendor:XICPackage Cooled:SOP8D/C:07+

Software design support and automatic place-and-route provided by Alteras development systems for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Caden...

X5083F

Package Cooled:英特锡尔D/C:08+/09+

∗1 Period Jitter 1: This value is the standard deviation of an output period when using Time Interval Analyzer with 10,000 sampling. ∗2 Period Jitter MIN-MAX : This value is the max range of an output period when using Time Interval Analyzer with 10,000 sampling. ∗3 Output Lock time: Time between voltage supply leads to 3.0V and output clock gets stable.

X5083F

D/C:08+/09+

∗1 Period Jitter 1: This value is the standard deviation of an output period when using Time Interval Analyzer with 10,000 sampling. ∗2 Period Jitter MIN-MAX : This value is the max range of an output period when using Time Interval Analyzer with 10,000 sampling. ∗3 Output Lock time: Time between voltage supply leads to 3.0V and output clock gets stable.

X5083-F

Vendor:XICORPackage Cooled:SOP8D/C:00+

When the Schottky diode is reversed biased, the potential barrier for electrons becomes large; hence, there is a small probability that an electron will have sufficient thermal energy to cross the junction. The reverse leakage current will be in the nanoampere to microampere range, depending upon the diode type, the reverse voltage, and the temperature.

X5083I

Vendor:INTERSILPackage Cooled:SOP-8D/C:06+

Note 1 : This regulator is not internally compensated and thus requires an external output-capacitor (COUT) for stability. Note 2 : Please be careful with regard to set wiring and temperature-related capacitor changes that may cause oscillation.

X5083P

Vendor:XICORPackage Cooled:DIP8D/C:0406+

Notes a. Surface Mounted on 1 x 1 FR4 Board. b. Junction-to-foot thermal impedance represents the effective thermal impedance of all heat carrying leads in parallel and is intended for use in conjunction with the thermal impedance of the PC board pads to ambient (RthJA = RthJF + RthPCB-A). It can also be used to estimate chip temperature if power dissipation and the lead temperature of a heat carrying (...

X5083P-2.7

Vendor:1000Package Cooled:DIPD/C:20007

The HA-460 Series of quartz crystal oscillators are resistance welded in an all metal package, offering RFI shielding, and are designed to survive standard wave soldering operations without damage. Insulated standoffs to enhance board cleaning are standard.

X5083S8

Vendor:XICORD/C:4

Drain to source clamp voltage Drain to source on resistance Drain to source leakage current Input threshold voltage Input protection reset threshold voltage Input supply current (normal operation) Input supply current (protection mode) Input clamp voltage Body-drain diode forward drop➂

X5083S8-4.5A

Vendor:INTERSILPackage Cooled:SOP-8D/C:04+

Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 0.88mH, IAS = 32A, VDD = 50V, RG = 25 Ω, Starting TJ = 25C 3. ISD 32A, di/dt 300A/µs, VDD BVDSS, Starting TJ = 25C 4. Pulse Test : Pulse width 300µs, Duty cycle 2% 5. Essentially independent of operating temperature

X5083S8I

Vendor:XICORPackage Cooled:SO-8D/C:06+

X5083S8I27

X5083S8I27T4

Vendor:SOP8LPackage Cooled:XICORD/C:0219+

The Absolute Minimum Operating Pulse Width (high or low) specification, tabulated in Table 1, determines the smallest Pulse Width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion.

X5083S8IZ

Vendor:INTERSILPackage Cooled:SOP-8D/C:06+

The S1117 series of positive adjustable and fixed regulators are designed to provide 1A with higher efficiency. All internal circuitry is designed to operate down to 1.3V input to output differential. On-chip trimming adjusts reference voltage to 2%

X5083S8IZ-2.7

Vendor:INTERSILPackage Cooled:SOP-8D/C:06+

The X5083S8IZ-2.7 is a integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the digitally controlled potentiometers. This section provides detail description of the following:

X5083S8IZ-2.7A

Vendor:INTERSILPackage Cooled:SOP8D/C:06+

Item Power Rating Power Rating Thermal Resistance Resistance Range Nominal Resistance Series TCR Tolerance Operation Temp. Range Max. Operating Volt. Dielectric Withstanding Voltage Load Life Humidity Temp. Cycle Soldering Heat Solder ability Insulation Resistance Vibration

X5083S8Z-2.7

Vendor:INTERSILPackage Cooled:SOP-8D/C:05+

Furthermore some critical parasitics have to be considered. These are shortened loops (e.g. in the ground line of the PCB board) close to the antenna and undesired loops in the antenna circuit. Shortened loops decrease Q of the circuit. They have the same effect like conducting plates close to the antenna. To avoid undesired loops in the antenna circuit it is recommended to mount the capac- itor Cres ...

X5083V8-2.7

Vendor:XICORPackage Cooled:TSSOP-8D/C:00+

Command/Data Input This input pin allows selection of either the Command or Data port in the HIMIB device. When this signal is HIGH, the Command port is selected and, when it is LOW, the Data port is selected. This pin is typically con- nected to the least significant bit of the address bus.

X5083V8-2.7A

Vendor:XICORPackage Cooled:TSSOP-8D/C:00

The voice ROM is originally designed to continu- ously record the 3-sec voice data at about 5kHz sampling rate. A higher sampling rate will gener- ate voices of better playback quality, but will shorten the total recording time. On the other hand, a lower sampling rate will result in longer recording time but sacrifice the voice quality.

X5083V8I-2.7A

Vendor:XICORPackage Cooled:TSSOP-8D/C:0

The 512Mb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 4 banks, 16Mbit x 8 I/Os x 4banks or 8Mbit x 16 I/Os x 4 banks device. This synchronous device achieves high speed double- data-rate transfer rates of up to 533Mb/sec/pin (DDR2-533) for general applications. The chip is designed to comply with the following key DDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency -...

X5083V8I-2.7A

Vendor:XICORPackage Cooled:TSSOP-8D/C:0

The 512Mb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 4 banks, 16Mbit x 8 I/Os x 4banks or 8Mbit x 16 I/Os x 4 banks device. This synchronous device achieves high speed double- data-rate transfer rates of up to 533Mb/sec/pin (DDR2-533) for general applications. The chip is designed to comply with the following key DDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency -...

X5083V8IZ-2.7

Vendor:INTERSILPackage Cooled:TSSOP-8D/C:06+

I2C INTERFACE TIMING CHARACTERISTICS6, 11 (Specifications Apply to All Parts) SCL Clock FrequencyfSCL tBUF Bus Free Time between STOP and STARTt1 tHD;STA Hold Time (Repeated START)t2After this period, the first clock pulse is generated. tLOW Low Period of SCL Clockt3 tHIGH High Period of SCL Clockt4 tSU;STA Setup Time for Repeated START Conditiont5 tHD;DAT Data Hold Timet6 tSU;DAT Data Setup ...

X5083ZF

Vendor:INTERSILD/C:0615+

The ZiLOG ZHX1010 SIR transceiver provides an efficient implementation of the IrDA-Data standard in a small footprint format. Application circuit space is also minimized, as only two external resistors and one capacitor are needed to com- plete the IrDA transceiver solution. The ZHX1010 SIR transceiver meets the IEC825-Class 1 Eye Safety limits.

X5083ZI

Vendor:XICPackage Cooled:SOP8D/C:07+

The HYM71V16M755HC(L)T8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 128Mbytes memory. The HYM71V16M755HC(L)T8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are inter- nally pipelined to achieve very high bandwidth.

X5083ZI

Vendor:XICPackage Cooled:SOP8D/C:07+

The HYM71V16M755HC(L)T8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 128Mbytes memory. The HYM71V16M755HC(L)T8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are inter- nally pipelined to achieve very high bandwidth.

X5097G

Vendor:XICORPackage Cooled:SOPD/C:70

The information presented in this document does not form part of any quotation or contract. The information presented is believed to be accurate and reliable, and may change without notice in advance. No liability will be accepted by the publisher for any consequence of use.Publication thereof does not convey nor imply any license under patent or other

X50C06

X50C08

Vendor:.Package Cooled:BGA

X5101A-7

Temperature Sensor diode can be connected, on the board, to any of the ADC inputs to monitor the on-chip temperature Four dedicated general-purpose Quad Timers totaling three dedicated pins: Timer C with one pin and Timer D with two pins Optional On-Chip Regulator FlexCAN (CAN Version 2.0 B-compliant ) module with 2-pin port for transmit and receive Two Serial Communication Interfaces (SCIs), each wi...

X5101A-A

X5101A-C

Package Cooled:SQL15

Advance/Load Input. Used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address.

X5101A-E

Package Cooled:SQL15

The ADS8509 is a complete 16-bit sampling analog-to-digital (A/D) converter using state-of-the-art CMOS structures. It contains a complete 16-bit, capacitor-based, successive approximation register (SAR) A/D converter with sample-and-hold, refer- ence, clock, and a serial data interface. Data can be output using the internal clock or can be synchronized to an external data clock. The ADS8509 also pr...

X5101B-0

Package Cooled:SQL15

INPUT - Is digital input for controlling the PWM pulse width of the bridge. A duty cycle higher than 50% will produce greater than 50% duty cycle pulses out of OUTPUT A. A duty cycle lower than 50% will produce greater than 50% duty cycle pulses out of OUTPUT B.

X5116AC-3C-E

Vendor:ELPIDA

On Board 24Mhz Crystal Driver Circuit Can be clocked by 48MHz external source On-Chip 1.8V Regulator for Low Power Core Operation Internal PLL for 480Mhz USB2.0 Sampling, Configurable MCU clock Supports firmware upgrade via USB bus if boot block Flash program memory is used 15 GPIOs for special function use: LED indicators, button inputs, power control to memory devices, etc.

X5116AC-3C-E

Vendor:ELPIDA

On Board 24Mhz Crystal Driver Circuit Can be clocked by 48MHz external source On-Chip 1.8V Regulator for Low Power Core Operation Internal PLL for 480Mhz USB2.0 Sampling, Configurable MCU clock Supports firmware upgrade via USB bus if boot block Flash program memory is used 15 GPIOs for special function use: LED indicators, button inputs, power control to memory devices, etc.

X5163AG

Vendor:INTERSILPackage Cooled:SOP-8D/C:N/A

X5163PAL

Vendor:XICORPackage Cooled:DIP8D/C:0037

X5163PI

Vendor:XICORPackage Cooled:DIP8D/C:05+

Note 9 This part specifically does not have thermal shutdown protection to avoid safety problems related to an unintentional restart due to thermal time constant variations Care should be taken to prevent excessive power dissipation on the die

X5163PI-2.7

Vendor:XICORPackage Cooled:DIP-8D/C:05+

Isolated Frequency Input. Amplifies, Protects, Filters, and Isolates Analog Input. Generates an output of 0 to +5V proportional to input frequency. Model 5B45 accepts full-scale inputs from 500 Hz to 20 kHz. Model 5B46 accepts full-scale input from20 Khz to 275 kHz. Module circuitry can withstand 240v rms at the input screw- terminals. All 5B45 & 5B46 series modules are mix-and-match and Hot Swap...

X5163S8-4.5A

Vendor:1000Package Cooled:SOP-8D/C:20007

These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance3-stateandincreased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly a...

X5163S8-4.5A

Vendor:INTERSILPackage Cooled:XICORD/C:06+

These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance3-stateandincreased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly a...

X5163S8I-2.7

Package Cooled:SOP8D/C:08+/09+

Another common application of the X5163S8I-2.7/829 is shown in Figure 6. X5163S8I-2.7his circuit performs two functions in combination. C1 and C2 form the standard inverter circuit described above. C3 and C4 plus the two diodes form the voltage doubler circuit. C1 and C3 are the pump capacitors and C2 and C4 are the reservoir capacitors. Because both sub-circuits rely on the same switches if either ou...

X5163S8IZ-2.7

Vendor:INTERSILPackage Cooled:SOP-8D/C:06+

For a general estimate of ICC, the following equation may be used: PTOTAL = PINT + PIO = ICCINT x VCCINT + PIO Separating internal and I/O power here is convenient because XC9500XV CPLDs also separate the correspond- ing power pins. PIO is a strong function of the load capaci- tance driven, so it is handled by I = CVf. ICCINT is another situation that reflects the actual design considered and the interna...

X5163S8IZ-4.5A

X5163S8Z-2.7A

Vendor:INTERPackage Cooled:SO-8D/C:6

The IRU3027 controller IC is specifically designed to meet VRM 9.0 specification for next generation microproces- sor applications requiring multiple on-board regulators. The IRU3027 provides a single chip controller IC for the Vcore, three LDO controllers, one with an automatic se- lect pin that connects to the Type Detect pin of the AGP slot for the AGP VDDQ supply, one for GTL+ and the other for the 1.8V ...

X5163S8Z-2.7A

Vendor:INTERPackage Cooled:SO-8D/C:6

The IRU3027 controller IC is specifically designed to meet VRM 9.0 specification for next generation microproces- sor applications requiring multiple on-board regulators. The IRU3027 provides a single chip controller IC for the Vcore, three LDO controllers, one with an automatic se- lect pin that connects to the Type Detect pin of the AGP slot for the AGP VDDQ supply, one for GTL+ and the other for the 1.8V ...

X5163S8Z-4.5A

Vendor:INTERSILPackage Cooled:SOP-8D/C:06+

Parameter Supply Voltage VDD to Ground Data Input, Data Output, VB Column Input Voltage, VCOL Free Air Operating Temperature Range, TA Storage Temperature Range, Ts Maximum Allowable Package Power Dissipation, PD[2,3] at TA = 71C Through-the-Wave Solder Temperature 1.59 mm (0.063") Below Body ESD Protection @ 1.5 kΩ, 100 pF

X5163S8Z-4.5A

Vendor:INTERSILPackage Cooled:SOP-8D/C:06+

Parameter Supply Voltage VDD to Ground Data Input, Data Output, VB Column Input Voltage, VCOL Free Air Operating Temperature Range, TA Storage Temperature Range, Ts Maximum Allowable Package Power Dissipation, PD[2,3] at TA = 71C Through-the-Wave Solder Temperature 1.59 mm (0.063") Below Body ESD Protection @ 1.5 kΩ, 100 pF

X5163SI

Vendor:N/APackage Cooled:N/AD/C:08+09+

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the A data is latched while CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low, A data is stored on a low-to-high transition of CLKAB. Wh...

X5163V14

Vendor:XICORD/C:1

X5163Z

Vendor:INTERSILPackage Cooled:INTERSILD/C:07+

Parameter Read cycle time Address access time Chip select1 access time Chip select2 access time Output enable access time Chip select1 output set time Chip select1 output floating Chip select2 output set time Chip select2 output floating Output enable output set time Output enable output floating Output hold time

X5163Z

Vendor:INTERSILPackage Cooled:SMD-8D/C:07+

Parameter Read cycle time Address access time Chip select1 access time Chip select2 access time Output enable access time Chip select1 output set time Chip select1 output floating Chip select2 output set time Chip select2 output floating Output enable output set time Output enable output floating Output hold time

X5163ZAL

Vendor:INTERSILPackage Cooled:SOP8D/C:06+

X5165AL

Vendor:INTERSILPackage Cooled:SOP8D/C:06+

X5165I

Vendor:INTERSILPackage Cooled:SOP8D/C:06+

• 6/12 I/O pins with individual direction control: - High-current source/sink for direct LED drive - Interrupt-on-pin change - Individually programmable weak pull-ups/ pull-downs - Ultra Low-Power Wake-up • Analog comparator module with: - Up to two analog comparators - Programmable on-chip voltage reference (CVREF) module (% of VDD) - Comparator inputs and outputs externally ac...

X5165PIZ-2.7

X5165S

Vendor:XICORPackage Cooled:N/AD/C:01+

Fully programmed sequencing control ramps the back-end plane voltages in order, and during shutdown from a healthy state, turns off the back-end supplies in the reverse order. In addition, electronic circuit breakers provide continuous protection for the system supplies during the plug-in operation. The TTL/CMOS-compatible ENABLE input and the board power good signal (PG) can interface directly to the indi...

X5165S8-2.7

Vendor:1000Package Cooled:XICORD/C:06+

1. Package is non-polarized. Parts may be on reel in orientation illustrated, 180 rotated, or mixed (both ways). 2. Device mounted on FR-4 PCB, 1 inch x 0.85 inch x 0.062 inch; pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at http://www.diodes.com/datasheets/ap02001.pdf. 3. No purposefully added Lead.

X5165S8-I-2.7

X5165S8IZ

Vendor:INTERSILPackage Cooled:SOP8D/C:06+

The X5165S8IZ is designed to produce the reference voltages required in TFT-LCD applications. Each output is programmed to the required voltage with 10 bits of resolution. Reference pins determine the high and low voltages of the output range, which are capable of swinging to either supply rail. Programming of each output is performed using the serial interface. A serial out pin enables daisy chaining of mul...

X5165SI

Vendor:N/APackage Cooled:1000D/C:08+09+

Floating Pin 4 divides the master oscillator by 10. Pin 4 should be tied to V+ for the 100 setting, the lowest frequency range. To detect a floating DIV pin, the LTC6900 attempts to pull the pin toward midsupply. Therefore, driving the DIV pin high requires sourcing approximately 2µA. Likewise, driving DIV low requires sinking 2µA. When Pin 4 is floated, it should preferably be bypassed by a 1nF ...

X5165SIZ

Vendor:availPackage Cooled:INTERSILD/C:07+

Positive input supply voltage. This pin is connected to an external capacitor for energy storage. An internal current source supplies current from Vin to this pin. Once the voltage on VAUX reaches approximately 10.3 V, the current source turns OFF. It turns ON again once VAUX falls to 7 V. During normal operation, power is supplied to the IC via this pin, by means of an auxiliary winding. The startup circ...

X5165V

Package Cooled:TSSOP20D/C:08+/09+

Note 6: Load and line regulation are measured at constant junction temperature, and are guaranteed up to the maximum power dissipation of 30W. Power dissipation is determined by the input/output differential and the output current. Guaranteed maximum power dissipation will not be available over the full input/output range.

X5165V14

Vendor:XICORPackage Cooled:TSSOPD/C:1

Positive and negative power supply voltages and common (or ground) for the input stage. Common1 is the analog reference voltage for input signals. The voltage between Common1 and Common2 is the isolation voltage and appears across the internal high voltage barrier.

X5165V14

Vendor:XICORPackage Cooled:TSSOPD/C:1

Positive and negative power supply voltages and common (or ground) for the input stage. Common1 is the analog reference voltage for input signals. The voltage between Common1 and Common2 is the isolation voltage and appears across the internal high voltage barrier.

X5168 G

X5168-G

Vendor:XICORPackage Cooled:SOP8D/C:00+

ADJ: In the adjustable version, the user programs the output voltage with two external resistors. The resistors should be 0.1% for high accuracy. The output amplifier is configured as a noninverting operational amplifier. The resistors should meet the criteria of R3 || R4 < 100 Ω. Connect ADJ to VOUT for an output voltage of 1.2 V. Note that the point at which the feedback network is connected to ...

X5168S8

Button shape is self-aligning with cup- shaped probes Durable stainless steel case engraved with registration number withstands harsh environments Easily affixed with self-stick adhesive backing, latched by its flange, or locked with a ring pressed onto its rim Presence detector acknowledges when reader first applies voltage Meets UL#913 (4th Edit.); Intrinsically Safe Apparatus, Approved under Entity Co...

X5168V