Index "X"Vendor:INTERSILPackage Cooled:SOP8D/C:06+
Vendor:INTERSILPackage Cooled:SOP8D/C:06+
connected from Drain to Source internally. This diode helps to control inductive kick-back when a winding is de- energized. Optional resistors (50-100Ω) are shown in the circuit to dampen resonances due to wiring inductance and gate capacitance. They should be used if the transistors are mounted any more than a few inches from the ELM312.
Vendor:XICORPackage Cooled:SO-8D/C:06+
• N channel FET switches with no parasitic diode to VCC C Isolation under power-off conditions C No DC path to VCC or GND C 5V tolerant in OFF and ON state • 5V tolerant I/Os • Low RON - 4Ω typicalΩ • Flat RON characteristics over operating range • Rail-to-rail switching 0 - 5V • Bidirectional dataflow with near-zero delay: no added ground bounce &...
Vendor:XICORPackage Cooled:SO-8D/C:06+
International standard packages JEDEC TO-264 AA, epoxy meet UL 94 V-0, flammability classification miniBLOC, with Aluminium nitride isolation Low RDS (on) HDMOSTM process Rugged polysilicon gate cell structure Unclamped Inductive Switching (UIS) rated Low package inductance Fast intrinsic Rectifier
Vendor:INTERSILD/C:08+
Vendor:XICORPackage Cooled:SOP-8
High Speed Communication Line Protection USB 1.1 and 2.0 Power and Data Line Protection Digital Video Interface (DVI) Monitors and Flat Panel Displays Pb−Free Package May be Available. The G−Suffix Denotes a Pb−Free Lead Finish
Vendor:XICORPackage Cooled:SOIC
Through the choice of p-type or n-type silicon, and the selection of metal, one can tailor the characteristics of a Schottky diode. Barrier height will be altered, and at the same time CJ and RS will be changed. In general, very low barrier height diodes
Package Cooled:200D/C:XICOR
The contents of in this specification are subject to change without notice. ELAN Microelectronics assumes no responsibility for errors that may appear in this specification. ELAN Microelectronics makes no commitment to update, or to keep current, the information contained in this specification. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, a...
Note 2: The maximum power dissipation is dictated by TJMAX, JA, and the ambient temperature TA and must be derated at elevated temperatures. The maximum allowable power dissipation is PDMAX = (TJMAX − TA)/JA. For the LM4924, TJMAX = 150˚C. For the JAs, please see the Application Information section or the Absolute Maximum Ratings section.
Package Cooled:DIP-8P
Note 2: The maximum power dissipation is dictated by TJMAX, JA, and the ambient temperature TA and must be derated at elevated temperatures. The maximum allowable power dissipation is PDMAX = (TJMAX − TA)/JA. For the LM4924, TJMAX = 150˚C. For the JAs, please see the Application Information section or the Absolute Maximum Ratings section.
Vendor:intersilPackage Cooled:TSSOP-8D/C:dc0439
Aperture Jitter (∆t). The standard deviation of the delay between the hold command (input clock switched from hold to track state) and the instant at which the analog input is sampled, excluding clock source jitter. It is the total jitter if the clock source is jitter free (ideal). Jitter diverges slowly as measurement time increases because of 1/f noise, important at low frequencies (< 10 kHz). Th...
Vendor:XICORPackage Cooled:intersilD/C:00
Aperture Jitter (∆t). The standard deviation of the delay between the hold command (input clock switched from hold to track state) and the instant at which the analog input is sampled, excluding clock source jitter. It is the total jitter if the clock source is jitter free (ideal). Jitter diverges slowly as measurement time increases because of 1/f noise, important at low frequencies (< 10 kHz). Th...
Vendor:YAMAHAPackage Cooled:QFPD/C:04+Original
The standard device offers access times of 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus conten- tion the device contains separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
Vendor:CLCC
Package Cooled:MOX1
Package Cooled:SOT23
Vendor:MOTOROLAPackage Cooled:SDIPD/C:99+
The SRC input of the bq2060 measures battery charge and discharge current. The SRC ADC input converts the current signal from the series sense resistor and stores the result in Current(). The full-scale input range to SBC is limited to 250mV as shown in Table 2.
Vendor:MOTOROLAPackage Cooled:SDIPD/C:99+
The SRC input of the bq2060 measures battery charge and discharge current. The SRC ADC input converts the current signal from the series sense resistor and stores the result in Current(). The full-scale input range to SBC is limited to 250mV as shown in Table 2.
Vendor:7500Package Cooled:MOTD/C:06+
Vendor:MOTPackage Cooled:SOP20
Vendor:XCPackage Cooled:QFP-44D/C:04+
Large area flicker elimination through field doubling Additional elimination of interline flicker in field mode Field switching and selection in field mode Noise and cross-color reduction Stills 9-image display, still-in-picture, picture-in-still with different frame versions q Zoom with selection of enlarged picture segment (8 x 12 positions) q Pin-programmable operation without standard co...
Vendor:ST
Notes: 1. The algebraic convention, where most negative value is a minimum and most positive is a maximum, is used in this data sheet. 2. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing. 3. Guaranteed by design. 4. RON = RON max. - RON min. 5. Flatness is defined as the difference between the maximum and minimum value of On-Resistance measured.
Vendor:XILINXD/C:07+
The SPT1175 operates from a single +5.0 V power supply and has an internal voltage reference which eliminates the need for external reference circuitry. All digital inputs are CMOS compatible and the tri-state outputs are TTL-compat- ible. The SPT1175 is ideal for most video and image pro- cessing applications that require low power dissipation and low cost. The SPT1175 is available in 24-lead plastic ...
Vendor:XICPackage Cooled:SOP
Vendor:ST
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OEAB should be tied to VCC through a pullup resistor and OEAB and OEBA should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.
Vendor:STRPackage Cooled:ZIP5D/C:TO3P-7P
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments.
Vendor:TIPackage Cooled:TID/C:05+
Three Fan Tachometer Inputs Three Programmable 16-bit Counter/Timers Direct Battery Management with SMSC SentinelAlert! Analog to Digital Converter with C 8 channels, 8b/10b conversion C 20ms conversion time for 8 channels Digital to Analog Converter with SMSC SentinelAlert! C 3 channels, 8b conversion C 1.5ms conversion time for 3 channels 2-GPIOs with SMSC SentinelAlert! 2-Single pin remot...
Vendor:TIPackage Cooled:TID/C:05+
Features lRF capable MOSFETs lDouble metal process for low gate resistance lLow RDS (on) HDMOSTM process l Rugged polysilicon gate cell structure l Unclamped Inductive Switching (UIS) rated lLow package inductance - easy to drive and to protect l Fast intrinsic rectifier
Vendor:TID/C:05+
Features lRF capable MOSFETs lDouble metal process for low gate resistance lLow RDS (on) HDMOSTM process l Rugged polysilicon gate cell structure l Unclamped Inductive Switching (UIS) rated lLow package inductance - easy to drive and to protect l Fast intrinsic rectifier
Vendor:TIPackage Cooled:TID/C:05+
The following external interfaces are supported by the QDR™ NSE device x Single QDR™ NPU interface - QDR™ Clock Frequency up to 250 MHz - Supports QDR™ burst of 2 - Echo clocks supported (CQ, CQ) x Point-to-Point Cascading Interface - Up to eight NSEs can be cascaded using this scheme x Associated Data SRAM with standard ZBT® Interface x Boundary Scan JTAG Interface (I...
Vendor:STRPackage Cooled:TO3P-7PD/C:TO3P-7P
Consuming only 1.15 mA of supply current, the LMP7711 offers a high gain bandwidth of 17 MHz, enabling accurate amplification at high closed loop gains. The LMP7711 has a supply voltage range of 1.8V to 5.5V; which makes this an ideal choice for portable low power applications with low supply voltage requirements. In order to reduce the already low power consumption of the LMP7711, an enable function...
Vendor:STRPackage Cooled:TO3P-7D/C:00+
S1M8662A is CDMA/PCS/GPS Triple Mode IF/ baseband IC which is divided into three main parts - IF frequency processing, basband processing , and digital interface. The receiver IC (S1M8662A)and transmitter IC (S1M8657) are provided as a KIT. S1M8662A is a receiver IC, installed with a Rx AGC, Baseband Converter, Baseband analog filter, and A-D Converter. It can send a digital baseband signal to the digital bas...
Vendor:STRPackage Cooled:TO3P-7PD/C:06+
The upstream facing port can be connected to a Hi-Speed USB host or hub or to an Original USB host or hub. If the upstream facing port is connected to a Hi-Speed USB host or hub, then the ISP1521 will operate as a Hi-Speed USB hub. That is, it will support high-speed, full-speed and low-speed devices connected to its downstream facing ports. If the upstream facing port is connected to an Original USB host ...
Vendor:STRPackage Cooled:00+D/C:TO3P-7P
The HAL 805 is a recent member of the Micronas fam- ily of programmable linear Hall sensors. As an exten- sion to the HAL 800, it offers open-circuit detection and individual programming of different sensors which are in parallel to the same supply voltage.
Vendor:IntelD/C:4922
Vendor:MOTPackage Cooled:PGAD/C:05+
Clock Pulse Input (Active Rising Edge) Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Synchronous Reset Input (Active LOW) TRI-STATE Output Enable Inputs (Active LOW) Parallel Data Inputs or TRI-STATE Parallel Outputs Serial Outputs
Vendor:MOTPackage Cooled:PGAD/C:05+
Each channel of the HA-2400/04/05 can be controlled and operated with suitable feedback networks in any of the standard op amp configurations. This specialization makes these amplifiers excellent components for multiplexing signal selection and mathematical function designs. With 30V/µs slew rate, 40MHz gain bandwidth and 30MΩ input impedance these devices are ideal building blo...
Vendor:MOTOPackage Cooled:QFPD/C:97+
The RC4700 processor also supports a supervisor mode in which the virtual address space is 256.5GB (2.5GB in 32-bit address mode), divided into three regions that are based on the high-order bits of the virtual address. If the RC4700 is configured for 64-bit virtual addressing, the virtual address space layout is an upwardly compatible extension of the 32-bit virtual address space layout. Figure 4 on pa...
Vendor:MOTOPackage Cooled:QFPD/C:97+
The RC4700 processor also supports a supervisor mode in which the virtual address space is 256.5GB (2.5GB in 32-bit address mode), divided into three regions that are based on the high-order bits of the virtual address. If the RC4700 is configured for 64-bit virtual addressing, the virtual address space layout is an upwardly compatible extension of the 32-bit virtual address space layout. Figure 4 on pa...
Vendor:S+MPackage Cooled:ZIP-5
Vendor:S+M
The three major blocks of the MT8931C, consisting of the system serial interface (ST-BUS), HDLC transceiver, and the digital subscriber loop interface (S-interface) are interconnected by high speed data busses.Data sent to and received from the S-interface port (B1, B2 and D channels) can be accessed from either the parallel microprocessor port or the serial ST-BUS port. This is also true for SNIC control a...
Vendor:EPCOSPackage Cooled:ZIP5D/C:96
This pin is the reference select pin and the external reference input. If (VA - 0.3V) < VREF < VA, the internal 1.0V reference is selected. If AGND < VREF < (AGND + 0.3V), the internal 0.5V reference is selected. If a voltage in the range of 0.8V to 1.2V is applied to this pin, that voltage is used as the reference. VREF should be bypassed to AGND with a 0.1 µF capacitor when an ex...
Vendor:EPCOSPackage Cooled:ZIP5D/C:96
This pin is the reference select pin and the external reference input. If (VA - 0.3V) < VREF < VA, the internal 1.0V reference is selected. If AGND < VREF < (AGND + 0.3V), the internal 0.5V reference is selected. If a voltage in the range of 0.8V to 1.2V is applied to this pin, that voltage is used as the reference. VREF should be bypassed to AGND with a 0.1 µF capacitor when an ex...
Vendor:EPCOSPackage Cooled:99/06+D/C:1875
V+ (Pin 8): Positive Power Supply. This supply must be kept free from noise and ripple. It should be bypassed directly to a ground plane with a quality 0.1µF capacitor. Additional bypass may be necessary for operation at high frequency or under larger loads.
DAC08 applications include 8-bit, 1 µs A/D converters, servo motor and pen drivers, waveform generators, audio encoders and attenuators, analog meter drivers, programmable power supplies, CRT display drivers, high-speed modems and other applications where low cost, high speed and complete input/ output versatility are required.
Package Cooled:PLCC
DESCRIPTION: The CENTRAL SEMICONDUCTOR BZX84C2V4 Series are surface mount silicon Zener diodes. These high quality voltage regulating diodes are designed for use in industrial, commercial, entertainment and computer applications.
Vendor:EPCOSPackage Cooled:ZIP5
Input bus select / I2C clock input. The operation of this pin depends on whether the I2C interface is enabled or disabled. This pin is only 3.3-V tolerant. When I2C is disabled (ISEL = low), a high level selects 24-bit input, single-edge input mode. A low level selects 12-bit input, dual-edge input mode. When I2C is enabled (ISEL = high), this pin functions as the I2C clock input (see the I2C register ...
Vendor:EPCOSPackage Cooled:ZIP5
Input bus select / I2C clock input. The operation of this pin depends on whether the I2C interface is enabled or disabled. This pin is only 3.3-V tolerant. When I2C is disabled (ISEL = low), a high level selects 24-bit input, single-edge input mode. A low level selects 12-bit input, dual-edge input mode. When I2C is enabled (ISEL = high), this pin functions as the I2C clock input (see the I2C register ...
Vendor:XICORD/C:2002
maintenance, a PRBS/QRSS generation/detection circuit is integrated in the chip, and different types of loopbacks can be set according to the appli- cations. Four different kinds of line terminating impedance, 75 Ω, 100 Ω, 110 Ω and 120 Ω are selectable. The chip also provides driver short-circuit protection and internal protection diode. The chip can be controlled by either softwa...
Vendor:INTERD/C:00
Universal Synchronous/Asynchronous Receiver-trans- mitter (USART) A full-duplex USART channel Programmable baud rate Synchronous mode with either internal or external clock 7-, 8- or 9-bit protocols Data transfer via Interrupt, polling Data double buffering with DMA support
The users software can invoke the Idle Mode When the microcontroller is in this mode power consump- tion is reduced The Special Function Registers and the onboard RAM retain their values during Idle but the processor stops executing instructions Idle
Vendor:MotorolaD/C:96
Vendor:EPCOS
The ChipCorder I5216 is an 8 to 16 minute Voice and Data Record and Playback system with integrated Voice band CODEC. The device works on a single 2.7V to 3.3V supply, and has fully integrated system functions, including: AGC, microphone preamplifier, speaker driver, memory and CODEC. The CODEC meets the PCM conformance specification of the G.714 recommendation. Its µ- Law and A-law compander meets th...
Vendor:SAWPackage Cooled:ZIP-5D/C:94
Digital Signal Processors (DSPs): TMS320C67x (C6711, C6711B, C6711C, and C6711D) − Eight 32-Bit Instructions/Cycle − 100-,150-,167-,200-,250-MHz Clock Rates − 10-, 6.7-, 6-, 5-, 4-ns Instruction Cycle Time − 600, 900, 1000, 1200, 1500 MFLOPS Advanced Very Long Instruction Word (VLIW) C67x DSP Core − Eight Highly Independent Functional Units: − Four ...
Vendor:EPCOSPackage Cooled:ZIP5D/C:08+
Vendor:S+M SAWPackage Cooled:ZIP5D/C:99
VCC1 is the positive supply voltage pin for the transmitter output amplifier and the transmitter base-band circuitry. VCC1 is usually connected to the positive supply through a ferrite RF decoupling bead which is bypassed by an RF capacitor on the supply side. See the description of VCC2 (Pin 16) for additional information.
Vendor:EPCOSPackage Cooled:N/AD/C:06+
Vendor:EPCOSD/C:00+
In-band interference rejection for an unmodulated interfering signal at 100kHz. low side from the wanted modulated signal at 433.92MHz. to achieve a Bit Error Rate =0.01. Figure 5 illustrates a suitable test set-up for measuring the interference rejection and selectivity of the receiver.
Vendor:EPCOSPackage Cooled:EPCOSD/C:DIP
A typical communication on the Microwire bus is made through the CS, SK, DI and DO signals. To facilitate various operations on the Memory array, a set of 7 instructions are implemented on NM93C06. The format of each instruction is listed under Table 1.
Vendor:EPCOSPackage Cooled:87+D/C:04+
A typical communication on the Microwire bus is made through the CS, SK, DI and DO signals. To facilitate various operations on the Memory array, a set of 7 instructions are implemented on NM93C06. The format of each instruction is listed under Table 1.
Vendor:SID5Package Cooled:27D/C:04+
Hynix HYMD216726A(L)6-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
Vendor:SID5Package Cooled:ZIP5D/C:04+
Hynix HYMD216726A(L)6-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
Package Cooled:0007+D/C:5000
Vendor:MOTPackage Cooled:SOP8D/C:04+
Vendor:MOTPackage Cooled:SOP8D/C:04+
Package Cooled:DIP
Vendor:NOPackage Cooled:DIPD/C:96+
• CASE: Hermetically sealed DO-213AB glass MELF package • TERMINALS: End caps, tin-lead plated solderable per MIL-STD-750, method 2026 • POLARITY: Cathode indicated by band. • MARKING: Cathode band only • TAPE & REEL optional: Standard per EIA-481-B with 12 mm tape, 1500 per 7 inch reel or 5000 per 13 inch reel (add TR suffix to part number) • WEIGHT: 0.0...
Vendor:EPCOSD/C:05+
Under-Voltage Lockout An Under-Voltage Lock-Out (UVLO) inhibits the operation of the converter until the input voltage is above the UVLO threshold (see the applicable data sheet specification). Below this voltage, the modules output is held off, irrespective of the state of the Inhibit control (pin 3). If the Inhibit control is connected to CVin (pin 2), the module will automatically power up when the...
Vendor:EPCOSPackage Cooled:SOPD/C:05+
Hynix HYMD512G726(L)8M-K/H/L series is Low Profile registered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 128Mx72 high-speed memory arrays. Hynix HYMD512G726(L)8M-K/H/L series consists of eighteen 64Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD512G726(L)8M-K/H/L series provide a high performance 8-byte interface...
Vendor:EPCOSD/C:05+
Hynix HYMD512G726(L)8M-K/H/L series is Low Profile registered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 128Mx72 high-speed memory arrays. Hynix HYMD512G726(L)8M-K/H/L series consists of eighteen 64Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD512G726(L)8M-K/H/L series provide a high performance 8-byte interface...
Vendor:BGTPackage Cooled:QFP2323-132D/C:03+
Vendor:STPackage Cooled:PLCC-44D/C:94
Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write. The IDT71V2546/48 contain data I/O, address and control signal registers. Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable (CEN) pin allows operation of the IDT71V2546/48 to be suspe...
Vendor:ST
Vendor:ST
Vendor:TID/C:02+
The Retransmit (RT) input is active in the stand-alone and width expansion modes. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred and at least one word has been read since the last RS cycle. A HIGH pulse on RT resets the internal read pointer to the first physical location of the FIFO. WCLK and RCLK may be free running but mus...
A better indicator of achievable receiver range performance is usually given by its selectivity, often stated as intermediate frequency (IF) or radio frequency (RF) bandwidth, depending on receiver topology. Selectivity is a measure of the rejection by the receiver of ether noise. More selective receivers will almost invariably provide better range. Only when the receiver selectivity is so high that most of...
Vendor:EPCOSPackage Cooled:QFN
The Philips Semiconductors FAST loads solve this problem by reducing the load capacitor lead inductance by paralleling three 15pF chip capacitors. The resulting load is 45pF. At the same time, since smaller value caps are used to build up the capacitive load, the associated series resonant point is above 1.2GHz.
Vendor:EPCOSPackage Cooled:QFN
The Philips Semiconductors FAST loads solve this problem by reducing the load capacitor lead inductance by paralleling three 15pF chip capacitors. The resulting load is 45pF. At the same time, since smaller value caps are used to build up the capacitive load, the associated series resonant point is above 1.2GHz.
Vendor:TIPackage Cooled:BGA1010D/C:99+
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/
Vendor:N/APackage Cooled:SOP8D/C:08+09+
tolerance voltage regulation. Through the use of external resistors, the RC5033 can generate accurate output voltages from 2.0V up to 3.6V. An integrated Over-Voltage protection function constantly monitors the output voltage and shuts down the power to the CPU in the event of a out-of- tolerance voltage situation, thereby protecting the CPU. The programmable oscillator can operate from 200KHz to grea...
Vendor:XICORPackage Cooled:01+D/C:760
FUNCTIONAL DESCRIPTION The LS155 and LS156 are Dual 1-of-4 Decoder/Demulti- plexers with common Address inputs and separate gated Enable inputs. When enabled, each decoder section accepts the binary weighted Address inputs (A0, A1) and provides four mutually exclusive active LOW outputs (O0 C O3). If the Enable requirements of each decoder are not met, all outputs of that decoder are HIGH. Each dec...
Vendor:XICORPackage Cooled:01+D/C:760
FUNCTIONAL DESCRIPTION The LS155 and LS156 are Dual 1-of-4 Decoder/Demulti- plexers with common Address inputs and separate gated Enable inputs. When enabled, each decoder section accepts the binary weighted Address inputs (A0, A1) and provides four mutually exclusive active LOW outputs (O0 C O3). If the Enable requirements of each decoder are not met, all outputs of that decoder are HIGH. Each dec...
Vendor:EPCOSPackage Cooled:QFN
The converters incorporate a fixed frequency single for- ward topology with magnetic feedback and an internal EMI filter. These converters are capable of meeting the conducted emissions and conducted susceptibility re- quirements of MIL-STD-461C without any additional components. All models include an external inhibit port and have an adjustable output voltage. They are en- closed in a hermetic 1.5&q...
Package Cooled:00+D/C:QFP
3. All devices are guaranteed to trigger at an IF value less than or equal to max IFT. Therefore, recommended operating IF lies between max IFT (30 mA for MOC3020M, 15 mA for MOC3010M and MOC3021M, 10 mA for MOC3011M and MOC3022M, 5 mA for MOC3012M and MOC3023M) and absolute max IF (60 mA).
Vendor:MOTPackage Cooled:00+D/C:QFP
3. All devices are guaranteed to trigger at an IF value less than or equal to max IFT. Therefore, recommended operating IF lies between max IFT (30 mA for MOC3020M, 15 mA for MOC3010M and MOC3021M, 10 mA for MOC3011M and MOC3022M, 5 mA for MOC3012M and MOC3023M) and absolute max IF (60 mA).
Vendor:TIPackage Cooled:2005
These devices are a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple
Vendor:MOTPackage Cooled:MOT
Once the chemistry is determined, the bq2000 completes the fast charge with the appropriate charge algorithm (Table 1). The user can customize the algorithm by programming the device using an external resistor and a capacitor connected to the RC pin, as discussed in later sections.
Vendor:MOTPackage Cooled:SOP-8
Vendor:TIPackage Cooled:TSOP56D/C:06+
______ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to the maximum current ratings. 3/ For case outlines H and X, derate above TA = +70C linearly at 5.26 mW/C. ...
Vendor:TIPackage Cooled:TSOP56
______ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to the maximum current ratings. 3/ For case outlines H and X, derate above TA = +70C linearly at 5.26 mW/C. ...
Vendor:TIPackage Cooled:8000D/C:00+
data stream. This gap time should have at least same length as the burst. • Up to 2200 short bursts per second can be received continuously. Some examples for suitable data format are: NEC Code, Toshiba Micom Format, Sharp Code, RC5 Code, RC6 Code, RCMM Code, R-2000 Code, RECS-80 Code. When a disturbance signal is applied to the TSOP11..KA1 it can still receive the data signal. How- ever the...
Vendor:XICOPPackage Cooled:DIPD/C:07/08+
Partial page write allowed 8-byte page write modes Write operation with built-in timer Hardware controlled write protection 40-year data retention 106 erase/write cycles per word 8-pin DIP/SOP/TSSOP package Commerical temperature range (0C to +70C)