Z0842004CME

Vendor:ZILOG

Z0842004CSE

Vendor:ZILOG

NM93C06 is a 256-bit CMOS non-volatile EEPROM organized as 16 x 16-bit array. This device features MICROWIRE interface which is a 4-wire serial bus with chipselect (CS), clock (SK), data input (DI) and data output (DO) signals. This interface is compat- ible to many of standard Microcontrollers and Microprocessors. There are 7 instructions implemented on the NM93C06 for various Read, Write, Erase, and ...

Z0842004CSE Z80PIO

Vendor:ZILOGPackage Cooled:CDIP40D/C:88

Z0842004CSEPIO

Vendor:ZILO

Z0842004DSE Z80A PIO

Vendor:ZILOGPackage Cooled:DIP

Z0842004PSC

Vendor:ZILOG

The CS8920As highly efficient StreamTrans- ferTM and Auto-Switch DMA options, make it an excellent choice for high-performance, low- cost, ISA adapter cards (Fig. 1.2). The CS8920As wide range of configuration options, listed below, allow engineers to design Ethernet solutions that meets their particular system re- quirements.

Z0842004PSC(Z80PIO)

Vendor:ZILOGPackage Cooled:DIP

DESCRIPTION The device is manufactured using high voltage Multi Epitaxial Planar technology for high switching speeds and medium voltage capability. It uses a Cellular Emitter structure with planar edge termination to enhance switching speeds while maintaining the wide RBSOA. The device is designed for use in lighting applications and low cost switch-mode power supplies.

Z0842004PSC-Z80P10

Vendor:ZILOGPackage Cooled:DIPD/C:120

Z0842004VSC

Vendor:ZIOLGPackage Cooled:PLCC

functionaloperation of the device at these or any other conditions beyond those indicated under recommendedoperating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Specifications are assured operating at maximum device limits for QFN package only, unless otherwise specified.

Z0842004VSC

Vendor:ZIOLGPackage Cooled:PLCC

functionaloperation of the device at these or any other conditions beyond those indicated under recommendedoperating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Specifications are assured operating at maximum device limits for QFN package only, unless otherwise specified.

Z0842006

Vendor:ZILOGD/C:07/08+

Z0842006

Vendor:ZILOGPackage Cooled:PLCC44D/C:07/08+

Z0842006CSE Z80PIO

Vendor:ZILOGPackage Cooled:CDIP40金D/C:87/88

Z0842006DSE Z80A PIO

Vendor:ZILOGPackage Cooled:DIPD/C:01+

Z0842006DSE Z80PIO

Vendor:ZILOGPackage Cooled:CDIP40D/C:89/92

Z0842006PSC/Z80PIO

Vendor:ZILOGPackage Cooled:DIP40D/C:08+

Notes: (1) ISR-will operate down to no load with reduced specifications. (2) If the remote sense ground is not used, pin 13 must be connected to pin 14 for optimal output voltage accuracy. (3) The Standby control (pin 8) has an internal pull-up, and if left open-circuit the module will operate when input power is applied. A small low-leakage (<100nA) MOSFET must be used to control this input. The ope...

Z0842006VSC Z80 PIO

Z0842006VSC/Z80PIO

Vendor:ZILOGPackage Cooled:PLCC44D/C:01+

The general purpose memory portion of the device is a CMOS serial EEPROM array with Xicors Block LockTM protection. This memory may be used to store fiber optic module manufacturing data, serial numbers, or various other system parameters.

Z0843002CMB/883C

Vendor:ZILOGPackage Cooled:CDIP28D/C:8851

Z0843004

Vendor:ZILOGPackage Cooled:PLCC44D/C:07/08+

Z0843004

Vendor:ZILOGD/C:07/08+

Z0843004CMB

Vendor:ZILOGPackage Cooled:DIP

The Z0843004CMB dual-band device has one band selection pin (BANDSEL1 on pin 14). When BANDSEL1 is set to logic 0, the EGSM900 receiver path is active. The LO frequency needs to be higher than the RF input frequency (i.e., a high side injection is used). When BANDSEL1 is set to logic 1, the DCS1800 receiver path is active. The LO frequency needs to be less than the RF input frequency (i.e., a low-side ...

Z0843004CMB 8301601XA

Vendor:ZILOG

Z0843004CMB883C

Vendor:ZILOGPackage Cooled:CDIP28D/C:9342

NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full-Scale. (3) 2-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the 2-tone fundamental envelope. (4) Effective Number of Bits (ENOB) is defined by (SINAD C 1.76)/6.02. (5) A 50kΩ pull-dow...

Z0843004CME Z80CTC

Vendor:ZILOGPackage Cooled:DIPD/C:9423

Z0843004CME Z80CTC

Vendor:ZILOGPackage Cooled:DIPD/C:9423

Z0843004CMEZ80CTC

FXL translators offer an advantage in that either VCC may be powered up first. This benefit derives from the chip design. When either VCC is at 0 volts, outputs are in a HIGH-Impedance state. The control inputs (T/R and OE) are designed to track the VCCA supply. A pull-up resistor tying OE to VCCA should be used to ensure that bus con- tention, excessive currents, or oscillations do not occur during p...

Z0843004CSE Z80 CTC

Vendor:ZILOGPackage Cooled:CDIP28D/C:——

Z0843004DEA

Vendor:ZILOGPackage Cooled:CDIP28D/C:——

Electrical Characteristics (Continued) The following specifications apply for V a e AV a e DV a e a 5 0 VDC VREF a e a 4 096 VDC VREFb e VINb e GND Vb e b5 0 VDC and fCLK e 2 5 MHz unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e a 25 C (Notes 8 9 and 10) (Continued)

Z0843004DSA

Vendor:ZILOGPackage Cooled:DIP陶瓷D/C:88

Efficient 16-bit 56800E family hybrid controller engine with dual Harvard architecture As many as 60 Million Instructions Per Second (MIPS) at 60MHz core frequency Single-cycle 16 16-bit parallel Multiplier-Accumulator (MAC) Four 36-bit accumulators, including extension bits Arithmetic and logic multi-bit shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Thr...

Z0843004DSE Z80A CTC

Vendor:ZILOGPackage Cooled:DIP

Z0843004VSC

Vendor:ZILOGPackage Cooled:PLCC44

Sony Ericsson has earlier announced (June 24, 2003) the decision to increase its focus on GSM/EDGE/UMTS and Japanese standards. Further to the phase-out of Sony Ericssons American CDMA business and GSM R&D activities in Munich, total restructuring costs are estimated to approximately Euro 70 million of which Euro 58 million has been recognized in the second quarter. The restructuring activities are well ...

Z0843004VSC

Vendor:ZILOGPackage Cooled:PLCC44D/C:05+

Sony Ericsson has earlier announced (June 24, 2003) the decision to increase its focus on GSM/EDGE/UMTS and Japanese standards. Further to the phase-out of Sony Ericssons American CDMA business and GSM R&D activities in Munich, total restructuring costs are estimated to approximately Euro 70 million of which Euro 58 million has been recognized in the second quarter. The restructuring activities are well ...

Z0843006

Vendor:ZILOGD/C:08+

Z0843006CSE

may be accessed by hardware or software operation. The hardware operation mode can be used by an external pro- grammer to identify the correct programming algorithm for the Atmel product. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49BV/LV001(N)(T) features DATA polling ...

Z0843006DEA

Vendor:ZILOGPackage Cooled:DIPD/C:06+

Tantalum Characteristics Tantalum capacitors with a minimum 10-V rating are recommended on the output bus, but only the AVX TPS Series, Sprague 594/595 Series, or Kemet T495/T510 Series. These AVX, Sprague, and Kemet capacitors are specified over other types due to their higher surge current, excellent power dissipation and ripple current ratings. As a caution, the TAJ Series by AVX is not recommended...

Z0843006DEA

Vendor:ZILOGPackage Cooled:DIPD/C:06+

Tantalum Characteristics Tantalum capacitors with a minimum 10-V rating are recommended on the output bus, but only the AVX TPS Series, Sprague 594/595 Series, or Kemet T495/T510 Series. These AVX, Sprague, and Kemet capacitors are specified over other types due to their higher surge current, excellent power dissipation and ripple current ratings. As a caution, the TAJ Series by AVX is not recommended...

Z0843006DSE

Vendor:ZILOGPackage Cooled:DIP-28D/C:06+

The Z0843006DSE is a 600kHz, PWM dc/dc boost switching regulator available in a 2mm x 2mm MLF™ package option. High power density is achieved with the Z0843006DSEs internal 34V / 1.2A switch, allowing it to power large loads in a tiny footprint. The Z0843006DSE is a version of the MIC2295 1.2MHz, PWM dc/dc boost switching regulator, that offers improved efficiency resulting from 600kHz operation. The ...

Z0843006DSE Z80A CTC

Vendor:ZILOGPackage Cooled:DIP

Z0843006DSE Z80A CTC

Vendor:ZILOGPackage Cooled:DIP

Z0843006PSC

Vendor:ZILOGPackage Cooled:DIP

As the multiple keying is possible , key No .1~6 are capable of output 63 commands through a combination of D1~D6 data . Key No . 7~18 are the single-shot keys for output 12 commands , and 75 commands can be output through a combination of continuous key (multiple keying is possible ) and single-shot key .

Z0843006PSC/Z80CTC

Vendor:ZILOGPackage Cooled:DIP28D/C:08+

When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Z0843006PSC-Z80

Vendor:ZILOGPackage Cooled:DIP/28D/C:86+

NOTES: 1. All typical values are at VCC = 5 V, Tamb = 25 C. 2. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND 3. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (A or B) terminals.

Z0844004CMB883C

Vendor:ZILOG

The AT49SN/SV12804 is divided into thirty-two memory planes. A read operation can occur in any of the thirty-one planes which is not being programmed or erased. This concurrent operation allows improved system performance by not requiring the sys- tem to wait for a program or erase operation to complete before a read is performed. To further increase the flexibility of the device, it contains an Erase Susp...

Z0844004CMB883C

Vendor:ZILOG

The AT49SN/SV12804 is divided into thirty-two memory planes. A read operation can occur in any of the thirty-one planes which is not being programmed or erased. This concurrent operation allows improved system performance by not requiring the sys- tem to wait for a program or erase operation to complete before a read is performed. To further increase the flexibility of the device, it contains an Erase Susp...

Z0844004CSE

Vendor:ZILOG

Z0844004CSE-SIO

Vendor:ZILOGPackage Cooled:DIPD/C:01+

Z0844004CSE-SIO

Vendor:ZILOGPackage Cooled:DIP

Z0844004DSA

Vendor:ZILOGPackage Cooled:ZILOGD/C:88

• CMOS for optimum speed/power • Windowed for reprogrammability • High speed 20 ns (Commercial) • Low power 660 mW (Commercial) • Super low standby power Less than 85 mW when deselected • EPROM technology 100% programmable • 5V 10% VCC, commercial and military • TTL-compatible I/O • Direct replacement for 27C64 EPROMs

Z0844004DSE Z80A SIO/O

Vendor:ZILOGPackage Cooled:DIPD/C:01+

Z0844004PSC(Z80A-SIO/0

Vendor:ZILOGPackage Cooled:DIPD/C:N/A

Z0844004PSC/Z80SIO/O

Vendor:ZILOG

Z0844006DSE Z80A SIO/O

Vendor:ZILOGPackage Cooled:DIP

Z0844006DSE Z80A SIO/O

Vendor:ZILOGPackage Cooled:DIP

Z0844006PSC

Vendor:ZILOGPackage Cooled:DIP

The Z0844006PSC EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in mounting hole rows on 15,2-mm (600-mil) centers. The Z0844006PSC is offered with two choices of temperature ranges, 0C to 70C (JL suffix) and C 40C to 85C (JE suffix). See Table 1.

Z0844006PSC/Z80SIO/O

Vendor:ZILOG

Z084406CSE

CH1 Soft-Start Input CH5 Enable Input CH6 Enable Input Step-Up Converter Switching Node CH1 Enable and Chip Enable Input Power Ground Power Ground CH2 Enable Input Step-Down Converter Switching Node CH3 Enable Input CH4 Enable Input CH2 Soft-Start Input Open-Drain, Active Low, Power Good for Step-Down Short Circuit Protection Input Step-Down Converter Input Step-Down Converter Compens...

Z0844104CME

Vendor:ZILOGPackage Cooled:DIPD/C:00+

1) CPD is defined as the value of the ICs internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x f IN + ICC/4 (per circuit)

Z0844104CME

Vendor:ZILOGPackage Cooled:DIPD/C:96+

1) CPD is defined as the value of the ICs internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x f IN + ICC/4 (per circuit)

Z0844104PSC

Vendor:ZiLOGPackage Cooled:DIP-40PD/C:DIP-40P

S0 Pin The S0 pin is used to select the mode of operation as shown in Table 1. The S0 pin contains an internal Schmitt trigger as part of its input to improve noise immunity. The S0 pin has an inter- nal pullCdown device in order to provide a low level when the pin is left unconnected. S1 Pin The S1 pin is used to select the mode of operation, as shown in Table 1. The S1 pin contains an intern...

Z0844104PSC

Vendor:ZiLOGPackage Cooled:91+D/C:91+

S0 Pin The S0 pin is used to select the mode of operation as shown in Table 1. The S0 pin contains an internal Schmitt trigger as part of its input to improve noise immunity. The S0 pin has an inter- nal pullCdown device in order to provide a low level when the pin is left unconnected. S1 Pin The S1 pin is used to select the mode of operation, as shown in Table 1. The S1 pin contains an intern...

Z0844204CSE

Z0844204DSE Z80A SIO/2

Vendor:ZILOGPackage Cooled:DIP

Z0844206PSC/Z80SIO/2

Vendor:ZILOGPackage Cooled:DIP40D/C:08+

1. All characteristics are measured with C = 0.1µF from Pin 1 to GND, and with C = 0.1µF from Pin 3 to GND. 2. Hysteresis is the difference between the positive going input threshold voltage. V T+, and the negative going input threshold voltage, VT-.

Z0844404

Vendor:ZILOGPackage Cooled:PLCC44

Z0844404VSC

Vendor:ZILOGPackage Cooled:PLCC

DESCRIPTION Using the latest high voltage technology based on a patented strip layout, STMicroelectronics has designed an advanced family of IGBTs, the Pow- erMESH™ IGBTs, with outstanding performances. The suffix S identifies a family optimized achieve minimum on-voltage drop for low frequency appli- cations (<1kHz).

Z0847004PSC

Vendor:ZILOGPackage Cooled:N AD/C:04+

DIGITAL DC CHARACTERISTICS Unless otherwise noted, these specifications apply for V+ = 4.5V to 5.5V for the LM74-5 MDA and V+ = 3.0V to 3.6V for the LM74-3 MDA.(Note 5). Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ=+25˚C, unless otherwise noted.

Z0847004PSG

NOTES: (1) Test levels: (A) 100% tested at 25C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (2) Junction temperature = ambient for 25C guaranteed specifications. (3) Junction temperature = ambient at low temperature limit: junction temperature = ambient +23C at high temperature limit for over temperatur...

Z084C0008VSC

Vendor:ZILPackage Cooled:PLCCD/C:.

Input bus select / I2C clock input. The operation of this pin depends on whether the I2C interface is enabled or disabled. This pin is only 3.3-V tolerant. When I2C is disabled (ISEL = low), a high level selects 24-bit input, single-edge input mode. A low level selects 12-bit input, dual-edge input mode. When I2C is enabled (ISEL = high), this pin functions as the I2C clock input (see the I2C register ...

Z084C0008VSC

Vendor:ZILPackage Cooled:PLCC

Input bus select / I2C clock input. The operation of this pin depends on whether the I2C interface is enabled or disabled. This pin is only 3.3-V tolerant. When I2C is disabled (ISEL = low), a high level selects 24-bit input, single-edge input mode. A low level selects 12-bit input, dual-edge input mode. When I2C is enabled (ISEL = high), this pin functions as the I2C clock input (see the I2C register ...

Z08523016VSC

Vendor:ZILOGPackage Cooled:00+D/C:1

Z0853004CSA

Z0853004DSA

Vendor:ZILOGPackage Cooled:DIPD/C:N/A

In addition to increased performance and FIFO size, the OXCF950 also provides enhanced features including improved flow control. Automated software flow control using Xon/Xoff and automated hardware flow control using CTS#/RTS# and DSR#/DTR# prevent FIFO over-run. Flow control and interrupt thresholds are fully programmable and readable, enabling programmers to fine- tune the performance of their syst...

Z0853004DSE

Vendor:ZILOGPackage Cooled:PLCC28D/C:N/A

operations and low power and low noise applications. It can be interfaced to 5V signal environment for inputs in mixed 3.3/5V system. It has more speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

Z0853004LMB

Vendor:ZILOGPackage Cooled:LCC44D/C:杂

Z0853004PSC(8530-4)

Vendor:ZILOGD/C:9437

The MAX3058 features four different modes of opera- tion: high speed, slope control, standby, and shutdown. The MAX3059 features three different modes of opera- tion: high speed, slope control, and shutdown. High- speed mode allows data rates up to 1Mbps. In slope-control mode, the slew rate may be optimized for data rates up to 500kbps, so the effects of EMI are reduced, and unshielded twisted or parallel c...

Z0853004VSC

Vendor:ZILOGPackage Cooled:PLCC

VCC1 is the positive supply voltage pin for the transmitter output amplifier and the transmitter base-band circuitry. VCC1 is usually connected to the positive supply through a ferrite RF decoupling bead which is bypassed by an RF capacitor on the supply side. See the description of VCC2 (Pin 16) for additional information.

Z0853006CMB/883C

Servo-Tek low ripple DC tachometer generators satisfy the need for a cost effective, very low ripple tachometer. In addition to being the first economical low ripple units of their type, the F-Series tachometers incorporate all the desirable features of the standard units such as temperature compensation, long brush life, excellent linearity, and small dimensions.

Z0853006CME

Vendor:ZILOGPackage Cooled:DIPD/C:88+

NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. The test limit for this parameter is 5µA at TA = C55C. 5. This parameter is guaranteed but no...

Z0853006DSA

Vendor:ZILOGPackage Cooled:DIPD/C:N/A

Conforms to POCSAG standard for pagers 512 or 1200 bps signal speed Supports tone, numeric or character call messages Battery-saving function for low battery consump- tion BS1 (RF control main output signal) and BS3 (PLL setup signal) 60-step setup time settingfor BS3, 50.8 ms (max) at 1200 bps and 119.1 ms (max) at 512 bps Note that (BS3 setup time) − (BS1 setup time) should be set to 2. BS...

Z0853006PSL

Package Cooled:DIP

Z0853008DEASCC

Vendor:ZILOGPackage Cooled:CDIP40

Z0853008PSG

Z0853008VSC

Vendor:ZILOGPackage Cooled:ＰＬＣＣ

The flowchar t in the Programming section of the EPROM Products Data Book (Section 5, Figure 5-1) shows AMDs Flashrite algorithm. The Flashrite algo- rithm reduces programming time by using a 100 µs pro- gramming pulse and by giving each address only as many pulses to reliably program the data. After each pulse is applied to a given address, the data in that ad- dress is verified. If the data d...

Z0853008VSC00TR

Vendor:ZILOGPackage Cooled:92+D/C:PLCC/44

The 4-bit analog channel-select address for the next conversion cycle is presented to the ADDRESS terminal (MSB first) and is clocked into the address register on the first four leading edges of I/O CLOCK. This address selects one of 14 inputs (11 analog inputs or 3 internal test inputs).

Z0853008VSC-SCC

Vendor:ZILOGPackage Cooled:01+D/C:12

The Hynix HYM76V8C735HGT8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 64Mbytes memory. The Hyundai HYM76V8C735HGT8 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.

Z0853604CMB

This 16-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

Z0853604CMB(Z80CIO) 8300101QA

Vendor:ZILOGPackage Cooled:CDIP40D/C:9145

Z0853604LMB

Vendor:ZILOG

Z0853604PSC

Vendor:ZILOGPackage Cooled:DIP40D/C:8840+

DETAILED FEATURES High Definition Programmable Features (720p/1080i) 2 Oversampling (148.5 MHz) Internal Test Pattern Generator (Color Hatch, Black Bar, Flat Field/Frame) Fully Programmable YCrCb to RGB Matrix Gamma Correction Programmable Adaptive Filter Control Programmable Sharpness Filter Control CGMS-A (720p/1080i)

Z08536060

Vendor:ZLIOD/C:DIP

Z0853606CMB

Vendor:ZILOG

• Fast: Optimized for medium operating frequencies ( 1-5 kHz in hard switching, >20 kHz in resonant mode). • Generation 4 IGBT design provides tighter parameter distribution and higher efficiency than Generation 3 • IGBT co-packaged with HEXFREDTM ultrafast, ultra-soft-recovery anti-parallel diodes for use in bridge configurations • Industry standard D2Pak package

Z0853606CMB/883C

Vendor:ZILOGPackage Cooled:CDIP40金面金脚D/C:88/89+

Z0853606CMECIO

Vendor:ZILOGPackage Cooled:DIPD/C:500

Z0853606DSE

Vendor:ZLIOD/C:55

For the purposes of simplification, the following descrip- tions will assume WE# is toggled to initiate an Erase or Program. Toggling the applicable CE# will accomplish the same function. (Note, there are separate timing diagrams to illustrate both WE# and CE# controlled Program or Write commands.)

Z0853606VEC

Vendor:ZILOGPackage Cooled:600D/C:N/A

These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

Z0853606VEC-CIO

Vendor:ZILOGPackage Cooled:01+D/C:6

The M41T81S Serial Access TIMEKEEPER ® SRAM is a low power Serial RTC with a built-in 32.768kHz oscillator (external crystal controlled). Eight bytes of the SRAM (see Table 2., page 12) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 12 bytes of SRAM provide status/ control of Alarm, Watchdog and Square Wave functions. Addresses an...

Z0853606VSC

Vendor:ZPackage Cooled:PLCC44D/C:O3

TTL/CMOS Reference input pre-scalar and Zero Delay MUX divider select inputs. The two-bit input pre-scalar divides the input reference frequency by /1, /2, /4, or /8. RSEL0 is the LSB bit. See Reference Input Divider and Zero Delay MUX Divider Select Table for proper decoding. The threshold voltage VTH = VCC/2. Internal 25kΩ pull-up. The default logic is HIGH.

Z0853606VSC010

Z0853606VSCCIO

Vendor:ZILOGPackage Cooled:305D/C:00+

1.5 V 2% 3.3-V Output Within 2 V of 1.5-V Output Under All Conditions 1.5-A Load Current Capability on 3.3-V Output 300-mA Load Current Capability on 1.5-V Output Overcurrent Protection for Both Outputs Thermally-Enhanced Packaging Concept for Efficient Heat Management Thermal Shutdown to Protect Device During Excessive Power Dissipation